1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/bitops.h>
5
6 /* ENETC device IDs */
7 #define ENETC_DEV_ID_PF 0xe100
8 #define ENETC_DEV_ID_VF 0xef00
9 #define ENETC_DEV_ID_PTP 0xee02
10
11 /* ENETC register block BAR */
12 #define ENETC_BAR_REGS 0
13
14 /** SI regs, offset: 0h */
15 #define ENETC_SIMR 0
16 #define ENETC_SIMR_EN BIT(31)
17 #define ENETC_SIMR_RSSE BIT(0)
18 #define ENETC_SICTR0 0x18
19 #define ENETC_SICTR1 0x1c
20 #define ENETC_SIPCAPR0 0x20
21 #define ENETC_SIPCAPR0_PSFP BIT(9)
22 #define ENETC_SIPCAPR0_RSS BIT(8)
23 #define ENETC_SIPCAPR0_QBV BIT(4)
24 #define ENETC_SIPCAPR0_QBU BIT(3)
25 #define ENETC_SIPCAPR1 0x24
26 #define ENETC_SITGTGR 0x30
27 #define ENETC_SIRBGCR 0x38
28 /* cache attribute registers for transactions initiated by ENETC */
29 #define ENETC_SICAR0 0x40
30 #define ENETC_SICAR1 0x44
31 #define ENETC_SICAR2 0x48
32 /* rd snoop, no alloc
33 * wr snoop, no alloc, partial cache line update for BDs and full cache line
34 * update for data
35 */
36 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
37 #define ENETC_SICAR_WR_COHERENT 0x00006727
38 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
39
40 #define ENETC_SIPMAR0 0x80
41 #define ENETC_SIPMAR1 0x84
42
43 /* VF-PF Message passing */
44 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
45 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
enetc_vsi_set_msize(u32 size)46 static inline u32 enetc_vsi_set_msize(u32 size)
47 {
48 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
49 }
50
51 #define ENETC_PSIMSGRR 0x204
52 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
53 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
54 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
55 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
56
57 #define ENETC_VSIMSGSR 0x204 /* RO */
58 #define ENETC_VSIMSGSR_MB BIT(0)
59 #define ENETC_VSIMSGSR_MS BIT(1)
60 #define ENETC_VSIMSGSNDAR0 0x210
61 #define ENETC_VSIMSGSNDAR1 0x214
62
63 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
64 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
65
66 /* SI statistics */
67 #define ENETC_SIROCT 0x300
68 #define ENETC_SIRFRM 0x308
69 #define ENETC_SIRUCA 0x310
70 #define ENETC_SIRMCA 0x318
71 #define ENETC_SITOCT 0x320
72 #define ENETC_SITFRM 0x328
73 #define ENETC_SITUCA 0x330
74 #define ENETC_SITMCA 0x338
75 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
76
77 /* Control BDR regs */
78 #define ENETC_SICBDRMR 0x800
79 #define ENETC_SICBDRSR 0x804 /* RO */
80 #define ENETC_SICBDRBAR0 0x810
81 #define ENETC_SICBDRBAR1 0x814
82 #define ENETC_SICBDRPIR 0x818
83 #define ENETC_SICBDRCIR 0x81c
84 #define ENETC_SICBDRLENR 0x820
85
86 #define ENETC_SICAPR0 0x900
87 #define ENETC_SICAPR1 0x904
88
89 #define ENETC_PSIIER 0xa00
90 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
91 #define ENETC_PSIIDR 0xa08
92 #define ENETC_SITXIDR 0xa18
93 #define ENETC_SIRXIDR 0xa28
94 #define ENETC_SIMSIVR 0xa30
95
96 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
97 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
98
99 #define ENETC_SIUEFDCR 0xe28
100
101 #define ENETC_SIRFSCAPR 0x1200
102 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
103 #define ENETC_SIRSSCAPR 0x1600
104 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
105
106 /** SI BDR sub-blocks, n = 0..7 */
107 enum enetc_bdr_type {TX, RX};
108 #define ENETC_BDR_OFF(i) ((i) * 0x200)
109 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
110 /* RX BDR reg offsets */
111 #define ENETC_RBMR 0
112 #define ENETC_RBMR_BDS BIT(2)
113 #define ENETC_RBMR_CM BIT(4)
114 #define ENETC_RBMR_VTE BIT(5)
115 #define ENETC_RBMR_EN BIT(31)
116 #define ENETC_RBSR 0x4
117 #define ENETC_RBBSR 0x8
118 #define ENETC_RBCIR 0xc
119 #define ENETC_RBBAR0 0x10
120 #define ENETC_RBBAR1 0x14
121 #define ENETC_RBPIR 0x18
122 #define ENETC_RBLENR 0x20
123 #define ENETC_RBIER 0xa0
124 #define ENETC_RBIER_RXTIE BIT(0)
125 #define ENETC_RBIDR 0xa4
126 #define ENETC_RBICR0 0xa8
127 #define ENETC_RBICR0_ICEN BIT(31)
128 #define ENETC_RBICR0_ICPT_MASK 0x1ff
129 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK)
130 #define ENETC_RBICR1 0xac
131
132 /* TX BDR reg offsets */
133 #define ENETC_TBMR 0
134 #define ENETC_TBSR_BUSY BIT(0)
135 #define ENETC_TBMR_VIH BIT(9)
136 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
137 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
138 #define ENETC_TBMR_EN BIT(31)
139 #define ENETC_TBSR 0x4
140 #define ENETC_TBBAR0 0x10
141 #define ENETC_TBBAR1 0x14
142 #define ENETC_TBPIR 0x18
143 #define ENETC_TBCIR 0x1c
144 #define ENETC_TBCIR_IDX_MASK 0xffff
145 #define ENETC_TBLENR 0x20
146 #define ENETC_TBIER 0xa0
147 #define ENETC_TBIER_TXTIE BIT(0)
148 #define ENETC_TBIDR 0xa4
149 #define ENETC_TBICR0 0xa8
150 #define ENETC_TBICR0_ICEN BIT(31)
151 #define ENETC_TBICR0_ICPT_MASK 0xf
152 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK)
153 #define ENETC_TBICR1 0xac
154
155 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
156
157 /* Port regs, offset: 1_0000h */
158 #define ENETC_PORT_BASE 0x10000
159 #define ENETC_PMR 0x0000
160 #define ENETC_PMR_EN GENMASK(18, 16)
161 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
162 #define ENETC_PMR_PSPEED_10M 0
163 #define ENETC_PMR_PSPEED_100M BIT(8)
164 #define ENETC_PMR_PSPEED_1000M BIT(9)
165 #define ENETC_PMR_PSPEED_2500M BIT(10)
166 #define ENETC_PSR 0x0004 /* RO */
167 #define ENETC_PSIPMR 0x0018
168 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
169 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
170 #define ENETC_PSIPVMR 0x001c
171 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
172 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
173 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
174 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
175 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
176 #define ENETC_PVCLCTR 0x0208
177 #define ENETC_PCVLANR1 0x0210
178 #define ENETC_PCVLANR2 0x0214
179 #define ENETC_VLAN_TYPE_C BIT(0)
180 #define ENETC_VLAN_TYPE_S BIT(1)
181 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
182 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
183 #define ENETC_PSIVLAN_EN BIT(31)
184 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
185 #define ENETC_PPAUONTR 0x0410
186 #define ENETC_PPAUOFFTR 0x0414
187 #define ENETC_PTXMBAR 0x0608
188 #define ENETC_PCAPR0 0x0900
189 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
190 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
191 #define ENETC_PCAPR1 0x0904
192 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
193 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
194 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
195 #define ENETC_PSICFGR0_VTE BIT(12)
196 #define ENETC_PSICFGR0_SIVIE BIT(14)
197 #define ENETC_PSICFGR0_ASE BIT(15)
198 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
199
200 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
201 #define ENETC_CBSE BIT(31)
202 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
203 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
204 #define ENETC_RSSHASH_KEY_SIZE 40
205 #define ENETC_PRSSCAPR 0x1404
206 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
207 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
208 #define ENETC_PSIVLANFMR 0x1700
209 #define ENETC_PSIVLANFMR_VS BIT(0)
210 #define ENETC_PRFSMR 0x1800
211 #define ENETC_PRFSMR_RFSE BIT(31)
212 #define ENETC_PRFSCAPR 0x1804
213 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
214 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
215 #define ENETC_PFPMR 0x1900
216 #define ENETC_PFPMR_PMACE BIT(1)
217 #define ENETC_EMDIO_BASE 0x1c00
218 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
219 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
220 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
221 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
222 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
223 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
224 #define ENETC_MMCSR 0x1f00
225 #define ENETC_MMCSR_LINK_FAIL BIT(31)
226 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */
227 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK)
228 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23)
229 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */
230 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21)
231 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */
232 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18)
233 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */
234 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */
235 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */
236 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK)
237 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8)
238 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */
239 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3)
240 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */
241 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */
242 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */
243 #define ENETC_MMFAECR 0x1f08
244 #define ENETC_MMFSECR 0x1f0c
245 #define ENETC_MMFAOCR 0x1f10
246 #define ENETC_MMFCRXR 0x1f14
247 #define ENETC_MMFCTXR 0x1f18
248 #define ENETC_MMHCR 0x1f1c
249 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
250
251 #define ENETC_PMAC_OFFSET 0x1000
252
253 #define ENETC_PM0_CMD_CFG 0x8008
254 #define ENETC_PM0_TX_EN BIT(0)
255 #define ENETC_PM0_RX_EN BIT(1)
256 #define ENETC_PM0_PROMISC BIT(4)
257 #define ENETC_PM0_PAUSE_IGN BIT(8)
258 #define ENETC_PM0_CMD_XGLP BIT(10)
259 #define ENETC_PM0_CMD_TXP BIT(11)
260 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
261 #define ENETC_PM0_CMD_SFD BIT(21)
262 #define ENETC_PM0_MAXFRM 0x8014
263 #define ENETC_SET_TX_MTU(val) ((val) << 16)
264 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
265 #define ENETC_PM0_RX_FIFO 0x801c
266 #define ENETC_PM0_RX_FIFO_VAL 1
267
268 #define ENETC_PM_IMDIO_BASE 0x8030
269
270 #define ENETC_PM0_PAUSE_QUANTA 0x8054
271 #define ENETC_PM0_PAUSE_THRESH 0x8064
272
273 #define ENETC_PM0_SINGLE_STEP 0x80c0
274 #define ENETC_PM0_SINGLE_STEP_CH BIT(7)
275 #define ENETC_PM0_SINGLE_STEP_EN BIT(31)
276 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
277
278 #define ENETC_PM0_IF_MODE 0x8300
279 #define ENETC_PM0_IFM_RG BIT(2)
280 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
281 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
282 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)
283 #define ENETC_PM0_IFM_SSP_1000 (2 << 13)
284 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
285 #define ENETC_PM0_IFM_SSP_10 (1 << 13)
286 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
287 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
288 #define ENETC_PM0_IFM_IFMODE_XGMII 0
289 #define ENETC_PM0_IFM_IFMODE_GMII 2
290 #define ENETC_PSIDCAPR 0x1b08
291 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
292 #define ENETC_PSFCAPR 0x1b18
293 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
294 #define ENETC_PSGCAPR 0x1b28
295 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)
296 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
297 #define ENETC_PFMCAPR 0x1b38
298 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
299
300 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
301 * Port MAC 1 to the pMAC.
302 */
303 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac))
304 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac))
305 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac))
306 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac))
307 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac))
308 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac))
309 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac))
310 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac))
311 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac))
312 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac))
313 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac))
314 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac))
315 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac))
316 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac))
317 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac))
318 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac))
319 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac))
320 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac))
321 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac))
322 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac))
323 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac))
324 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac))
325 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac))
326 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac))
327 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac))
328 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac))
329 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac))
330 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac))
331 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac))
332 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac))
333 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac))
334 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac))
335 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac))
336 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac))
337 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac))
338 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac))
339 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac))
340 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac))
341 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac))
342 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac))
343 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac))
344 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac))
345 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac))
346 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac))
347 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac))
348 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac))
349 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac))
350 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac))
351 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac))
352 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac))
353 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac))
354
355 /* Port counters */
356 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
357 #define ENETC_PBFDSIR 0x0810
358 #define ENETC_PFDMSAPR 0x0814
359 #define ENETC_UFDMF 0x1680
360 #define ENETC_MFDMF 0x1684
361 #define ENETC_PUFDVFR 0x1780
362 #define ENETC_PMFDVFR 0x1784
363 #define ENETC_PBFDVFR 0x1788
364
365 /** Global regs, offset: 2_0000h */
366 #define ENETC_GLOBAL_BASE 0x20000
367 #define ENETC_G_EIPBRR0 0x0bf8
368 #define ENETC_G_EIPBRR1 0x0bfc
369 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
370 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
371
372 /* PCI device info */
373 struct enetc_hw {
374 /* SI registers, used by all PCI functions */
375 void __iomem *reg;
376 /* Port registers, PF only */
377 void __iomem *port;
378 /* IP global registers, PF only */
379 void __iomem *global;
380 };
381
382 /* ENETC register accessors */
383
384 /* MDIO issue workaround (on LS1028A) -
385 * Due to a hardware issue, an access to MDIO registers
386 * that is concurrent with other ENETC register accesses
387 * may lead to the MDIO access being dropped or corrupted.
388 * To protect the MDIO accesses a readers-writers locking
389 * scheme is used, where the MDIO register accesses are
390 * protected by write locks to insure exclusivity, while
391 * the remaining ENETC registers are accessed under read
392 * locks since they only compete with MDIO accesses.
393 */
394 extern rwlock_t enetc_mdio_lock;
395
396 /* use this locking primitive only on the fast datapath to
397 * group together multiple non-MDIO register accesses to
398 * minimize the overhead of the lock
399 */
enetc_lock_mdio(void)400 static inline void enetc_lock_mdio(void)
401 {
402 read_lock(&enetc_mdio_lock);
403 }
404
enetc_unlock_mdio(void)405 static inline void enetc_unlock_mdio(void)
406 {
407 read_unlock(&enetc_mdio_lock);
408 }
409
410 /* use these accessors only on the fast datapath under
411 * the enetc_lock_mdio() locking primitive to minimize
412 * the overhead of the lock
413 */
enetc_rd_reg_hot(void __iomem * reg)414 static inline u32 enetc_rd_reg_hot(void __iomem *reg)
415 {
416 lockdep_assert_held(&enetc_mdio_lock);
417
418 return ioread32(reg);
419 }
420
enetc_wr_reg_hot(void __iomem * reg,u32 val)421 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val)
422 {
423 lockdep_assert_held(&enetc_mdio_lock);
424
425 iowrite32(val, reg);
426 }
427
428 /* internal helpers for the MDIO w/a */
_enetc_rd_reg_wa(void __iomem * reg)429 static inline u32 _enetc_rd_reg_wa(void __iomem *reg)
430 {
431 u32 val;
432
433 enetc_lock_mdio();
434 val = ioread32(reg);
435 enetc_unlock_mdio();
436
437 return val;
438 }
439
_enetc_wr_reg_wa(void __iomem * reg,u32 val)440 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val)
441 {
442 enetc_lock_mdio();
443 iowrite32(val, reg);
444 enetc_unlock_mdio();
445 }
446
_enetc_rd_mdio_reg_wa(void __iomem * reg)447 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg)
448 {
449 unsigned long flags;
450 u32 val;
451
452 write_lock_irqsave(&enetc_mdio_lock, flags);
453 val = ioread32(reg);
454 write_unlock_irqrestore(&enetc_mdio_lock, flags);
455
456 return val;
457 }
458
_enetc_wr_mdio_reg_wa(void __iomem * reg,u32 val)459 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val)
460 {
461 unsigned long flags;
462
463 write_lock_irqsave(&enetc_mdio_lock, flags);
464 iowrite32(val, reg);
465 write_unlock_irqrestore(&enetc_mdio_lock, flags);
466 }
467
468 #ifdef ioread64
_enetc_rd_reg64(void __iomem * reg)469 static inline u64 _enetc_rd_reg64(void __iomem *reg)
470 {
471 return ioread64(reg);
472 }
473 #else
474 /* using this to read out stats on 32b systems */
_enetc_rd_reg64(void __iomem * reg)475 static inline u64 _enetc_rd_reg64(void __iomem *reg)
476 {
477 u32 low, high, tmp;
478
479 do {
480 high = ioread32(reg + 4);
481 low = ioread32(reg);
482 tmp = ioread32(reg + 4);
483 } while (high != tmp);
484
485 return le64_to_cpu((__le64)high << 32 | low);
486 }
487 #endif
488
_enetc_rd_reg64_wa(void __iomem * reg)489 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg)
490 {
491 u64 val;
492
493 enetc_lock_mdio();
494 val = _enetc_rd_reg64(reg);
495 enetc_unlock_mdio();
496
497 return val;
498 }
499
500 /* general register accessors */
501 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg))
502 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val))
503 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
504 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
505 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off))
506 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val)
507 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off))
508 /* port register accessors - PF only */
509 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
510 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
511 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off))
512 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\
513 (hw)->port + (off), val)
514 /* global register accessors - PF only */
515 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
516 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
517 /* BDR register accessors, see ENETC_BDR() */
518 #define enetc_bdr_rd(hw, t, n, off) \
519 enetc_rd(hw, ENETC_BDR(t, n, off))
520 #define enetc_bdr_wr(hw, t, n, off, val) \
521 enetc_wr(hw, ENETC_BDR(t, n, off), val)
522 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
523 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
524 #define enetc_txbdr_wr(hw, n, off, val) \
525 enetc_bdr_wr(hw, TX, n, off, val)
526 #define enetc_rxbdr_wr(hw, n, off, val) \
527 enetc_bdr_wr(hw, RX, n, off, val)
528
529 /* Buffer Descriptors (BD) */
530 union enetc_tx_bd {
531 struct {
532 __le64 addr;
533 __le16 buf_len;
534 __le16 frm_len;
535 union {
536 struct {
537 u8 reserved[3];
538 u8 flags;
539 }; /* default layout */
540 __le32 txstart;
541 __le32 lstatus;
542 };
543 };
544 struct {
545 __le32 tstamp;
546 __le16 tpid;
547 __le16 vid;
548 u8 reserved[6];
549 u8 e_flags;
550 u8 flags;
551 } ext; /* Tx BD extension */
552 struct {
553 __le32 tstamp;
554 u8 reserved[10];
555 u8 status;
556 u8 flags;
557 } wb; /* writeback descriptor */
558 };
559
560 enum enetc_txbd_flags {
561 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
562 ENETC_TXBD_FLAGS_TSE = BIT(1),
563 ENETC_TXBD_FLAGS_W = BIT(2),
564 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */
565 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
566 ENETC_TXBD_FLAGS_EX = BIT(6),
567 ENETC_TXBD_FLAGS_F = BIT(7)
568 };
569 #define ENETC_TXBD_STATS_WIN BIT(7)
570 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
571 #define ENETC_TXBD_FLAGS_OFFSET 24
572
enetc_txbd_set_tx_start(u64 tx_start,u8 flags)573 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags)
574 {
575 u32 temp;
576
577 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) |
578 (flags << ENETC_TXBD_FLAGS_OFFSET);
579
580 return cpu_to_le32(temp);
581 }
582
enetc_clear_tx_bd(union enetc_tx_bd * txbd)583 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
584 {
585 memset(txbd, 0, sizeof(*txbd));
586 }
587
588 /* Extension flags */
589 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
590 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1)
591 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
592
593 union enetc_rx_bd {
594 struct {
595 __le64 addr;
596 u8 reserved[8];
597 } w;
598 struct {
599 __le16 inet_csum;
600 __le16 parse_summary;
601 __le32 rss_hash;
602 __le16 buf_len;
603 __le16 vlan_opt;
604 union {
605 struct {
606 __le16 flags;
607 __le16 error;
608 };
609 __le32 lstatus;
610 };
611 } r;
612 struct {
613 __le32 tstamp;
614 u8 reserved[12];
615 } ext;
616 };
617
618 #define ENETC_RXBD_LSTATUS_R BIT(30)
619 #define ENETC_RXBD_LSTATUS_F BIT(31)
620 #define ENETC_RXBD_ERR_MASK 0xff
621 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
622 #define ENETC_RXBD_FLAG_VLAN BIT(9)
623 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
624 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
625
626 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
627 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
628 #define ENETC_MAX_NUM_VFS 2
629
630 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
631 #define ENETC_CBD_STATUS_MASK 0xf
632
633 struct enetc_cmd_rfse {
634 u8 smac_h[6];
635 u8 smac_m[6];
636 u8 dmac_h[6];
637 u8 dmac_m[6];
638 __be32 sip_h[4];
639 __be32 sip_m[4];
640 __be32 dip_h[4];
641 __be32 dip_m[4];
642 u16 ethtype_h;
643 u16 ethtype_m;
644 u16 ethtype4_h;
645 u16 ethtype4_m;
646 u16 sport_h;
647 u16 sport_m;
648 u16 dport_h;
649 u16 dport_m;
650 u16 vlan_h;
651 u16 vlan_m;
652 u8 proto_h;
653 u8 proto_m;
654 u16 flags;
655 u16 result;
656 u16 mode;
657 };
658
659 #define ENETC_RFSE_EN BIT(15)
660 #define ENETC_RFSE_MODE_BD 2
661
enetc_load_primary_mac_addr(struct enetc_hw * hw,struct net_device * ndev)662 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw,
663 struct net_device *ndev)
664 {
665 u8 addr[ETH_ALEN] __aligned(4);
666
667 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
668 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
669 eth_hw_addr_set(ndev, addr);
670 }
671
672 #define ENETC_SI_INT_IDX 0
673 /* base index for Rx/Tx interrupts */
674 #define ENETC_BDR_INT_BASE_IDX 1
675
676 /* Messaging */
677
678 /* Command completion status */
679 enum enetc_msg_cmd_status {
680 ENETC_MSG_CMD_STATUS_OK,
681 ENETC_MSG_CMD_STATUS_FAIL
682 };
683
684 /* VSI-PSI command message types */
685 enum enetc_msg_cmd_type {
686 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
687 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
688 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
689 };
690
691 /* VSI-PSI command action types */
692 enum enetc_msg_cmd_action_type {
693 ENETC_MSG_CMD_MNG_ADD = 1,
694 ENETC_MSG_CMD_MNG_REMOVE
695 };
696
697 /* PSI-VSI command header format */
698 struct enetc_msg_cmd_header {
699 u16 type; /* command class type */
700 u16 id; /* denotes the specific required action */
701 };
702
703 /* Common H/W utility functions */
704
enetc_bdr_enable_rxvlan(struct enetc_hw * hw,int idx,bool en)705 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx,
706 bool en)
707 {
708 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
709
710 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
711 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val);
712 }
713
enetc_bdr_enable_txvlan(struct enetc_hw * hw,int idx,bool en)714 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx,
715 bool en)
716 {
717 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
718
719 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
720 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val);
721 }
722
enetc_set_bdr_prio(struct enetc_hw * hw,int bdr_idx,int prio)723 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
724 int prio)
725 {
726 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
727
728 val &= ~ENETC_TBMR_PRIO_MASK;
729 val |= ENETC_TBMR_SET_PRIO(prio);
730 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
731 }
732
733 enum bdcr_cmd_class {
734 BDCR_CMD_UNSPEC = 0,
735 BDCR_CMD_MAC_FILTER,
736 BDCR_CMD_VLAN_FILTER,
737 BDCR_CMD_RSS,
738 BDCR_CMD_RFS,
739 BDCR_CMD_PORT_GCL,
740 BDCR_CMD_RECV_CLASSIFIER,
741 BDCR_CMD_STREAM_IDENTIFY,
742 BDCR_CMD_STREAM_FILTER,
743 BDCR_CMD_STREAM_GCL,
744 BDCR_CMD_FLOW_METER,
745 __BDCR_CMD_MAX_LEN,
746 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
747 };
748
749 /* class 5, command 0 */
750 struct tgs_gcl_conf {
751 u8 atc; /* init gate value */
752 u8 res[7];
753 struct {
754 u8 res1[4];
755 __le16 acl_len;
756 u8 res2[2];
757 };
758 };
759
760 /* gate control list entry */
761 struct gce {
762 __le32 period;
763 u8 gate;
764 u8 res[3];
765 };
766
767 /* tgs_gcl_conf address point to this data space */
768 struct tgs_gcl_data {
769 __le32 btl;
770 __le32 bth;
771 __le32 ct;
772 __le32 cte;
773 struct gce entry[];
774 };
775
776 /* class 7, command 0, Stream Identity Entry Configuration */
777 struct streamid_conf {
778 __le32 stream_handle; /* init gate value */
779 __le32 iports;
780 u8 id_type;
781 u8 oui[3];
782 u8 res[3];
783 u8 en;
784 };
785
786 #define ENETC_CBDR_SID_VID_MASK 0xfff
787 #define ENETC_CBDR_SID_VIDM BIT(12)
788 #define ENETC_CBDR_SID_TG_MASK 0xc000
789 /* streamid_conf address point to this data space */
790 struct streamid_data {
791 union {
792 u8 dmac[6];
793 u8 smac[6];
794 };
795 u16 vid_vidm_tg;
796 };
797
798 #define ENETC_CBDR_SFI_PRI_MASK 0x7
799 #define ENETC_CBDR_SFI_PRIM BIT(3)
800 #define ENETC_CBDR_SFI_BLOV BIT(4)
801 #define ENETC_CBDR_SFI_BLEN BIT(5)
802 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
803 #define ENETC_CBDR_SFI_FMITEN BIT(7)
804 #define ENETC_CBDR_SFI_ENABLE BIT(7)
805 /* class 8, command 0, Stream Filter Instance, Short Format */
806 struct sfi_conf {
807 __le32 stream_handle;
808 u8 multi;
809 u8 res[2];
810 u8 sthm;
811 /* Max Service Data Unit or Flow Meter Instance Table index.
812 * Depending on the value of FLT this represents either Max
813 * Service Data Unit (max frame size) allowed by the filter
814 * entry or is an index into the Flow Meter Instance table
815 * index identifying the policer which will be used to police
816 * it.
817 */
818 __le16 fm_inst_table_index;
819 __le16 msdu;
820 __le16 sg_inst_table_index;
821 u8 res1[2];
822 __le32 input_ports;
823 u8 res2[3];
824 u8 en;
825 };
826
827 /* class 8, command 2 stream Filter Instance status query short format
828 * command no need structure define
829 * Stream Filter Instance Query Statistics Response data
830 */
831 struct sfi_counter_data {
832 u32 matchl;
833 u32 matchh;
834 u32 msdu_dropl;
835 u32 msdu_droph;
836 u32 stream_gate_dropl;
837 u32 stream_gate_droph;
838 u32 flow_meter_dropl;
839 u32 flow_meter_droph;
840 };
841
842 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
843 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
844 #define ENETC_CBDR_SGI_CGTST BIT(6)
845 #define ENETC_CBDR_SGI_OGTST BIT(7)
846 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
847 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
848 #define ENETC_CBDR_SGI_OEX BIT(4)
849 #define ENETC_CBDR_SGI_OEXEN BIT(5)
850 #define ENETC_CBDR_SGI_IRX BIT(6)
851 #define ENETC_CBDR_SGI_IRXEN BIT(7)
852 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
853 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
854 #define ENETC_CBDR_SGI_EN BIT(7)
855 /* class 9, command 0, Stream Gate Instance Table, Short Format
856 * class 9, command 2, Stream Gate Instance Table entry query write back
857 * Short Format
858 */
859 struct sgi_table {
860 u8 res[8];
861 u8 oipv;
862 u8 res0[2];
863 u8 ocgtst;
864 u8 res1[7];
865 u8 gset;
866 u8 oacl_len;
867 u8 res2[2];
868 u8 en;
869 };
870
871 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
872 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
873 #define ENETC_CBDR_SGI_AGTST BIT(7)
874
875 /* class 9, command 1, Stream Gate Control List, Long Format */
876 struct sgcl_conf {
877 u8 aipv;
878 u8 res[2];
879 u8 agtst;
880 u8 res1[4];
881 union {
882 struct {
883 u8 res2[4];
884 u8 acl_len;
885 u8 res3[3];
886 };
887 u8 cct[8]; /* Config change time */
888 };
889 };
890
891 #define ENETC_CBDR_SGL_IOMEN BIT(0)
892 #define ENETC_CBDR_SGL_IPVEN BIT(3)
893 #define ENETC_CBDR_SGL_GTST BIT(4)
894 #define ENETC_CBDR_SGL_IPV_MASK 0xe
895 /* Stream Gate Control List Entry */
896 struct sgce {
897 u32 interval;
898 u8 msdu[3];
899 u8 multi;
900 };
901
902 /* stream control list class 9 , cmd 1 data buffer */
903 struct sgcl_data {
904 u32 btl;
905 u32 bth;
906 u32 ct;
907 u32 cte;
908 struct sgce sgcl[];
909 };
910
911 #define ENETC_CBDR_FMI_MR BIT(0)
912 #define ENETC_CBDR_FMI_MREN BIT(1)
913 #define ENETC_CBDR_FMI_DOY BIT(2)
914 #define ENETC_CBDR_FMI_CM BIT(3)
915 #define ENETC_CBDR_FMI_CF BIT(4)
916 #define ENETC_CBDR_FMI_NDOR BIT(5)
917 #define ENETC_CBDR_FMI_OALEN BIT(6)
918 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
919
920 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
921 struct fmi_conf {
922 __le32 cir;
923 __le32 cbs;
924 __le32 eir;
925 __le32 ebs;
926 u8 conf;
927 u8 res1;
928 u8 ir_fpp;
929 u8 res2[4];
930 u8 en;
931 };
932
933 struct enetc_cbd {
934 union{
935 struct sfi_conf sfi_conf;
936 struct sgi_table sgi_table;
937 struct fmi_conf fmi_conf;
938 struct {
939 __le32 addr[2];
940 union {
941 __le32 opt[4];
942 struct tgs_gcl_conf gcl_conf;
943 struct streamid_conf sid_set;
944 struct sgcl_conf sgcl_conf;
945 };
946 }; /* Long format */
947 __le32 data[6];
948 };
949 __le16 index;
950 __le16 length;
951 u8 cmd;
952 u8 cls;
953 u8 _res;
954 u8 status_flags;
955 };
956
957 #define ENETC_CLK 400000000ULL
enetc_cycles_to_usecs(u32 cycles)958 static inline u32 enetc_cycles_to_usecs(u32 cycles)
959 {
960 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK);
961 }
962
enetc_usecs_to_cycles(u32 usecs)963 static inline u32 enetc_usecs_to_cycles(u32 usecs)
964 {
965 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL);
966 }
967
968 /* port time gating control register */
969 #define ENETC_PTGCR 0x11a00
970 #define ENETC_PTGCR_TGE BIT(31)
971 #define ENETC_PTGCR_TGPE BIT(30)
972
973 /* Port time gating capability register */
974 #define ENETC_PTGCAPR 0x11a08
975 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
976
977 /* Port time specific departure */
978 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
979 #define ENETC_TSDE BIT(31)
980
981 /* PSFP setting */
982 #define ENETC_PPSFPMR 0x11b00
983 #define ENETC_PPSFPMR_PSFPEN BIT(0)
984 #define ENETC_PPSFPMR_VS BIT(1)
985 #define ENETC_PPSFPMR_PVC BIT(2)
986 #define ENETC_PPSFPMR_PVZC BIT(3)
987