1 /*
2  * Copyright 2018-2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef DCFG_H
9 #define DCFG_H
10 
11 #include <endian.h>
12 
13 #if defined(CONFIG_CHASSIS_2)
14 #include <dcfg_lsch2.h>
15 #elif defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_3)
16 #include <dcfg_lsch3.h>
17 #endif
18 
19 #ifdef NXP_GUR_BE
20 #define gur_in32(a)		bswap32(mmio_read_32((uintptr_t)(a)))
21 #define gur_out32(a, v)		mmio_write_32((uintptr_t)(a), bswap32(v))
22 #elif defined(NXP_GUR_LE)
23 #define gur_in32(a)		mmio_read_32((uintptr_t)(a))
24 #define gur_out32(a, v)		mmio_write_32((uintptr_t)(a), v)
25 #else
26 #error Please define CCSR GUR register endianness
27 #endif
28 
29 typedef struct {
30 	union {
31 		uint32_t val;
32 		struct {
33 			uint32_t min_ver:4;
34 			uint32_t maj_ver:4;
35 #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
36 			uint32_t personality:6;
37 			uint32_t rsv1:2;
38 #elif defined(CONFIG_CHASSIS_2)
39 			uint32_t personality:8;
40 
41 #endif
42 #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
43 			uint32_t dev_id:6;
44 			uint32_t rsv2:2;
45 			uint32_t family:4;
46 #elif defined(CONFIG_CHASSIS_2)
47 			uint32_t dev_id:12;
48 #endif
49 			uint32_t mfr_id;
50 		} __packed bf;
51 		struct {
52 			uint32_t maj_min:8;
53 			uint32_t version; /* SoC version without major and minor info */
54 		} __packed bf_ver;
55 	} __packed svr_reg;
56 	bool sec_enabled;
57 	bool is_populated;
58 } soc_info_t;
59 
60 typedef struct {
61 	bool is_populated;
62 	uint8_t ocram_present;
63 	uint8_t ddrc1_present;
64 #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
65 	uint8_t ddrc2_present;
66 #endif
67 } devdisr5_info_t;
68 
69 typedef struct {
70 	uint32_t porsr1;
71 	uintptr_t g_nxp_dcfg_addr;
72 	unsigned long nxp_sysclk_freq;
73 	unsigned long nxp_ddrclk_freq;
74 	unsigned int nxp_plat_clk_divider;
75 } dcfg_init_info_t;
76 
77 
78 struct sysinfo {
79 	unsigned long freq_platform;
80 	unsigned long freq_ddr_pll0;
81 	unsigned long freq_ddr_pll1;
82 };
83 
84 int get_clocks(struct sysinfo *sys);
85 
86 /* Read the PORSR1 register */
87 uint32_t read_reg_porsr1(void);
88 
89 /*******************************************************************************
90  * Returns true if secur eboot is enabled on board
91  * mode = 0  (development mode - sb_en = 1)
92  * mode = 1 (production mode - ITS = 1)
93  ******************************************************************************/
94 bool check_boot_mode_secure(uint32_t *mode);
95 
96 const soc_info_t *get_soc_info();
97 const devdisr5_info_t *get_devdisr5_info();
98 
99 void dcfg_init(dcfg_init_info_t *dcfg_init_data);
100 bool is_sec_enabled(void);
101 
102 void error_handler(int error_code);
103 #endif /*	DCFG_H	*/
104