1 /*
2  * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3  */
4 
5 
6 /******************************************************************************
7  * @file     system.c
8  * @brief    CSI Device System Source File
9  * @version  V1.0
10  * @date     02. Oct 2018
11  ******************************************************************************/
12 
13 #include <csi_config.h>
14 #include <soc.h>
15 #include <csi_core.h>
16 #include <drv_irq.h>
17 #include <csi_kernel.h>
18 
19 /*
20 #if defined(CONFIG_KERNEL_RHINO)
21 #define CONFIG_SYSTICK_HZ RHINO_CONFIG_TICKS_PER_SECOND
22 #endif
23 */
24 
25 #ifndef CONFIG_SYSTICK_HZ
26 #define CONFIG_SYSTICK_HZ 100
27 #endif
28 
29 int g_system_clock = IHS_VALUE;
30 extern int32_t g_top_irqstack;
31 extern void irq_vectors_init(void);
32 extern void mm_heap_initialize(void);
33 
drv_get_cpu_id(void)34 int32_t drv_get_cpu_id(void)
35 {
36     return 0;
37 }
38 
39 #ifdef CONFIG_KERNEL_NONE
_system_init_for_baremetal(void)40 static void _system_init_for_baremetal(void)
41 {
42     __enable_excp_irq();
43 
44     csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, 0);    //10ms
45 
46     mm_heap_initialize();
47 }
48 
49 
50 #if 0
51 void next_jump_addr(void)
52 {
53 	__NOP();
54 	__NOP();
55 	__NOP();
56 	__NOP();
57 }
58 static void _system_jump_s_mode(void)
59 {
60 	/* set MSTATUS_MPP, MSTATUS_MPIE,  */
61 	uint64_t mstatus = __get_MSTATUS();
62 	mstatus |= (0x01 << 11);
63 	mstatus |= (0x0 << 7);
64 	__set_MSTATUS(mstatus);
65 	/* set MEPC */
66 	__set_MEPC(next_jump_addr);
67 	/* set satp 0 */
68 	/* mret */
69 	__MRET();
70 	next_jump_addr();
71 }
72 #endif
73 
74 #endif
75 
76 #ifndef CONFIG_KERNEL_NONE
_system_init_for_kernel(void)77 static void _system_init_for_kernel(void)
78 {
79     irq_vectors_init();
80 
81     csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, 0);    //10ms
82     drv_irq_enable(CORET_IRQn);
83 
84 #ifndef CONFIG_KERNEL_RHINO
85 #ifndef CONFIG_NUTTXMM_NONE
86     mm_heap_initialize();
87 #endif
88 #else
89     extern void aos_heap_set();
90     aos_heap_set();
91 #endif
92 }
93 #endif
94 
95 /**
96   * @brief  initialize the system
97   *         Initialize the psr and vbr.
98   * @param  None
99   * @return None
100   */
SystemInit(void)101 void SystemInit(void)
102 {
103     int i;
104 
105     /* enable theadisaee */
106 	uint32_t mxstatus = __get_MXSTATUS();
107 	mxstatus |= (1 << 22);
108 	__set_MXSTATUS(mxstatus);
109 
110     g_system_clock = IHS_VALUE;
111 
112     /* set PLIC_PER */
113     PLIC->PLIC_PER = 0x1;
114 
115     for (i = 0; i < 32; i++) {
116     	PLIC->PLIC_IP[i] = 0;
117     }
118     for (i = 0; i < 1023; i++) {
119     	PLIC->PLIC_H0_MCLAIM = i;
120     }
121 
122     for (i = 0; i < 1023; i++) {
123     	PLIC->PLIC_PRIO[i] = 31;
124     }
125 
126     /* set hart threshold 0, enable all interrupt */
127 	PLIC->PLIC_H0_MTH = 0;
128 
129     /* enable cache */
130     csi_dcache_enable();
131     csi_icache_enable();
132 
133     /* enable msoft interrupt */
134     uint32_t mie = __get_MIE();
135     mie |= (1 << 3);
136     __set_MIE(mie);
137     //drv_irq_enable(Machine_Software_IRQn);
138 
139     /* enable interrupt 18 */
140     PLIC->PLIC_H0_MIE[0] = 0xffffffff;
141 #ifdef CONFIG_KERNEL_NONE
142     _system_init_for_baremetal();
143 #else
144     _system_init_for_kernel();
145 #endif
146 
147     //_system_jump_s_mode();
148 }
149