1/*
2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited
3 */
4
5 /******************************************************************************
6 * @file     startup.S
7 * @brief    startup file. Should use with
8 *           GCC for CSKY Embedded Processors
9 * @version  V1.0
10 * @date     29. July 2019
11 ******************************************************************************/
12
13#include <csi_config.h>
14
15.section .vectors
16    .align  6
17    .globl  __Vectors
18    .type   __Vectors, @object
19__Vectors:
20    j   Default_Handler				/* 0 */
21    j   Stspend_Handler			/* 1 */
22    j   Default_Handler				/* 2 */
23    j   Mtspend_Handler			/* 3 */
24    j   Default_Handler				/* 4 */
25    j   Scoret_Handler			/* 5 */
26    j   Default_Handler				/* 6 */
27    j   Mcoret_Handler			/* 7 */
28    j   Default_Handler				/* 8 */
29    j   Sirq_Handler			/* 9 */
30    j   Default_Handler				/* 10 */
31    j   Default_IRQHandler			/* 11 */
32    j   Default_Handler
33    j   Default_Handler
34    j   Default_Handler
35    j   Default_Handler
36
37
38    .text
39    .align  2
40_start:
41    .text
42    .align  2
43    .globl  Reset_Handler
44    .type   Reset_Handler, %function
45Reset_Handler:
46.option push
47.option norelax
48    la      gp, __global_pointer$
49.option pop
50    /* disable ie and clear all interrupts */
51    csrw    mie, zero
52    csrw    mip, zero
53
54    /* C910 will invalid all i-cache and d-cache automatically when reset */
55    /* invalid all MMU TLB Entry */
56    sfence.vma x0,x0
57	/* setup mmu VA(0~1G) <==>  PA(0~1G) */
58    /* set SMEH, page size 1G */
59    /* set SMEH, 0x0 maps 0x0, ASID = 0 */
60    li		a0, (0x40 << 16)
61    csrw	smeh, a0
62    /* set SMEL, 0x0 maps 0x0, So = 0, C = 0, B = 0, SH = 0, D = 1, A = 1, G = 1, U = 1, XWR = 7, V = 1 */
63    li		a0, 0xFF
64    csrw	smel, a0
65    /* set SMCIR, ramdom write */
66    li		a0, 0x10000000
67    csrw	smcir, a0
68    /* set SATP mode sv39 , enable mmu */
69    li		a0, 8 << 60
70    csrw	satp, a0
71
72    /* setup mmu VA(256G~256G+1G) <==>  PA(256G~256G+1G) */
73    /* set SMEH, page size 1G */
74    /* set SMEH, 256G maps 256G */
75    li		a0, (0x40 << 16)
76    li		a1, 0x1 << (26 + 18)
77    or		a0, a0,a1
78    csrw	smeh, a0
79    /* set SMEL, 256G maps 256G */
80    li		a0, 0xFF
81    li		a1, 0x1 << (26 + 10)
82    or		a0, a0,a1
83    csrw	smel, a0
84    /* set SMCIR, ramdom write */
85    li		a0, 0x10000000
86    csrw	smcir, a0
87    /* set SATP mode sv39 , enable mmu */
88    li		a0, 8 << 60
89    csrw	satp, a0
90    sfence.vma
91
92
93
94    la      a0, __Vectors
95    li	    a1, 0x1
96    or	    a0, a0,a1
97    csrw    mtvec, a0
98
99#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906D==1))|| (CONFIG_CPU_C910D==1)
100    li      a0, 0x2000
101    csrs    mstatus, a0
102#endif
103
104#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906D==1))
105    la      a0, __Vectors
106    csrw    mtvt, a0
107#endif
108
109    la      sp, g_top_irqstack
110
111    /* Load data section */
112    la      a0, __erodata
113    la      a1, __data_start__
114    la      a2, __data_end__
115    bgeu    a1, a2, 2f
1161:
117    ld      t0, (a0)
118    sd      t0, (a1)
119    addi    a0, a0, 4
120    addi    a1, a1, 4
121    bltu    a1, a2, 1b
1222:
123
124    /* Clear bss section */
125    la      a0, __bss_start__
126    la      a1, __bss_end__
127    bgeu    a0, a1, 2f
1281:
129    sd      zero, (a0)
130    addi    a0, a0, 4
131    bltu    a0, a1, 1b
1322:
133
134#ifndef __NO_SYSTEM_INIT
135    jal     SystemInit
136#endif
137
138#ifndef __NO_BOARD_INIT
139    jal     board_pre_init
140#endif
141
142    jal     main
143
144    .size   Reset_Handler, . - Reset_Handler
145
146__exit:
147    j      __exit
148
149.section .bss
150    .align  3
151    .global g_base_irqstack
152    .global g_top_irqstack
153g_base_irqstack:
154    .space CONFIG_ARCH_INTERRUPTSTACK
155g_top_irqstack:
156