1 /*
2 * Copyright 2018-2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <caam.h>
11 #include <cassert.h>
12 #include <cci.h>
13 #include <common/debug.h>
14 #include <dcfg.h>
15 #ifdef I2C_INIT
16 #include <i2c.h>
17 #endif
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <ls_interconnect.h>
21 #ifdef POLICY_FUSE_PROVISION
22 #include <nxp_gpio.h>
23 #endif
24 #if TRUSTED_BOARD_BOOT
25 #include <nxp_smmu.h>
26 #endif
27 #include <nxp_timer.h>
28 #include <plat_console.h>
29 #include <plat_gic.h>
30 #include <plat_tzc380.h>
31 #include <scfg.h>
32 #if defined(NXP_SFP_ENABLED)
33 #include <sfp.h>
34 #endif
35
36 #include <errata.h>
37 #include <ns_access.h>
38 #ifdef CONFIG_OCRAM_ECC_EN
39 #include <ocram.h>
40 #endif
41 #include <plat_common.h>
42 #include <platform_def.h>
43 #include <soc.h>
44
45 static dcfg_init_info_t dcfg_init_data = {
46 .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
47 .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
48 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
49 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
50 };
51
52
53 /* Function to return the SoC SYS CLK */
get_sys_clk(void)54 unsigned int get_sys_clk(void)
55 {
56 return NXP_SYSCLK_FREQ;
57 }
58
59 /*
60 * Function returns the base counter frequency
61 * after reading the first entry at CNTFID0 (0x20 offset).
62 *
63 * Function is used by:
64 * 1. ARM common code for PSCI management.
65 * 2. ARM Generic Timer init.
66 *
67 */
plat_get_syscnt_freq2(void)68 unsigned int plat_get_syscnt_freq2(void)
69 {
70 unsigned int counter_base_frequency;
71
72 counter_base_frequency = get_sys_clk()/4;
73
74 return counter_base_frequency;
75 }
76
77 #ifdef IMAGE_BL2
78
79 static struct soc_type soc_list[] = {
80 SOC_ENTRY(LS1023A, LS1023A, 1, 2),
81 SOC_ENTRY(LS1023AE, LS1023AE, 1, 2),
82 SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2),
83 SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2),
84 SOC_ENTRY(LS1043A, LS1043A, 1, 4),
85 SOC_ENTRY(LS1043AE, LS1043AE, 1, 4),
86 SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4),
87 SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4),
88 };
89
90 #ifdef POLICY_FUSE_PROVISION
91 static gpio_init_info_t gpio_init_data = {
92 .gpio1_base_addr = NXP_GPIO1_ADDR,
93 .gpio2_base_addr = NXP_GPIO2_ADDR,
94 .gpio3_base_addr = NXP_GPIO3_ADDR,
95 .gpio4_base_addr = NXP_GPIO4_ADDR,
96 };
97 #endif
98
99 /*
100 * Function to set the base counter frequency at
101 * the first entry of the Frequency Mode Table,
102 * at CNTFID0 (0x20 offset).
103 *
104 * Set the value of the pirmary core register cntfrq_el0.
105 */
set_base_freq_CNTFID0(void)106 static void set_base_freq_CNTFID0(void)
107 {
108 /*
109 * Below register specifies the base frequency of the system counter.
110 * As per NXP Board Manuals:
111 * The system counter always works with SYS_REF_CLK/4 frequency clock.
112 *
113 */
114 unsigned int counter_base_frequency = get_sys_clk()/4;
115
116 /*
117 * Setting the frequency in the Frequency modes table.
118 *
119 * Note: The value for ls1046ardb board at this offset
120 * is not RW as stated. This offset have the
121 * fixed value of 100000400 Hz.
122 *
123 * The below code line has no effect.
124 * Keeping it for other platforms where it has effect.
125 */
126 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
127
128 write_cntfrq_el0(counter_base_frequency);
129 }
130
soc_preload_setup(void)131 void soc_preload_setup(void)
132 {
133
134 }
135
136 /*******************************************************************************
137 * This function implements soc specific erratas
138 * This is called before DDR is initialized or MMU is enabled
139 ******************************************************************************/
soc_early_init(void)140 void soc_early_init(void)
141 {
142 uint8_t num_clusters, cores_per_cluster;
143 dram_regions_info_t *dram_regions_info = get_dram_regions_info();
144
145 #ifdef CONFIG_OCRAM_ECC_EN
146 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
147 #endif
148 dcfg_init(&dcfg_init_data);
149 #ifdef POLICY_FUSE_PROVISION
150 gpio_init(&gpio_init_data);
151 sec_init(NXP_CAAM_ADDR);
152 #endif
153 #if LOG_LEVEL > 0
154 /* Initialize the console to provide early debug support */
155
156 plat_console_init(NXP_CONSOLE_ADDR,
157 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
158 #endif
159 set_base_freq_CNTFID0();
160
161 /* Enable snooping on SEC read and write transactions */
162 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
163 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
164
165 /*
166 * Initialize Interconnect for this cluster during cold boot.
167 * No need for locks as no other CPU is active.
168 */
169 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
170
171 /*
172 * Enable Interconnect coherency for the primary CPU's cluster.
173 */
174 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
175 plat_ls_interconnect_enter_coherency(num_clusters);
176
177 #if TRUSTED_BOARD_BOOT
178 uint32_t mode;
179
180 sfp_init(NXP_SFP_ADDR);
181 /*
182 * For secure boot disable SMMU.
183 * Later when platform security policy comes in picture,
184 * this might get modified based on the policy
185 */
186 if (check_boot_mode_secure(&mode) == true) {
187 bypass_smmu(NXP_SMMU_ADDR);
188 }
189
190 /*
191 * For Mbedtls currently crypto is not supported via CAAM
192 * enable it when that support is there. In tbbr.mk
193 * the CAAM_INTEG is set as 0.
194 */
195
196 #ifndef MBEDTLS_X509
197 /* Initialize the crypto accelerator if enabled */
198 if (is_sec_enabled() == false) {
199 INFO("SEC is disabled.\n");
200 } else {
201 sec_init(NXP_CAAM_ADDR);
202 }
203 #endif
204 #elif defined(POLICY_FUSE_PROVISION)
205 gpio_init(&gpio_init_data);
206 sfp_init(NXP_SFP_ADDR);
207 sec_init(NXP_CAAM_ADDR);
208 #endif
209
210 soc_errata();
211
212 /*
213 * Initialize system level generic timer for Layerscape Socs.
214 */
215 delay_timer_init(NXP_TIMER_ADDR);
216
217 #ifdef DDR_INIT
218 i2c_init(NXP_I2C_ADDR);
219 dram_regions_info->total_dram_size = init_ddr();
220 #endif
221 }
222
soc_bl2_prepare_exit(void)223 void soc_bl2_prepare_exit(void)
224 {
225 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
226 set_sfp_wr_disable();
227 #endif
228 }
229
230 /*****************************************************************************
231 * This function returns the boot device based on RCW_SRC
232 ****************************************************************************/
get_boot_dev(void)233 enum boot_device get_boot_dev(void)
234 {
235 enum boot_device src = BOOT_DEVICE_NONE;
236 uint32_t porsr1;
237 uint32_t rcw_src, val;
238
239 porsr1 = read_reg_porsr1();
240
241 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
242
243 val = rcw_src & RCW_SRC_NAND_MASK;
244
245 if (val == RCW_SRC_NAND_VAL) {
246 val = rcw_src & NAND_RESERVED_MASK;
247 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
248 src = BOOT_DEVICE_IFC_NAND;
249 INFO("RCW BOOT SRC is IFC NAND\n");
250 }
251 } else {
252 /* RCW SRC NOR */
253 val = rcw_src & RCW_SRC_NOR_MASK;
254 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
255 src = BOOT_DEVICE_IFC_NOR;
256 INFO("RCW BOOT SRC is IFC NOR\n");
257 } else {
258 switch (rcw_src) {
259 case QSPI_VAL1:
260 case QSPI_VAL2:
261 src = BOOT_DEVICE_QSPI;
262 INFO("RCW BOOT SRC is QSPI\n");
263 break;
264 case SD_VAL:
265 src = BOOT_DEVICE_EMMC;
266 INFO("RCW BOOT SRC is SD/EMMC\n");
267 break;
268 default:
269 src = BOOT_DEVICE_NONE;
270 }
271 }
272 }
273
274 return src;
275 }
276
277 /* This function sets up access permissions on memory regions */
soc_mem_access(void)278 void soc_mem_access(void)
279 {
280 struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION];
281 int dram_idx, index = 0U;
282 dram_regions_info_t *info_dram_regions = get_dram_regions_info();
283
284 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
285 dram_idx++) {
286 if (info_dram_regions->region[dram_idx].size == 0) {
287 ERROR("DDR init failure, or");
288 ERROR("DRAM regions not populated correctly.\n");
289 break;
290 }
291
292 index = populate_tzc380_reg_list(tzc380_reg_list,
293 dram_idx, index,
294 info_dram_regions->region[dram_idx].addr,
295 info_dram_regions->region[dram_idx].size,
296 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
297 }
298
299 mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list);
300
301 /* Configure CSU secure access register to disable TZASC bypass mux */
302 mmio_write_32((uintptr_t)(NXP_CSU_ADDR +
303 CSU_SEC_ACCESS_REG_OFFSET),
304 bswap32(TZASC_BYPASS_MUX_DISABLE));
305 }
306
307
308 #else
309 const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
310
311 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
312 assert_invalid_ls1043_cluster_count);
313
314 /* This function returns the SoC topology */
plat_get_power_domain_tree_desc(void)315 const unsigned char *plat_get_power_domain_tree_desc(void)
316 {
317
318 return _power_domain_tree_desc;
319 }
320
321 /*
322 * This function returns the core count within the cluster corresponding to
323 * `mpidr`.
324 */
plat_ls_get_cluster_core_count(u_register_t mpidr)325 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
326 {
327 return CORES_PER_CLUSTER;
328 }
329
soc_early_platform_setup2(void)330 void soc_early_platform_setup2(void)
331 {
332 dcfg_init(&dcfg_init_data);
333 /* Initialize system level generic timer for Socs */
334 delay_timer_init(NXP_TIMER_ADDR);
335
336 #if LOG_LEVEL > 0
337 /* Initialize the console to provide early debug support */
338 plat_console_init(NXP_CONSOLE_ADDR,
339 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
340 #endif
341 }
342
343 /*
344 * For LS1043a rev1.0, GIC base address align with 4k.
345 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
346 * is set, GIC base address align with 4K, or else align
347 * with 64k.
348 */
get_gic_offset(uint32_t * gicc_base,uint32_t * gicd_base)349 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
350 {
351 uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET);
352 uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR +
353 SCFG_GIC400_ADDR_ALIGN_OFFSET);
354 uint32_t val;
355
356 val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
357
358 if ((val & 0xff) == REV1_1) {
359 val = be32toh(mmio_read_32((uintptr_t)gic_align));
360 if (val & (1L << GIC_ADDR_BIT)) {
361 *gicc_base = NXP_GICC_4K_ADDR;
362 *gicd_base = NXP_GICD_4K_ADDR;
363 } else {
364 *gicc_base = NXP_GICC_64K_ADDR;
365 *gicd_base = NXP_GICD_64K_ADDR;
366 }
367 } else {
368 *gicc_base = NXP_GICC_4K_ADDR;
369 *gicd_base = NXP_GICD_4K_ADDR;
370 }
371 }
372
soc_platform_setup(void)373 void soc_platform_setup(void)
374 {
375 /* Initialize the GIC driver, cpu and distributor interfaces */
376 static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
377 /*
378 * On a GICv2 system, the Group 1 secure interrupts are treated
379 * as Group 0 interrupts.
380 */
381 static interrupt_prop_t ls_interrupt_props[] = {
382 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
383 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
384 };
385 static uint32_t gicc_base, gicd_base;
386
387 get_gic_offset(&gicc_base, &gicd_base);
388 plat_ls_gic_driver_init(gicd_base, gicc_base,
389 PLATFORM_CORE_COUNT,
390 ls_interrupt_props,
391 ARRAY_SIZE(ls_interrupt_props),
392 target_mask_array);
393
394 plat_ls_gic_init();
395 enable_init_timer();
396 }
397
398 /* This function initializes the soc from the BL31 module */
soc_init(void)399 void soc_init(void)
400 {
401 /* low-level init of the soc */
402 soc_init_lowlevel();
403 _init_global_data();
404 soc_init_percpu();
405 _initialize_psci();
406
407 /*
408 * Initialize the interconnect during cold boot.
409 * No need for locks as no other CPU is active.
410 */
411 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
412
413 /*
414 * Enable coherency in interconnect for the primary CPU's cluster.
415 * Earlier bootloader stages might already do this but we can't
416 * assume so. No harm in executing this code twice.
417 */
418 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
419
420 /* Init CSU to enable non-secure access to peripherals */
421 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
422
423 /* Initialize the crypto accelerator if enabled */
424 if (is_sec_enabled() == false) {
425 INFO("SEC is disabled.\n");
426 } else {
427 sec_init(NXP_CAAM_ADDR);
428 }
429 }
430
soc_runtime_setup(void)431 void soc_runtime_setup(void)
432 {
433
434 }
435 #endif
436