1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __IMX_PM_H 7 #define __IMX_PM_H 8 9 #include <stdint.h> 10 11 #define MX7_DDRC_NUM 32 12 #define MX7_DDRC_PHY_NUM 16 13 14 #define SUSPEND_OCRAM_SIZE 0x1000 15 #define LOWPOWER_IDLE_OCRAM_SIZE 0x1000 16 17 #define SUSPEND_OCRAM_OFFSET 0x0 18 #define LOWPOWER_IDLE_OCRAM_OFFSET 0x1000 19 20 #ifndef __ASSEMBLER__ 21 #include <sm/sm.h> 22 23 /* The structure is used for suspend and low power idle */ 24 struct imx7_pm_info { 25 uint32_t m4_reserve0; 26 uint32_t m4_reserve1; 27 uint32_t m4_reserve2; 28 vaddr_t va_base; /* va of pm_info */ 29 paddr_t pa_base; /* pa of pm_info */ 30 uintptr_t entry; 31 paddr_t tee_resume; 32 uint32_t ddr_type; 33 uint32_t pm_info_size; 34 paddr_t ddrc_pa_base; 35 vaddr_t ddrc_va_base; 36 paddr_t ddrc_phy_pa_base; 37 vaddr_t ddrc_phy_va_base; 38 paddr_t src_pa_base; 39 vaddr_t src_va_base; 40 paddr_t iomuxc_gpr_pa_base; 41 vaddr_t iomuxc_gpr_va_base; 42 paddr_t ccm_pa_base; 43 vaddr_t ccm_va_base; 44 paddr_t gpc_pa_base; 45 vaddr_t gpc_va_base; 46 paddr_t snvs_pa_base; 47 vaddr_t snvs_va_base; 48 paddr_t anatop_pa_base; 49 vaddr_t anatop_va_base; 50 paddr_t lpsr_pa_base; 51 vaddr_t lpsr_va_base; 52 paddr_t gic_pa_base; 53 vaddr_t gic_va_base; 54 uint32_t ttbr0; 55 uint32_t ttbr1; 56 uint32_t num_online_cpus; 57 uint32_t num_lpi_cpus; 58 uint32_t val; 59 uint32_t flag0; 60 uint32_t flag1; 61 uint32_t ddrc_num; 62 uint32_t ddrc_val[MX7_DDRC_NUM][2]; 63 uint32_t ddrc_phy_num; 64 uint32_t ddrc_phy_val[MX7_DDRC_NUM][2]; 65 } __aligned(8); 66 67 struct suspend_save_regs { 68 uint32_t irq[3]; 69 uint32_t fiq[3]; 70 uint32_t und[3]; 71 uint32_t abt[3]; 72 uint32_t mon[3]; 73 } __aligned(8); 74 75 struct imx7_pm_data { 76 uint32_t ddr_type; 77 uint32_t ddrc_num; 78 uint32_t (*ddrc_offset)[2]; 79 uint32_t ddrc_phy_num; 80 uint32_t (*ddrc_phy_offset)[2]; 81 }; 82 83 void imx7_suspend(struct imx7_pm_info *info); 84 void imx7_resume(void); 85 void ca7_cpu_resume(void); 86 int imx7_suspend_init(void); 87 int pm_imx7_iram_tbl_init(void); 88 int imx7_cpu_suspend(uint32_t power_state, uintptr_t entry, 89 uint32_t context_id, struct sm_nsec_ctx *nsec); 90 int imx7d_lowpower_idle(uint32_t power_state, uintptr_t entry, 91 uint32_t context_id, struct sm_nsec_ctx *nsec); 92 void imx7d_low_power_idle(struct imx7_pm_info *info); 93 int imx7d_cpuidle_init(void); 94 void v7_cpu_resume(void); 95 #endif 96 97 #endif 98