1 /*
2 * Copyright 2021 The Hafnium Authors.
3 *
4 * Use of this source code is governed by a BSD-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/BSD-3-Clause.
7 */
8
9 #include "hf/cpu.h"
10 #include "hf/dlog.h"
11 #include "hf/io.h"
12 #include "hf/panic.h"
13 #include "hf/plat/interrupts.h"
14 #include "hf/static_assert.h"
15 #include "hf/types.h"
16
17 #include "msr.h"
18
19 #define BIT_32(nr) (UINT32_C(1) << (nr))
20
21 #define MPIDR_AFFINITY_MASK (0xff00ffffff)
22 #define MPIDR_AFFLVL_MASK (0xff)
23 #define MPIDR_AFF0_SHIFT (0)
24 #define MPIDR_AFF1_SHIFT (8)
25 #define MPIDR_AFF2_SHIFT (16)
26 #define MPIDR_AFF3_SHIFT (32)
27 #define RDIST_AFF3_SHIFT (56)
28 #define RDIST_AFF2_SHIFT (48)
29 #define RDIST_AFF1_SHIFT (40)
30 #define RDIST_AFF0_SHIFT (32)
31
32 /* Mask for the configuration field common to all GIC interfaces */
33 #define GIC_CFG_MASK (0x3)
34
35 /**
36 * Common GIC Distributor interface register offsets
37 */
38 #define GICD_CTLR (0x0)
39 #define GICD_TYPER (0x4)
40 #define GICD_IIDR (0x8)
41 #define GICD_IGROUPR (0x80)
42 #define GICD_ISENABLER (0x100)
43 #define GICD_ICENABLER (0x180)
44 #define GICD_ISPENDR (0x200)
45 #define GICD_ICPENDR (0x280)
46 #define GICD_ISACTIVER (0x300)
47 #define GICD_ICACTIVER (0x380)
48 #define GICD_IPRIORITYR (0x400)
49 #define GICD_ICFGR (0xc00)
50 #define GICD_NSACR (0xe00)
51
52 /* GICD_CTLR bit definitions */
53 #define CTLR_ENABLE_G0_SHIFT 0
54 #define CTLR_ENABLE_G0_MASK (0x1)
55 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
56
57 /* Common GIC Distributor interface register constants. */
58 #define PIDR2_ARCH_REV_SHIFT 4
59 #define PIDR2_ARCH_REV_MASK 0xf
60
61 /* GIC revision as reported by PIDR2.ArchRev register field */
62 #define ARCH_REV_GICV3 3
63 #define ARCH_REV_GICV4 4
64
65 #define IGROUPR_SHIFT 5
66 #define ISENABLER_SHIFT 5
67 #define ICENABLER_SHIFT ISENABLER_SHIFT
68 #define ISPENDR_SHIFT 5
69 #define ICPENDR_SHIFT ISPENDR_SHIFT
70 #define ISACTIVER_SHIFT 5
71 #define ICACTIVER_SHIFT ISACTIVER_SHIFT
72 #define IPRIORITYR_SHIFT 2
73 #define ITARGETSR_SHIFT 2
74 #define ICFGR_SHIFT 4
75 #define NSACR_SHIFT 4
76
77 #define GIC_PRI_MASK (0xff)
78
79 /**
80 * GICv3 and 3.1 specific Distributor interface register offsets and constants
81 */
82 #define GICD_TYPER2 (0x0c)
83 #define GICD_STATUSR (0x10)
84 #define GICD_SETSPI_NSR (0x40)
85 #define GICD_CLRSPI_NSR (0x48)
86 #define GICD_SETSPI_SR (0x50)
87 #define GICD_CLRSPI_SR (0x58)
88 #define GICD_IGRPMODR (0xd00)
89 #define GICD_IGROUPRE (0x1000)
90 #define GICD_ISENABLERE (0x1200)
91 #define GICD_ICENABLERE (0x1400)
92 #define GICD_ISPENDRE (0x1600)
93 #define GICD_ICPENDRE (0x1800)
94 #define GICD_ISACTIVERE (0x1a00)
95 #define GICD_ICACTIVERE (0x1c00)
96 #define GICD_IPRIORITYRE (0x2000)
97 #define GICD_ICFGRE (0x3000)
98 #define GICD_IGRPMODRE (0x3400)
99 #define GICD_NSACRE (0x3600)
100
101 /**
102 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID
103 * and n >= 32, making the effective offset as 0x6100
104 */
105 #define GICD_IROUTER (0x6000)
106 #define GICD_IROUTERE (0x8000)
107
108 #define GICD_PIDR2_GICV3 (0xffe8)
109
110 #define IGRPMODR_SHIFT 5
111
112 /* GICD_CTLR bit definitions */
113 #define CTLR_ENABLE_G1NS_SHIFT 1
114 #define CTLR_ENABLE_G1S_SHIFT 2
115 #define CTLR_ARE_S_SHIFT 4
116 #define CTLR_ARE_NS_SHIFT 5
117 #define CTLR_DS_SHIFT 6
118 #define CTLR_E1NWF_SHIFT 7
119 #define GICD_CTLR_RWP_SHIFT 31
120
121 #define CTLR_ENABLE_G1NS_MASK (0x1)
122 #define CTLR_ENABLE_G1S_MASK (0x1)
123 #define CTLR_ARE_S_MASK (0x1)
124 #define CTLR_ARE_NS_MASK (0x1)
125 #define CTLR_DS_MASK (0x1)
126 #define CTLR_E1NWF_MASK (0x1)
127 #define GICD_CTLR_RWP_MASK (0x1)
128
129 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
130 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
131 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
132 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
133 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
134 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
135 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
136
137 /* GICD_IROUTER shifts and masks */
138 #define IROUTER_SHIFT 0
139 #define IROUTER_IRM_SHIFT 31
140 #define IROUTER_IRM_MASK (0x1)
141
142 #define GICV3_IRM_PE (0)
143 #define GICV3_IRM_ANY (1)
144
145 #define NUM_OF_DIST_REGS 30
146
147 /* GICD_TYPER shifts and masks */
148 #define TYPER_ESPI (1 << 8)
149 #define TYPER_DVIS (1 << 18)
150 #define TYPER_ESPI_RANGE_MASK (0x1f)
151 #define TYPER_ESPI_RANGE_SHIFT (27)
152 #define TYPER_ESPI_RANGE (TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
153
154 /**
155 * Common GIC Redistributor interface registers & constants
156 */
157 #define GICR_SGIBASE_OFFSET (65536) /* 64 KB */
158 #define GICR_CTLR (0x0)
159 #define GICR_IIDR (0x04)
160 #define GICR_TYPER (0x08)
161 #define GICR_STATUSR (0x10)
162 #define GICR_WAKER (0x14)
163 #define GICR_PROPBASER (0x70)
164 #define GICR_PENDBASER (0x78)
165 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + (0x80))
166 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + (0x100))
167 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + (0x180))
168 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + (0x200))
169 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + (0x280))
170 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + (0x300))
171 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + (0x380))
172 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + (0x400))
173 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + (0xc00))
174 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + (0xc04))
175 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + (0xd00))
176 #define GICR_NSACR (GICR_SGIBASE_OFFSET + (0xe00))
177
178 #define GICR_IGROUPR GICR_IGROUPR0
179 #define GICR_ISENABLER GICR_ISENABLER0
180 #define GICR_ICENABLER GICR_ICENABLER0
181 #define GICR_ISPENDR GICR_ISPENDR0
182 #define GICR_ICPENDR GICR_ICPENDR0
183 #define GICR_ISACTIVER GICR_ISACTIVER0
184 #define GICR_ICACTIVER GICR_ICACTIVER0
185 #define GICR_ICFGR GICR_ICFGR0
186 #define GICR_IGRPMODR GICR_IGRPMODR0
187
188 /* GICR_CTLR bit definitions */
189 #define GICR_CTLR_UWP_SHIFT 31
190 #define GICR_CTLR_UWP_MASK (0x1)
191 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
192 #define GICR_CTLR_RWP_SHIFT 3
193 #define GICR_CTLR_RWP_MASK (0x1)
194 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
195 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
196
197 /**
198 * GICv3 and 3.1 CPU interface registers & constants
199 */
200 /* ICC_SRE bit definitions */
201 #define ICC_SRE_EN_BIT BIT_32(3)
202 #define ICC_SRE_DIB_BIT BIT_32(2)
203 #define ICC_SRE_DFB_BIT BIT_32(1)
204 #define ICC_SRE_SRE_BIT BIT_32(0)
205
206 /* ICC_IGRPEN1_EL3 bit definitions */
207 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
208 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
209
210 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
211 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
212
213 /* ICC_IGRPEN0_EL1 bit definitions */
214 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
215 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
216
217 /* ICC_HPPIR0_EL1 bit definitions */
218 #define HPPIR0_EL1_INTID_SHIFT 0
219 #define HPPIR0_EL1_INTID_MASK (0xffffff)
220
221 /* ICC_HPPIR1_EL1 bit definitions */
222 #define HPPIR1_EL1_INTID_SHIFT 0
223 #define HPPIR1_EL1_INTID_MASK (0xffffff)
224
225 /* ICC_IAR0_EL1 bit definitions */
226 #define IAR0_EL1_INTID_SHIFT 0
227 #define IAR0_EL1_INTID_MASK (0xffffff)
228
229 /* ICC_IAR1_EL1 bit definitions */
230 #define IAR1_EL1_INTID_SHIFT 0
231 #define IAR1_EL1_INTID_MASK (0xffffff)
232
233 /* ICC SGI macros */
234 #define SGIR_TGT_SHIFT 0
235 #define SGIR_TGT_MASK 0xffff
236 #define SGIR_AFF1_SHIFT 16
237 #define SGIR_INTID_SHIFT 24
238 #define SGIR_INTID_MASK 0xf
239 #define SGIR_AFF2_SHIFT 32
240 #define SGIR_IRM_SHIFT 40
241 #define SGIR_IRM_MASK 0x1
242 #define SGIR_AFF3_SHIFT 48
243 #define SGIR_AFF_MASK 0xff
244
245 #define SGIR_IRM_TO_AFF (0)
246
247 /**
248 * GICv3 and 3.1 miscellaneous definitions
249 */
250 /* Interrupt group definitions */
251 #define INTR_GROUP1S (0)
252 #define INTR_GROUP0 (1)
253 #define INTR_GROUP1NS (2)
254
255 /* Interrupt IDs reported by the HPPIR and IAR registers */
256 #define PENDING_G1S_INTID (1020)
257 #define PENDING_G1NS_INTID (8192)
258
259 /* Constant to categorize LPI interrupt */
260 #define MIN_LPI_ID (8192)
261
262 /* GICv3 can only target up to 16 PEs with SGI */
263 #define GICV3_MAX_SGI_TARGETS (16)
264
265 /* PPIs INTIDs 16-31 */
266 #define MAX_PPI_ID (31)
267 #define MIN_SPI_ID (32)
268 #define MAX_SPI_ID (1019)
269
270 #if GIC_EXT_INTID
271
272 /* GICv3.1 extended PPIs INTIDs 1056-1119 */
273 #define MIN_EPPI_ID (1056)
274 #define MAX_EPPI_ID (1119)
275
276 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */
277 #define MIN_ESPI_ID (4096)
278 #define MAX_ESPI_ID (5119)
279
280 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
281 #define IS_SGI_PPI(id) \
282 (((id) <= MAX_PPI_ID) || \
283 (((id) >= MIN_EPPI_ID) && ((id) <= MAX_EPPI_ID)))
284
285 /* SPIs: 32-1019, ESPIs: 4096-5119 */
286 #define IS_SPI(id) \
287 ((((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID)) || \
288 (((id) >= MIN_ESPI_ID) && ((id) <= MAX_ESPI_ID)))
289 #else /* GICv3 */
290 /* SGIs: 0-15, PPIs: 16-31 */
291 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID)
292
293 /* SPIs: 32-1019 */
294 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID))
295
296 #endif /* GIC_EXT_INTID */
297
298 /**
299 * GICv3 private macro definitions
300 */
301
302 /* Constants to indicate the status of the RWP bit */
303 #define RWP_TRUE (1)
304 #define RWP_FALSE (0)
305
306 /* Calculate GIC register bit number corresponding to its interrupt ID */
307 #define BIT_NUM(REG, id) ((id) & ((1U << REG##R_SHIFT) - 1U))
308
309 /*
310 * Calculate 8, 32 and 64-bit GICD register offset
311 * corresponding to its interrupt ID
312 */
313 #if GIC_EXT_INTID
314 /* GICv3.1 */
315 #define GICD_OFFSET_8(REG, id) \
316 (((id) <= MAX_SPI_ID) ? GICD_##REG##R + (uintptr_t)(id) \
317 : GICD_##REG##RE + (uintptr_t)(id)-MIN_ESPI_ID)
318
319 #define GICD_OFFSET(REG, id) \
320 (((id) <= MAX_SPI_ID) \
321 ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) \
322 : GICD_##REG##RE + \
323 ((((uintptr_t)(id)-MIN_ESPI_ID) >> REG##R_SHIFT) \
324 << 2))
325
326 #define GICD_OFFSET_64(REG, id) \
327 (((id) <= MAX_SPI_ID) \
328 ? GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) \
329 : GICD_##REG##RE + \
330 ((((uintptr_t)(id)-MIN_ESPI_ID) >> REG##R_SHIFT) \
331 << 3))
332
333 #else /* GICv3 */
334 #define GICD_OFFSET_8(REG, id) (GICD_##REG##R + (uintptr_t)(id))
335
336 #define GICD_OFFSET(REG, id) \
337 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
338
339 #define GICD_OFFSET_64(REG, id) \
340 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
341 #endif /* GIC_EXT_INTID */
342
343 /*
344 * Read/Write 8, 32 and 64-bit GIC Distributor register
345 * corresponding to its interrupt ID
346 */
347 #define GICD_READ(REG, base, id) \
348 io_read32(IO32_C((base) + GICD_OFFSET(REG, (id))))
349
350 #define GICD_READ_64(REG, base, id) \
351 io_read64(IO64_C((base) + GICD_OFFSET_64(REG, (id))))
352
353 #define GICD_WRITE_8(REG, base, id, val) \
354 io_write8(IO8_C((base) + GICD_OFFSET_8(REG, (id))), (val))
355
356 #define GICD_WRITE(REG, base, id, val) \
357 io_write32(IO32_C((base) + GICD_OFFSET(REG, (id)), (val)))
358
359 #define GICD_WRITE_64(REG, base, id, val) \
360 io_write64(IO64_C((base) + GICD_OFFSET_64(REG, (id))), (val))
361
362 /*
363 * Bit operations on GIC Distributor register corresponding
364 * to its interrupt ID
365 */
366 /* Get bit in GIC Distributor register */
367 #define GICD_GET_BIT(REG, base, id) \
368 ((io_read32(IO32_C((base) + GICD_OFFSET(REG, (id)))) >> \
369 BIT_NUM(REG, (id))) & \
370 1U)
371
372 /* Set bit in GIC Distributor register */
373 #define GICD_SET_BIT(REG, base, id) \
374 io_setbits32(IO32_C((base) + GICD_OFFSET(REG, (id))), \
375 ((uint32_t)1 << BIT_NUM(REG, (id))))
376
377 /* Clear bit in GIC Distributor register */
378 #define GICD_CLR_BIT(REG, base, id) \
379 io_clrbits32(IO32_C((base) + GICD_OFFSET(REG, (id))), \
380 ((uint32_t)1 << BIT_NUM(REG, (id))))
381
382 /* Write bit in GIC Distributor register */
383 #define GICD_WRITE_BIT(REG, base, id) \
384 io_write32(IO32_C((base) + GICD_OFFSET(REG, (id))), \
385 ((uint32_t)1 << BIT_NUM(REG, (id))))
386
387 /*
388 * Calculate 8 and 32-bit GICR register offset
389 * corresponding to its interrupt ID
390 */
391 #if GIC_EXT_INTID
392 /* GICv3.1 */
393 #define GICR_OFFSET_8(REG, id) \
394 (((id) <= MAX_PPI_ID) ? GICR_##REG##R + (uintptr_t)(id) \
395 : GICR_##REG##R + (uintptr_t)(id) - \
396 (MIN_EPPI_ID - MIN_SPI_ID))
397
398 #define GICR_OFFSET(REG, id) \
399 (((id) <= MAX_PPI_ID) \
400 ? GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) \
401 : GICR_##REG##R + \
402 ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID)) >> \
403 REG##R_SHIFT) \
404 << 2))
405 #else /* GICv3 */
406 #define GICR_OFFSET_8(REG, id) (GICR_##REG##R + (uintptr_t)(id))
407
408 #define GICR_OFFSET(REG, id) \
409 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
410 #endif /* GIC_EXT_INTID */
411
412 /* Read/Write GIC Redistributor register corresponding to its interrupt ID */
413 #define GICR_READ(REG, base, id) \
414 io_read32(IO32_C((base) + GICR_OFFSET(REG, (id))))
415
416 #define GICR_WRITE_8(REG, base, id, val) \
417 io_write8(IO8_C((base) + GICR_OFFSET_8(REG, (id))), (val))
418
419 #define GICR_WRITE(REG, base, id, val) \
420 io_write32(IO32_C((base) + GICR_OFFSET(REG, (id))), (val))
421
422 /*
423 * Bit operations on GIC Redistributor register
424 * corresponding to its interrupt ID
425 */
426
427 /* Get bit in GIC Redistributor register */
428 #define GICR_GET_BIT(REG, base, id) \
429 ((io_read32(IO32_C((base) + GICR_OFFSET(REG, (id)))) >> \
430 BIT_NUM(REG, (id))) & \
431 1U)
432
433 /* Write bit in GIC Redistributor register */
434 #define GICR_WRITE_BIT(REG, base, id) \
435 io_write32(IO32_C((base) + GICR_OFFSET(REG, (id))), \
436 ((uint32_t)1 << BIT_NUM(REG, (id))))
437
438 /* Set bit in GIC Redistributor register */
439 #define GICR_SET_BIT(REG, base, id) \
440 io_setbits32(IO32_C((base) + GICR_OFFSET(REG, (id))), \
441 ((uint32_t)1 << BIT_NUM(REG, (id))))
442
443 /* Clear bit in GIC Redistributor register */
444 #define GICR_CLR_BIT(REG, base, id) \
445 io_clrbits32(IO32_C((base) + GICR_OFFSET(REG, (id))), \
446 ((uint32_t)1 << BIT_NUM(REG, (id))))
447
gicd_irouter_val_from_mpidr(uint64_t mpidr,unsigned int irm)448 static inline uint64_t gicd_irouter_val_from_mpidr(uint64_t mpidr,
449 unsigned int irm)
450 {
451 return (mpidr & ~(UINT32_C(0xff) << 24)) |
452 ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT);
453 }
454
455 /**
456 * GIC Distributor interface register accessors that are common to GICv3 & GICv2
457 */
gicd_read_ctlr(uintptr_t base)458 static inline unsigned int gicd_read_ctlr(uintptr_t base)
459 {
460 return io_read32(IO32_C(base + GICD_CTLR));
461 }
462
gicd_write_ctlr(uintptr_t base,unsigned int val)463 static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
464 {
465 io_write32(IO32_C(base + GICD_CTLR), val);
466 }
467
468 /**
469 * GIC Distributor interface accessors
470 */
471 /*
472 * Wait for updates to:
473 * GICD_CTLR[2:0] - the Group Enables
474 * GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit
475 * GICD_ICENABLER<n> - the clearing of enable state for SPIs
476 */
gicd_wait_for_pending_write(uintptr_t gicd_base)477 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
478 {
479 while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) {
480 }
481 }
482
gicd_read_pidr2(uintptr_t base)483 static inline uint32_t gicd_read_pidr2(uintptr_t base)
484 {
485 return io_read32(IO32_C(base + GICD_PIDR2_GICV3));
486 }
487
gicd_write_irouter(uintptr_t base,unsigned int id,uint64_t affinity)488 static inline void gicd_write_irouter(uintptr_t base, unsigned int id,
489 uint64_t affinity)
490 {
491 CHECK(id >= MIN_SPI_ID);
492 GICD_WRITE_64(IROUTE, base, id, affinity);
493 }
494
495 /**
496 * GIC Redistributor interface accessors
497 */
gicr_read_ctlr(uintptr_t base)498 static inline uint32_t gicr_read_ctlr(uintptr_t base)
499 {
500 return io_read32(IO32_C(base + GICR_CTLR));
501 }
502
503 /*
504 * Wait for updates to:
505 * GICR_ICENABLER0
506 * GICR_CTLR.DPG1S
507 * GICR_CTLR.DPG1NS
508 * GICR_CTLR.DPG0
509 * GICR_CTLR, which clears EnableLPIs from 1 to 0
510 */
gicr_wait_for_pending_write(uintptr_t gicr_base)511 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
512 {
513 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) {
514 }
515 }
516
517 /**
518 * GIC Distributor functions for accessing the GIC registers
519 * corresponding to a single interrupt ID. These functions use bitwise
520 * operations or appropriate register accesses to modify or return
521 * the bit-field corresponding the single interrupt ID.
522 */
523
524 /**
525 * Accessors to set the bits corresponding to interrupt ID
526 * in GIC Distributor ICFGR and ICFGRE.
527 */
gicd_set_icfgr(uintptr_t base,unsigned int id,unsigned int cfg)528 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
529 {
530 /* Interrupt configuration is a 2-bit field */
531 unsigned int bit_shift = BIT_NUM(ICFG, id) << 1U;
532
533 /* Clear the field, and insert required configuration */
534 io_clrsetbits32(IO32_C(base + GICD_OFFSET(ICFG, id)),
535 (uint32_t)GIC_CFG_MASK << bit_shift,
536 (cfg & GIC_CFG_MASK) << bit_shift);
537 }
538
539 /**
540 * Accessors to get/set/clear the bit corresponding to interrupt ID
541 * in GIC Distributor IGROUPR and IGROUPRE.
542 */
gicd_get_igroupr(uintptr_t base,unsigned int id)543 unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
544 {
545 return GICD_GET_BIT(IGROUP, base, id);
546 }
547
gicd_set_igroupr(uintptr_t base,unsigned int id)548 void gicd_set_igroupr(uintptr_t base, unsigned int id)
549 {
550 GICD_SET_BIT(IGROUP, base, id);
551 }
552
gicd_clr_igroupr(uintptr_t base,unsigned int id)553 void gicd_clr_igroupr(uintptr_t base, unsigned int id)
554 {
555 GICD_CLR_BIT(IGROUP, base, id);
556 }
557
558 /**
559 * Accessors to get/set/clear the bit corresponding to interrupt ID
560 * in GIC Distributor IGRPMODR and IGRPMODRE.
561 */
gicd_get_igrpmodr(uintptr_t base,unsigned int id)562 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
563 {
564 return GICD_GET_BIT(IGRPMOD, base, id);
565 }
566
gicd_set_igrpmodr(uintptr_t base,unsigned int id)567 void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
568 {
569 GICD_SET_BIT(IGRPMOD, base, id);
570 }
571
gicd_clr_igrpmodr(uintptr_t base,unsigned int id)572 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
573 {
574 GICD_CLR_BIT(IGRPMOD, base, id);
575 }
576
577 /**
578 * Accessors to set the bit corresponding to interrupt ID
579 * in GIC Distributor ICENABLER and ICENABLERE.
580 */
gicd_set_icenabler(uintptr_t base,unsigned int id)581 void gicd_set_icenabler(uintptr_t base, unsigned int id)
582 {
583 GICD_WRITE_BIT(ICENABLE, base, id);
584 }
585
586 /**
587 * Accessors to set the bit corresponding to interrupt ID
588 * in GIC Distributor ISENABLER and ISENABLERE.
589 */
gicd_set_isenabler(uintptr_t base,unsigned int id)590 void gicd_set_isenabler(uintptr_t base, unsigned int id)
591 {
592 GICD_WRITE_BIT(ISENABLE, base, id);
593 }
594
595 /**
596 * Accessors to set the bit corresponding to interrupt ID
597 * in GIC Distributor IPRIORITYR and IPRIORITYRE.
598 */
gicd_set_ipriorityr(uintptr_t base,unsigned int id,unsigned int pri)599 void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
600 {
601 GICD_WRITE_8(IPRIORITY, base, id, (uint8_t)(pri & GIC_PRI_MASK));
602 }
603
604 /**
605 * Accessor to set the byte corresponding to interrupt `id`
606 * in GIC Redistributor IPRIORITYR and IPRIORITYRE.
607 */
gicr_set_ipriorityr(uintptr_t base,unsigned int id,unsigned int pri)608 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
609 {
610 GICR_WRITE_8(IPRIORITY, base, id, (uint8_t)(pri & GIC_PRI_MASK));
611 }
612
613 /**
614 * Accessors to get/set/clear the bit corresponding to interrupt `id`
615 * from GIC Redistributor IGROUPR0 and IGROUPRE
616 */
gicr_get_igroupr(uintptr_t base,unsigned int id)617 unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id)
618 {
619 return GICR_GET_BIT(IGROUP, base, id);
620 }
621
gicr_set_igroupr(uintptr_t base,unsigned int id)622 void gicr_set_igroupr(uintptr_t base, unsigned int id)
623 {
624 GICR_SET_BIT(IGROUP, base, id);
625 }
626
gicr_clr_igroupr(uintptr_t base,unsigned int id)627 void gicr_clr_igroupr(uintptr_t base, unsigned int id)
628 {
629 GICR_CLR_BIT(IGROUP, base, id);
630 }
631
632 /**
633 * Accessors to get/set/clear the bit corresponding to interrupt `id`
634 * from GIC Redistributor IGRPMODR0 and IGRPMODRE
635 */
gicr_get_igrpmodr(uintptr_t base,unsigned int id)636 unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id)
637 {
638 return GICR_GET_BIT(IGRPMOD, base, id);
639 }
640
gicr_set_igrpmodr(uintptr_t base,unsigned int id)641 void gicr_set_igrpmodr(uintptr_t base, unsigned int id)
642 {
643 GICR_SET_BIT(IGRPMOD, base, id);
644 }
645
gicr_clr_igrpmodr(uintptr_t base,unsigned int id)646 void gicr_clr_igrpmodr(uintptr_t base, unsigned int id)
647 {
648 GICR_CLR_BIT(IGRPMOD, base, id);
649 }
650
651 /**
652 * Accessor to write the bit corresponding to interrupt `id`
653 * in GIC Redistributor ISENABLER0 and ISENABLERE
654 */
gicr_set_isenabler(uintptr_t base,unsigned int id)655 void gicr_set_isenabler(uintptr_t base, unsigned int id)
656 {
657 GICR_WRITE_BIT(ISENABLE, base, id);
658 }
659
660 /**
661 * Accessor to write the bit corresponding to interrupt `id`
662 * in GIC Redistributor ICENABLER0 and ICENABLERE
663 */
gicr_set_icenabler(uintptr_t base,unsigned int id)664 void gicr_set_icenabler(uintptr_t base, unsigned int id)
665 {
666 GICR_WRITE_BIT(ICENABLE, base, id);
667 }
668
669 /**
670 * Accessor to set the bit fields corresponding to interrupt `id`
671 * in GIC Redistributor ICFGR0, ICFGR1 and ICFGRE
672 */
gicr_set_icfgr(uintptr_t base,unsigned int id,unsigned int cfg)673 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
674 {
675 /* Interrupt configuration is a 2-bit field */
676 unsigned int bit_shift = BIT_NUM(ICFG, id) << 1U;
677
678 /* Clear the field, and insert required configuration */
679 io_clrsetbits32(IO32_C(base + GICR_OFFSET(ICFG, id)),
680 (uint32_t)GIC_CFG_MASK << bit_shift,
681 (cfg & GIC_CFG_MASK) << bit_shift);
682 }
683