1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "hdmi.h"
27 #include "head.h"
28 #include "ior.h"
29 #include "outp.h"
30
31 #include <nvif/class.h>
32
33 void
gm200_sor_dp_drive(struct nvkm_ior * sor,int ln,int pc,int dc,int pe,int pu)34 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
35 {
36 struct nvkm_device *device = sor->disp->engine.subdev.device;
37 const u32 loff = nv50_sor_link(sor);
38 const u32 shift = sor->func->dp->lanes[ln] * 8;
39 u32 data[4];
40
41 pu &= 0x0f;
42
43 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
44 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
45 data[2] = nvkm_rd32(device, 0x61c130 + loff);
46 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0)
47 data[2] = (data[2] & ~0x00000f00) | (pu << 8);
48
49 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
50 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
51 nvkm_wr32(device, 0x61c130 + loff, data[2]);
52
53 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
54 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
55 }
56
57 const struct nvkm_ior_func_dp
58 gm200_sor_dp = {
59 .lanes = { 0, 1, 2, 3 },
60 .links = gf119_sor_dp_links,
61 .power = g94_sor_dp_power,
62 .pattern = gm107_sor_dp_pattern,
63 .drive = gm200_sor_dp_drive,
64 .vcpi = gf119_sor_dp_vcpi,
65 .audio = gf119_sor_dp_audio,
66 .audio_sym = gf119_sor_dp_audio_sym,
67 .watermark = gf119_sor_dp_watermark,
68 };
69
70 void
gm200_sor_hdmi_scdc(struct nvkm_ior * ior,u8 scdc)71 gm200_sor_hdmi_scdc(struct nvkm_ior *ior, u8 scdc)
72 {
73 struct nvkm_device *device = ior->disp->engine.subdev.device;
74 const u32 soff = nv50_ior_base(ior);
75 const u32 ctrl = scdc & 0x3;
76
77 nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);
78
79 ior->tmds.high_speed = !!(scdc & 0x2);
80 }
81
82 const struct nvkm_ior_func_hdmi
83 gm200_sor_hdmi = {
84 .ctrl = gk104_sor_hdmi_ctrl,
85 .scdc = gm200_sor_hdmi_scdc,
86 .infoframe_avi = gk104_sor_hdmi_infoframe_avi,
87 .infoframe_vsi = gk104_sor_hdmi_infoframe_vsi,
88 };
89
90 void
gm200_sor_route_set(struct nvkm_outp * outp,struct nvkm_ior * ior)91 gm200_sor_route_set(struct nvkm_outp *outp, struct nvkm_ior *ior)
92 {
93 struct nvkm_device *device = outp->disp->engine.subdev.device;
94 const u32 moff = __ffs(outp->info.or) * 0x100;
95 const u32 sor = ior ? ior->id + 1 : 0;
96 u32 link = ior ? (ior->asy.link == 2) : 0;
97
98 if (outp->info.sorconf.link & 1) {
99 nvkm_mask(device, 0x612308 + moff, 0x0000001f, link << 4 | sor);
100 link++;
101 }
102
103 if (outp->info.sorconf.link & 2)
104 nvkm_mask(device, 0x612388 + moff, 0x0000001f, link << 4 | sor);
105 }
106
107 int
gm200_sor_route_get(struct nvkm_outp * outp,int * link)108 gm200_sor_route_get(struct nvkm_outp *outp, int *link)
109 {
110 struct nvkm_device *device = outp->disp->engine.subdev.device;
111 const int sublinks = outp->info.sorconf.link;
112 int lnk[2], sor[2], m, s;
113
114 for (*link = 0, m = __ffs(outp->info.or) * 2, s = 0; s < 2; m++, s++) {
115 if (sublinks & BIT(s)) {
116 u32 data = nvkm_rd32(device, 0x612308 + (m * 0x80));
117 lnk[s] = (data & 0x00000010) >> 4;
118 sor[s] = (data & 0x0000000f);
119 if (!sor[s])
120 return -1;
121 *link |= lnk[s];
122 }
123 }
124
125 if (sublinks == 3) {
126 if (sor[0] != sor[1] || WARN_ON(lnk[0] || !lnk[1]))
127 return -1;
128 }
129
130 return ((sublinks & 1) ? sor[0] : sor[1]) - 1;
131 }
132
133 static const struct nvkm_ior_func
134 gm200_sor = {
135 .route = {
136 .get = gm200_sor_route_get,
137 .set = gm200_sor_route_set,
138 },
139 .state = gf119_sor_state,
140 .power = nv50_sor_power,
141 .clock = gf119_sor_clock,
142 .hdmi = &gm200_sor_hdmi,
143 .dp = &gm200_sor_dp,
144 .hda = &gf119_sor_hda,
145 };
146
147 static int
gm200_sor_new(struct nvkm_disp * disp,int id)148 gm200_sor_new(struct nvkm_disp *disp, int id)
149 {
150 struct nvkm_device *device = disp->engine.subdev.device;
151 u32 hda;
152
153 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000))
154 hda = nvkm_rd32(device, 0x101034);
155
156 return nvkm_ior_new_(&gm200_sor, disp, SOR, id, hda & BIT(id));
157 }
158
159 static const struct nvkm_disp_func
160 gm200_disp = {
161 .oneinit = nv50_disp_oneinit,
162 .init = gf119_disp_init,
163 .fini = gf119_disp_fini,
164 .intr = gf119_disp_intr,
165 .intr_error = gf119_disp_intr_error,
166 .super = gf119_disp_super,
167 .uevent = &gf119_disp_chan_uevent,
168 .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
169 .dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
170 .sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
171 .root = { 0,0,GM200_DISP },
172 .user = {
173 {{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
174 {{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
175 {{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
176 {{0,0,GM200_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gk104_disp_core },
177 {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
178 {}
179 },
180 };
181
182 int
gm200_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)183 gm200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
184 struct nvkm_disp **pdisp)
185 {
186 return nvkm_disp_new_(&gm200_disp, device, type, inst, pdisp);
187 }
188