1 /**
2 * Copyright (c) 2017, Realsil Semiconductor Corporation. All rights reserved.
3 *
4 */
5
6 #include <stdio.h>
7 #include <string.h>
8 #include "os_sched.h"
9 #include "os_pool.h"
10 #include "os_sync.h"
11 #include "os_mem.h"
12
13 #include "hci_tp.h"
14 #include "hci_uart.h"
15 #include "bt_types.h"
16 #include "trace_app.h"
17
18 #include "bt_board.h"
19 #include "hci_board.h"
20 #include "hci_process.h"
21 #include "build_info.h"
22 //#include "bt_intf.h"
23 #include "wifi_conf.h" //for wifi_disable_powersave and wifi_resume_powersave
24
25 #define hci_board_32reg_set(addr, val) HAL_WRITE32(addr, 0, val)
26 #define hci_board_32reg_read(addr) HAL_READ32(addr, 0)
27
28 #define BT_EFUSE_TABLE_LEN 0x20
29
30
31 #define BT_CONFIG_SIGNATURE 0x8723ab55
32 #define BT_CONFIG_HEADER_LEN 6
33
34 typedef struct {
35 u32 IQK_xx;
36 u32 IQK_yy;
37 u32 IDAC;
38 u32 QDAC;
39 }BT_Cali_TypeDef;
40 BT_Cali_TypeDef g_iqk_data;
41
42 const BAUDRATE_MAP baudrates[] =
43 {
44 {0x0000701d, 115200},
45 {0x0252C00A, 230400},
46 {0x03F75004, 921600},
47 {0x05F75004, 921600},
48 {0x00005004, 1000000},
49 {0x04928002, 1500000},
50 {0x00005002, 2000000},
51 {0x0000B001, 2500000},
52 {0x04928001, 3000000},
53 {0x052A6001, 3500000},
54 {0x00005001, 4000000},
55 };
56 unsigned int baudrates_length = sizeof(baudrates) / sizeof(BAUDRATE_MAP);
57
58 static uint32_t hci_tp_baudrate;
59 uint8_t hci_tp_lgc_efuse[BT_EFUSE_TABLE_LEN];
60 uint8_t hci_tp_phy_efuse[19];
61
62 extern const unsigned char *rltk_bt_get_patch_code(void);
63 extern void rltk_coex_bt_enable(u8 enable);
64
cal_bit_shift(uint32_t Mask)65 static uint32_t cal_bit_shift(uint32_t Mask)
66 {
67 uint32_t i;
68 for(i=0; i<31;i++)
69 {
70 if(((Mask>>i) & 0x1)==1)
71 break;
72 }
73 return (i);
74 }
75
set_reg_value(uint32_t reg_address,uint32_t Mask,uint32_t val)76 static void set_reg_value(uint32_t reg_address, uint32_t Mask , uint32_t val)
77 {
78 uint32_t shift = 0;
79 uint32_t data = 0;
80 data = hci_board_32reg_read(reg_address);
81 shift = cal_bit_shift(Mask);
82 data = ((data & (~Mask)) | (val << shift));
83 hci_board_32reg_set(reg_address, data);
84 data = hci_board_32reg_read(reg_address);
85 }
86
hci_rtk_parse_config(uint8_t * config_buf,uint16_t config_len,uint8_t * efuse_buf)87 bool hci_rtk_parse_config(uint8_t *config_buf, uint16_t config_len, uint8_t *efuse_buf)
88 {
89
90 uint32_t signature;
91 uint16_t payload_len;
92 uint16_t entry_offset;
93 uint16_t entry_len;
94 uint8_t *p_entry;
95 uint8_t *p;
96 uint8_t *p_len;
97 uint8_t i;
98 uint16_t tx_flatk;
99
100 //enter the config_len
101
102 p = config_buf;
103 p_len = config_buf + 4;
104
105 extern uint32_t bt_flatk_8721d(uint16_t txgain_flatk);
106
107 LE_STREAM_TO_UINT32(signature, p);
108 LE_STREAM_TO_UINT16(payload_len, p);
109
110 if (signature != BT_CONFIG_SIGNATURE)
111 {
112 HCI_PRINT_ERROR1("hci_rtk_parse_config: invalid signature 0x%08x", signature);
113
114 return false;
115 }
116
117 if (payload_len != config_len - BT_CONFIG_HEADER_LEN)
118 {
119 HCI_PRINT_WARN2("hci_rtk_parse_config: invalid len, stated %u, calculated %u",
120 payload_len, config_len - BT_CONFIG_HEADER_LEN);
121 LE_UINT16_TO_STREAM(p_len, config_len - BT_CONFIG_HEADER_LEN); //just avoid the length is not coreect
122 /* FIX the len */
123 // return false;
124 }
125 #define BT_EFUSE_BLOCK1_OFFSET 0x06
126 #define BT_EFUSE_BLOCK2_OFFSET 0x0c
127 #define BT_EFUSE_BLOCK3_OFFSET 0x12
128
129 p_entry = config_buf + BT_CONFIG_HEADER_LEN;
130
131 while (p_entry < config_buf + config_len)
132 {
133 p = p_entry;
134 LE_STREAM_TO_UINT16(entry_offset, p);
135 LE_STREAM_TO_UINT8(entry_len, p);
136 p_entry = p + entry_len;
137
138 switch (entry_offset)
139 {
140 case 0x000c:
141 if ((rltk_wlan_is_mp())||(!CHECK_SW(EFUSE_SW_UPPERSTACK_SWITCH)))
142 {
143 //default use the 115200
144 hci_board_debug("set hci baudrate 115200\n");
145 memcpy(p,&(baudrates[0].bt_baudrate),4);
146 }
147 LE_STREAM_TO_UINT32(hci_tp_baudrate, p);
148
149 #if 0
150 if (entry_len >= 12)
151 {
152 p_hci_rtk->hw_flow_cntrl |= 0x80; /* bit7 set hw flow control */
153 p += 8;
154
155 if (*p & 0x04) /* offset 0x18, bit2 */
156 {
157 p_hci_rtk->hw_flow_cntrl |= 1; /* bit0 enable hw flow control */
158 }
159 }
160 HCI_PRINT_TRACE2("hci_rtk_parse_config: baudrate 0x%08x, hw flow control 0x%02x",
161 p_hci_rtk->baudrate,p_hci_rtk->hw_flow_cntrl);
162 //hci_board_debug("hci_rtk_parse_config: baudrate 0x%08x\n", p_hci_rtk->baudrate);
163 #endif
164 break;
165 case 0x0018:
166 if ((rltk_wlan_is_mp())||(!CHECK_SW(EFUSE_SW_UPPERSTACK_SWITCH)))
167 {
168 //hci_board_debug("hci uart flow ctrl: 0x%02x\n", p[0]);
169 p[0] =p[0] & (~ BIT2) ;
170 hci_board_debug("close hci uart flow ctrl: 0x%02x\n", p[0]);
171 //close the flow control
172 }
173 break;
174 case 0x0030:
175 if (entry_len == 6)
176 {
177 if ((efuse_buf[0] != 0xff) && (efuse_buf[1] != 0xff))
178 {
179 //memcpy(p,&efuse_buf[0],6);
180 /*
181 hci_board_debug("\r\nBT ADDRESS:\r\n");
182 for(int i = 0 ;i <6;i ++)
183 {
184 p[i] = efuse_buf[5-i];
185 hci_board_debug("%02x:",efuse_buf[i]);
186 }
187 hci_board_debug("\r\n");*/
188 for(int i = 0 ;i <6;i ++)
189 {
190 p[i] = efuse_buf[5-i];
191 }
192
193 hci_board_debug("\nBT ADDRESS: %02x:%02x:%02x:%02x:%02x:%02x\r\n",
194 efuse_buf[0], efuse_buf[1], efuse_buf[2],
195 efuse_buf[3], efuse_buf[4], efuse_buf[5]);
196 }
197 else
198 {
199 hci_board_debug("hci_rtk_parse_config: BT ADDRESS %02x %02x %02x %02x %02x %02x, use the defaut config\n",
200 p[0], p[1], p[2], p[3], p[4], p[5]);
201 }
202 }
203 break;
204 case 0x194:
205 if(efuse_buf[LEFUSE(0x196)]== 0xff)
206 {
207 if(!(hci_tp_phy_efuse[2]& BIT0))
208 {
209 //0
210 tx_flatk=hci_tp_phy_efuse[0xa] | hci_tp_phy_efuse[0xb]<<8;
211 bt_flatk_8721d(tx_flatk);
212 hci_board_debug("\r\n WRITE physical FLATK=tx_flatk=%x \r\n", tx_flatk);
213 }
214
215 break;
216 }
217 else
218 {
219
220 p[0]= efuse_buf[LEFUSE(0x196)];
221 if(efuse_buf[LEFUSE(0x196)] & BIT1)
222 {
223 p[1]= efuse_buf[LEFUSE(0x197)];
224 }
225
226 if(efuse_buf[LEFUSE(0x196)] & BIT2)
227 {
228 p[2]= efuse_buf[LEFUSE(0x198)];
229 p[3]= efuse_buf[LEFUSE(0x199)];
230
231 tx_flatk=efuse_buf[LEFUSE(0x198)] | efuse_buf[LEFUSE(0x199)]<<8;
232 bt_flatk_8721d(tx_flatk);
233 hci_board_debug("\r\n WRITE logic FLATK=tx_flatk=%x \r\n", tx_flatk);
234
235 }
236 else
237 {
238 if(!(hci_tp_phy_efuse[2]& BIT0))
239 {
240 //0
241 tx_flatk=hci_tp_phy_efuse[0xa] | hci_tp_phy_efuse[0xb]<<8;
242
243 bt_flatk_8721d(tx_flatk);
244 hci_board_debug("\r\n WRITE physical FLATK=tx_flatk=%x \r\n", tx_flatk);
245 }
246
247 }
248
249 if(efuse_buf[LEFUSE(0x196)] & BIT5)
250 {
251 p[4]= efuse_buf[LEFUSE(0x19a)];
252 p[5]= efuse_buf[LEFUSE(0x19b)];
253 }
254 }
255
256 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
257 {
258 for(i = 0;i < entry_len;i ++)
259 {
260 hci_board_debug("\r\n logic efuseMap[%x] = %x\r\n",0x196+i, p[i]);
261 }
262 }
263 break;
264 case 0x19f:
265 for(i = 0;i <entry_len;i ++)
266 {
267 if(efuse_buf[LEFUSE(0x19c+i)] != 0xff)
268 {
269 p[i]= efuse_buf[LEFUSE(0x19c+i)];
270 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
271 {
272 hci_board_debug("\r\n logic efuseMap[%x] = %x\r\n",0x19c+i, p[i]);
273 }
274 }
275 }
276 break;
277 case 0x1A4:
278 for(i = 0;i < entry_len;i ++)
279 {
280 if(efuse_buf[LEFUSE(0x1a2+i)] != 0xff)
281 {
282 p[i]= efuse_buf[LEFUSE(0x1A2+i)];
283 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
284 {
285 hci_board_debug("\r\n logic efuseMap[%x] = %x\r\n",0x1A2+i, p[i]);
286 }
287 }
288 }
289 break;
290 default:
291 HCI_PRINT_TRACE2("hci_rtk_parse_config: entry offset 0x%04x, len 0x%02x",
292 entry_offset, entry_len);
293 break;
294 }
295 }
296 return true;
297 }
298
299
hci_flash_stream_read(uint8_t * address,uint32_t len,uint8_t * data)300 int hci_flash_stream_read(uint8_t *address, uint32_t len, uint8_t * data)
301 {
302 memcpy(data, (const void *)address, len);
303 return 1;
304 }
305
hci_find_patch_address(void)306 uint8_t *hci_find_patch_address(void)
307 {
308 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
309 {
310 hci_board_debug("\nWe use DEBUG VAL:0x%x\n", HAL_READ32(0x08000000, 0x3028));
311 }
312
313 if(CHECK_SW(EFUSE_SW_USE_FLASH_PATCH))
314 {
315 //1
316 return (uint8_t *)rltk_bt_get_patch_code();
317 }
318 else if (ota_get_cur_index() == OTA_INDEX_1)
319 {
320 hci_board_debug("\nWe use BT ROM OTA2 PATCH ADDRESS:0x%x\n", MERGE_PATCH_ADDRESS_OTA2);
321 HCI_PRINT_INFO1("\nWe use BT ROM OTA2 PATCH ADDRESS:0x%x\n", MERGE_PATCH_ADDRESS_OTA2);
322 return (uint8_t *)MERGE_PATCH_ADDRESS_OTA2;
323 }
324 else
325 {
326 hci_board_debug("\nWe use BT ROM OTA1 PATCH ADDRESS:0x%x\n", MERGE_PATCH_ADDRESS_OTA1);
327 HCI_PRINT_INFO1("\nWe use BT ROM OTA1 PATCH ADDRESS:0x%x\n", MERGE_PATCH_ADDRESS_OTA1);
328 return (uint8_t *)MERGE_PATCH_ADDRESS_OTA1;
329 }
330 }
331
332
333 /** @brief configuration */
334 unsigned char rtlbt_init_config[] =
335 {
336 0x55, 0xab, 0x23, 0x87,
337
338 0x19, 0x00,
339 //0x10, 0x00,
340 0x30, 0x00, 0x06, 0x11, 0x28, 0x36, 0x12, 0x51, 0x89, /* BT MAC address */
341 // 0x07, 0x00,
342 0x0c, 0x00, 0x04, 0x04, 0x50, 0xF7, 0x03, /* Baudrate 921600 */
343 0x18, 0x00, 0x01,0x5c, /* flow control */
344 //efuse value
345 0x94, 0x01, 0x06, 0x08, 0x00, 0x00, 0x00,0x27, 0x07,
346
347 0x9f, 0x01, 0x05, 0x23, 0x23 , 0x23, 0x23,0x59,
348
349 0xA4, 0x01, 0x04, 0xFE, 0xFE , 0xFE, 0xFE
350 };
351
352 extern unsigned char rtlbt_config[];
353 extern unsigned int rtlbt_config_len;
354
hci_rtk_combine_config(void)355 uint8_t *hci_rtk_combine_config(void)
356 {
357 #define HCI_CONFIG_HEAD 6
358 uint16_t config_length = rtlbt_config_len + sizeof(rtlbt_init_config) - HCI_CONFIG_HEAD;
359
360 uint8_t *full_config_buf = os_mem_zalloc(RAM_TYPE_DATA_ON, config_length);
361 uint8_t *p_len = full_config_buf+4;
362
363 memcpy(full_config_buf,rtlbt_init_config, sizeof(rtlbt_init_config));
364 memcpy(full_config_buf+sizeof(rtlbt_init_config),rtlbt_config+HCI_CONFIG_HEAD, rtlbt_config_len-HCI_CONFIG_HEAD);
365
366 HCI_PRINT_WARN1("hci_rtk_combine_config: invalid len, calculated %u", config_length);
367
368 LE_UINT16_TO_STREAM(p_len, config_length); //just avoid the length is not coreect
369 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
370 {
371 hci_board_debug("hci_rtk_combine_config: all config length is %x\r\n",config_length);
372 for(uint8_t i=0;i< config_length;i++)
373 {
374 hci_board_debug("\n:%02x", full_config_buf[i]);
375 }
376 }
377 return full_config_buf;
378 }
379
fix_config_len(void)380 uint16_t fix_config_len(void)
381 {
382 return (rtlbt_config_len + sizeof(rtlbt_init_config) - HCI_CONFIG_HEAD);
383 }
384
385
hci_rtk_find_patch(uint8_t bt_hci_chip_id)386 bool hci_rtk_find_patch(uint8_t bt_hci_chip_id)
387 {
388 extern unsigned int rtlbt_fw_len;
389 extern unsigned char rtlbt_config[];
390 extern unsigned int rtlbt_config_len;
391 const uint8_t no_patch_sing[4]= {0xFF, 0xFF, 0xFF, 0xFF};
392 uint8_t tmp_patch_head[8];
393
394
395 uint8_t *fw_buf;
396 uint8_t *config_buf;
397 uint16_t fw_len;
398 uint32_t fw_offset;
399 uint16_t config_len;
400 uint32_t lmp_subversion;;
401 uint16_t mp_num_of_patch=0;
402 uint16_t fw_chip_id = 0;
403 uint8_t i;
404
405 uint8_t *p_merge_addr = hci_find_patch_address();
406
407 hci_flash_stream_read(p_merge_addr ,8, tmp_patch_head);
408
409 hci_flash_stream_read(p_merge_addr+8 ,4, (uint8_t *)&lmp_subversion);
410 //LE_ARRAY_TO_UINT32(lmp_subversion, (p_merge_addr+8));
411
412 //if single patch or merged patch
413
414 if(!memcmp(tmp_patch_head, "Realtech", sizeof("Realtech")-1))
415 {
416 hci_flash_stream_read(p_merge_addr+0x0c ,2, (uint8_t *)&mp_num_of_patch);
417 //LE_ARRAY_TO_UINT16(mp_num_of_patch, p_merge_addr+0x0c);
418
419 if(mp_num_of_patch == 1)
420 {
421 hci_flash_stream_read(p_merge_addr+0x0e +2*mp_num_of_patch ,2, (uint8_t *)&fw_len);
422 //LE_ARRAY_TO_UINT16(fw_len, p_merge_addr+0x0e +2*mp_num_of_patch );
423 hci_flash_stream_read(p_merge_addr+0x0e +4*mp_num_of_patch ,4, (uint8_t *)&fw_offset);
424 //LE_ARRAY_TO_UINT32(fw_offset, p_merge_addr+0x0e +4*mp_num_of_patch);
425 if (rltk_wlan_is_mp())
426 {
427 hci_board_debug("\n fw_chip_id patch =%x,mp_num_of_patch=%x \n", fw_chip_id,mp_num_of_patch);
428 hci_board_debug("\n lmp_subversion=%x , fw_len =%x, fw_offset = %x \n", lmp_subversion, fw_len, fw_offset);
429 }
430 }
431 else
432 {
433 for(i = 0 ;i<mp_num_of_patch; i++)
434 {
435 hci_flash_stream_read(p_merge_addr+0x0e + 2*i ,2, (uint8_t *)&fw_chip_id);
436 // LE_ARRAY_TO_UINT16(fw_chip_id, p_merge_addr+0x0e + 2*i);
437
438 if(fw_chip_id == bt_hci_chip_id)
439 {
440 hci_flash_stream_read(p_merge_addr+0x0e +2*mp_num_of_patch + 2*i ,2, (uint8_t *)&fw_len);
441 //LE_ARRAY_TO_UINT16(fw_len, p_merge_addr+0x0e +2*mp_num_of_patch + 2*i);
442 hci_flash_stream_read(p_merge_addr+0x0e +4*mp_num_of_patch + 4*i ,4, (uint8_t *)&fw_offset);
443 //LE_ARRAY_TO_UINT32(fw_offset, p_merge_addr+0x0e +4*mp_num_of_patch + 4*i);
444 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
445 {
446 //0
447 hci_board_debug("\n fw_chip_id patch =%x,mp_num_of_patch=%x \n", fw_chip_id,mp_num_of_patch);
448 hci_board_debug("\n lmp_subversion=%x , fw_len =%x, fw_offset = %x \n", lmp_subversion, fw_len, fw_offset);
449 }
450 break;
451 }
452 }
453
454 if(i >= mp_num_of_patch)
455 {
456 hci_board_debug("\n ERROR:no match patch\n");
457 return false;
458 }
459 }
460
461 fw_buf = os_mem_zalloc(RAM_TYPE_DATA_ON, fw_len);
462 if(fw_buf == NULL)
463 {
464 hci_board_debug("\n fw_buf ,malloc %d byte fail, \n", fw_len);
465 return false;
466 }
467 else
468 {
469 memcpy(fw_buf,p_merge_addr+fw_offset, fw_len);
470 LE_UINT32_TO_ARRAY(fw_buf+fw_len-4,lmp_subversion);
471 }
472 }
473 else if(!memcmp(tmp_patch_head, no_patch_sing, sizeof(no_patch_sing)))
474 {
475 hci_board_debug("\nWrong patch head %x %x %x %x\n",p_merge_addr[0], p_merge_addr[1], p_merge_addr[2], p_merge_addr[3]);
476 return false;
477 }
478 else
479 {
480 hci_board_debug("\nwe use single patch\n");
481 if(p_merge_addr != (uint8_t *)rltk_bt_get_patch_code())
482 {
483 hci_board_debug("\nnot support single patch on rom\n");
484 return false;
485 }
486
487 fw_len = rtlbt_fw_len ;
488 fw_buf = os_mem_zalloc(RAM_TYPE_DATA_ON, fw_len);
489 memcpy(fw_buf,(const void *)rltk_bt_get_patch_code(), fw_len);
490 }
491
492 config_buf = rtlbt_init_config;
493 config_len = sizeof(rtlbt_init_config);
494 //config_len = 0;
495
496 if (config_len != 0)
497 {
498 if (hci_rtk_parse_config(config_buf, config_len, hci_tp_lgc_efuse) == false)
499 {
500 return false;
501 }
502 else
503 {
504 config_buf = hci_rtk_combine_config();
505 config_len = fix_config_len();
506 }
507 }
508
509
510 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
511 {
512 hci_board_debug("\nWe use lmp_subversion=%x fw_buf=%x, fw_len = %x, config_buf = %x,config_len= %x, baudrate 0x%x\n", lmp_subversion,fw_buf, fw_len, config_buf, config_len, hci_tp_baudrate);
513 }
514
515 hci_set_patch(fw_buf, fw_len, config_buf, config_len, hci_tp_baudrate);
516
517 return true;
518 }
519
bt_read_efuse(void)520 void bt_read_efuse(void)
521 {
522 u32 Idx = 0;
523 u32 ret = 0;
524 uint8_t *p_buf;
525
526 //read logic efuse
527 p_buf = os_mem_zalloc(RAM_TYPE_DATA_ON, 1024);
528 ret = EFUSE_LMAP_READ(p_buf);
529 if (ret == _FAIL)
530 {
531 hci_board_debug("EFUSE_LMAP_READ fail \n");
532 }
533 memcpy(hci_tp_lgc_efuse, p_buf+0x190,BT_EFUSE_TABLE_LEN);
534
535 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
536 {
537 //0
538 hci_board_debug("\r\n==logic_efuse:==\r\n ");
539 for (Idx = 0; Idx < BT_EFUSE_TABLE_LEN; Idx++)
540 {
541 hci_board_debug("\n%x:", hci_tp_lgc_efuse[Idx]);
542 }
543
544 }
545
546 //read physical efuse
547 for (Idx = 0; Idx < 16; Idx++)
548 {
549 EFUSE_PMAP_READ8(0, 0x120 + Idx, hci_tp_phy_efuse + Idx, L25EOUTVOLTAGE);
550 if ((Idx == 7) && (hci_tp_phy_efuse[Idx] == 0))
551 {
552 hci_tp_phy_efuse[Idx] = 0x13;
553 }
554 }
555 EFUSE_PMAP_READ8(0, 0x1FD, hci_tp_phy_efuse + 16, L25EOUTVOLTAGE);
556 EFUSE_PMAP_READ8(0, 0x1FE, hci_tp_phy_efuse + 17, L25EOUTVOLTAGE);
557 EFUSE_PMAP_READ8(0, 0x1FF, hci_tp_phy_efuse + 18, L25EOUTVOLTAGE);
558
559 if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
560 {
561 //0
562 hci_board_debug("\r\n==bt phy_efuse 0x120~0x12F:==\r\n ");
563 for (Idx = 0; Idx < 16; Idx++)
564 {
565 hci_board_debug("\n%x:", hci_tp_phy_efuse[Idx]);
566 }
567 hci_board_debug("\r\n==bt phy_efuse 0x1FD~0x1FF:==\r\n ");
568 for (Idx = 16; Idx < 19; Idx++)
569 {
570 hci_board_debug("\n%x:", hci_tp_phy_efuse[Idx]);
571 }
572 }
573 os_mem_free(p_buf);
574 }
575
576
bt_power_on(void)577 void bt_power_on(void)
578 {
579 set_reg_value(0x40000000,BIT0 | BIT1, 3);
580 }
581
bt_power_off(void)582 void bt_power_off(void)
583 {
584 set_reg_value(0x40000000,BIT0 | BIT1, 0);
585 rltk_coex_bt_enable(0);
586 if(!rltk_wlan_is_mp()){
587 //wifi_resume_powersave();
588 }
589 }
590
bt_change_gnt_bt_only(void)591 void bt_change_gnt_bt_only(void)
592 {
593 set_reg_value(0x40080764, BIT9 | BIT10,3 );
594 }
595
bt_change_gnt_wifi_only(void)596 void bt_change_gnt_wifi_only(void)
597 {
598 set_reg_value(0x40080764, BIT9 | BIT10,1);
599 }
600
bt_reset(void)601 void bt_reset(void)
602 {
603 if(!rltk_wlan_is_mp()) {
604 wifi_disable_powersave();
605 }
606
607 if(!CHECK_SW(EFUSE_SW_BT_FW_LOG))
608 {
609 //0
610 //open bt log pa16
611 hci_board_debug("BT FW LOG OPEN\n");
612 //close please change efuse:EFUSE wmap 1a1 1 fe
613 set_reg_value(0x48000440,BIT0 |BIT1 | BIT2 | BIT3 | BIT4, 17);
614 }
615
616 hci_board_debug("BT Reset...\n");
617 //bt power
618 bt_power_on();
619
620 os_delay(5);
621
622 //isolation
623 set_reg_value(0x40000000,BIT16, 0);
624 os_delay(5);
625
626 //BT function enable
627 set_reg_value(0x40000204,BIT24, 0);
628 os_delay(5);
629
630 set_reg_value(0x40000204,BIT24, 1);
631 os_delay(50);
632
633 //BT clock enable
634 set_reg_value(0x40000214, BIT24, 1);
635 os_delay(5);
636 }
637
hci_board_init()638 bool hci_board_init()
639 {
640 bool ret=false;
641
642 if(!(wifi_is_up(RTW_STA_INTERFACE) || wifi_is_up(RTW_AP_INTERFACE))) {
643 hci_board_debug("\nWIFI is off !Please restart BT after WIFI on!\n");
644 return false;
645 }
646
647 HCI_PRINT_INFO1("hci_tp_open, this cut is AmebaD %X CUT",SYSCFG_CUTVersion()+10);
648
649 if (rltk_wlan_is_mp())
650 {
651 hci_board_debug("\r\n==========this is BT MP DRIVER===========,\r\n this cut is AmebaD %X CUT\r\n",SYSCFG_CUTVersion()+10);
652 }
653 else if(!CHECK_SW(EFUSE_SW_DRIVER_DEBUG_LOG))
654 {
655 hci_board_debug("\r\n***********this is BT NORMAL DRIVER*******,\r\n this cut is AmebaD %X CUT\r\n",SYSCFG_CUTVersion()+10);
656 }
657
658
659
660 hci_board_debug("\r\nBT BUILD Date: %s \r\n",UTS_VERSION);
661 bt_read_efuse();
662
663 return true;
664 }
665
hci_normal_start(void)666 void hci_normal_start(void)
667 {
668 if(!rltk_wlan_is_mp())
669 {
670 rltk_coex_bt_enable(1);
671 }
672 }
673
bt_write_phy_efuse_value(void)674 void bt_write_phy_efuse_value(void)
675 {
676 hci_tp_phy_efuse[0] = 0;
677 hci_tp_phy_efuse[1] = 0x9e;
678 hci_tp_phy_efuse[2] = 0xfe;
679 hci_tp_phy_efuse[3] = g_iqk_data.IQK_xx & 0xff;
680 hci_tp_phy_efuse[4] = (g_iqk_data.IQK_xx >> 8) & 0xff;
681 hci_tp_phy_efuse[5] = g_iqk_data.IQK_yy & 0xff;
682 hci_tp_phy_efuse[6] = (g_iqk_data.IQK_yy >> 8) & 0xff;
683 //hci_tp_phy_efuse[7] = 0;//(g_iqk_data.IQK_yy >> 8) & 0xff;
684 hci_tp_phy_efuse[8] = 0x19;//(g_iqk_data.IQK_yy >> 8) & 0xff;
685
686 hci_tp_phy_efuse[12] = (g_iqk_data.QDAC) & 0xff;
687 hci_tp_phy_efuse[13] = (g_iqk_data.IDAC) & 0xff;
688
689 for(int i=0;i<0x10; i++)
690 {
691 hci_board_debug("\r\n write physical efuse 0x%x =0x%02x",0x120+i, hci_tp_phy_efuse[i]);
692 EFUSE_PMAP_WRITE8(0, 0x120 + i, hci_tp_phy_efuse[i], L25EOUTVOLTAGE);
693 }
694 }
695
696 #if 0
697 void hci_uart_out(void)
698 {
699 hci_board_debug("HCI UART OUT OK: PA2 TX, PA4 RX\r\n");
700 HAL_WRITE32(0x48000000, 0x5f0, 0x00000202);
701 //PA2 TX
702 HAL_WRITE32(0x48000000, 0x408, 0x00005C11);
703 //PA4 RX
704 HAL_WRITE32(0x48000000, 0x410,
705 0x00005C11);
706
707 bt_change_gnt_bt_only();
708 }
709 #endif
710
hci_board_complete(void)711 bool hci_board_complete(void)
712 {
713 // uint8_t orignal_hci_tp_phy_efuse[0x10];
714 /// hci_uart_out();
715 //return false;
716
717
718 if(rltk_wlan_is_mp())
719 {
720 #ifdef FT_MODE
721 uint8_t TestItem;
722 static bool write_efuse_ok=false;
723 hci_board_debug("\r\n=================original ========================\r\n");
724 for (int Idx = 0; Idx < 16; Idx++)
725 {
726 EFUSE_PMAP_READ8(0, 0x120 + Idx, orignal_hci_tp_phy_efuse + Idx, L25EOUTVOLTAGE);
727 hci_board_debug("\r\n original physical efuse 0x%x =0x%02x",0x120+Idx, orignal_hci_tp_phy_efuse[Idx]);
728 if(orignal_hci_tp_phy_efuse[Idx] != 0xff)
729 {
730 write_efuse_ok = true;
731 }
732 }
733
734 hci_board_debug("\r\n=================will write physical efuse ========================\r\n");
735 for(int i=0;i<0x10; i++)
736 {
737 hci_board_debug("\r\n 0x%x =0x%02x",0x120+i, hci_tp_phy_efuse[i]);
738 //EFUSE_PMAP_WRITE8(0, 0x120 + i, hci_tp_phy_efuse[i], L25EOUTVOLTAGE);
739 }
740
741 /*TODO:GNT_BT TO WIFI */
742 bt_change_gnt_wifi_only();
743 hci_board_debug("EFUSE_SW_MP_MODE: UPPERSTACK NOT UP \r\nGNT_BT %x...\n", HAL_READ32(0x40080000, 0x0764));
744 while ( 1 )
745 {
746 if ( GPIO_ReadDataBit( _PA_5 ) )
747 {
748 os_delay(2);
749 if ( GPIO_ReadDataBit( _PA_5 ) ) /* still input high */
750 {
751 GPIO_WriteBit( _PA_13, 0 );
752 TestItem = 0;
753 TestItem = GPIO_ReadDataBit( _PB_7 ); /* bit0 */
754 TestItem |= (GPIO_ReadDataBit( _PA_17 ) << 1); /* bit1 */
755 TestItem |= (GPIO_ReadDataBit( _PA_19 ) << 2); /* bit2 */
756 TestItem |= (GPIO_ReadDataBit( _PA_20 ) << 3); /* bit3 */
757 TestItem |= (GPIO_ReadDataBit( _PA_6 ) << 4); /* bit4 */
758 hci_board_debug( "TestItem is %d!!!\n", TestItem );
759 switch ( TestItem )
760 {
761 case 13:
762 if(write_efuse_ok == false)
763 {
764 bt_write_phy_efuse_value();
765 write_efuse_ok=true;
766 }
767 else
768 {
769 hci_board_debug("ERROR:phy_efuse has been write!!!,please check the phyfuse value\n");
770 /*TODO, tell the GPIO*/
771 }
772 break;
773
774 default:
775 break;
776 }
777 hci_board_debug( "trx done\n" );
778 GPIO_WriteBit( _PA_13, 1);
779 }
780 }
781 os_delay(15);
782 }
783 #endif
784 return false;
785 }
786
787 if(!CHECK_SW(EFUSE_SW_UPPERSTACK_SWITCH))
788 {
789 //0
790 hci_board_debug("Not Start upperStack, normal test\n");
791 return false;
792 }
793
794 hci_board_debug("Start upperStack\n");
795
796 return true;
797 }
798
799 //IQK LOK ABOUT
800
bt_iqk_efuse_valid(BT_Cali_TypeDef * bt_iqk_data)801 bool bt_iqk_efuse_valid(BT_Cali_TypeDef *bt_iqk_data)
802 {
803
804 if((hci_tp_phy_efuse[1] & BIT0))
805 {
806 //1
807 hci_board_debug("bt_iqk_efuse_valid: no data\r\n");
808 return false;
809 }
810 else
811 {
812 //0
813 bt_iqk_data->IQK_xx = hci_tp_phy_efuse[3] | hci_tp_phy_efuse[4] <<8;
814 bt_iqk_data->IQK_yy = hci_tp_phy_efuse[5] | hci_tp_phy_efuse[6] <<8;
815 bt_iqk_data->QDAC = hci_tp_phy_efuse[0x0c];
816 bt_iqk_data->IDAC = hci_tp_phy_efuse[0x0d];
817 hci_board_debug("physical efuse: has data hci_tp_phy_efuse[1]= %x \r\n", hci_tp_phy_efuse[1]);
818 return true;
819 }
820 }
821
bt_iqk_logic_efuse_valid(BT_Cali_TypeDef * bt_iqk_data)822 bool bt_iqk_logic_efuse_valid(BT_Cali_TypeDef *bt_iqk_data)
823 {
824 if(((hci_tp_lgc_efuse[0x16] == 0xff) && (hci_tp_lgc_efuse[0x17] == 0xff))||
825 ((hci_tp_lgc_efuse[0x18] == 0xff)&&(hci_tp_lgc_efuse[0x19] == 0xff))||
826 (hci_tp_lgc_efuse[0x1a] == 0xff) ||
827 (hci_tp_lgc_efuse[0x1b] == 0xff) )
828 {
829 hci_board_debug("bt_iqk_logic_efuse_valid: no data\r\n");
830 return false;
831 }
832 else
833 {
834 bt_iqk_data->IQK_xx = hci_tp_lgc_efuse[0x16] | hci_tp_lgc_efuse[0x17] <<8;
835 bt_iqk_data->IQK_yy = hci_tp_lgc_efuse[0x18] | hci_tp_lgc_efuse[0x19] <<8;
836 bt_iqk_data->QDAC = hci_tp_lgc_efuse[0x1a];
837 bt_iqk_data->IDAC = hci_tp_lgc_efuse[0x1b];
838 hci_board_debug("logic efuse: has data\r\n");
839 return true;
840 }
841 }
842
bt_dump_iqk(BT_Cali_TypeDef * iqk_data)843 void bt_dump_iqk(BT_Cali_TypeDef *iqk_data)
844 {
845 hci_board_debug("bt_iqk_dump: DUMP,\r\n");
846 hci_board_debug("the IQK_xx data is 0x%x,\r\n", iqk_data->IQK_xx);
847 hci_board_debug("the IQK_yy data is 0x%x,\r\n", iqk_data->IQK_yy);
848 hci_board_debug("the QDAC data is 0x%x,\r\n", iqk_data->QDAC);
849 hci_board_debug("the IDAC data is 0x%x,\r\n", iqk_data->IDAC);
850 }
851
852 extern uint32_t bt_iqk_8721d(BT_Cali_TypeDef *cal_data,BOOLEAN store);
853 extern uint32_t bt_lok_write(uint32_t lok_xx, uint32_t lok_yy);
854 extern uint32_t bt_dck_write(uint32_t q_dck, uint32_t i_dck);
855
bt_check_iqk(void)856 bool bt_check_iqk(void)
857 {
858 BT_Cali_TypeDef bt_iqk_data;
859
860 if(!(hci_tp_lgc_efuse[LEFUSE(0x1A1)] & BIT0))
861 //if(!CHECK_SW(EFUSE_SW_USE_LOGIC_EFUSE))
862 {
863 //0
864 hci_board_debug("\r\n%s: USE FIX LOGIC EFUSE\r\n",__FUNCTION__);
865 if (bt_iqk_logic_efuse_valid(&bt_iqk_data))
866 {
867 bt_dump_iqk(&bt_iqk_data);
868 bt_lok_write(bt_iqk_data.IDAC, bt_iqk_data.QDAC);
869 hci_tp_phy_efuse[0] = 0;
870 hci_tp_phy_efuse[1] =hci_tp_phy_efuse[1] & (~BIT0);
871 //hci_tp_phy_efuse[1] = 0xfe;
872 //hci_tp_phy_efuse[2] = 0xff;
873 hci_tp_phy_efuse[3] = bt_iqk_data.IQK_xx & 0xff;
874 hci_tp_phy_efuse[4] = (bt_iqk_data.IQK_xx >> 8) & 0xff;
875 hci_tp_phy_efuse[5] = bt_iqk_data.IQK_yy & 0xff;
876 hci_tp_phy_efuse[6] = (bt_iqk_data.IQK_yy >> 8) & 0xff;
877 return true;
878 }
879 hci_board_debug("\r\n%s: LOGIC EFUSE HAS NO DATA\r\n",__FUNCTION__);
880 return false;
881 }
882
883 if (bt_iqk_efuse_valid(&bt_iqk_data))
884 {
885 if(hci_tp_phy_efuse[0]!=0)
886 {
887 bt_dck_write(hci_tp_phy_efuse[0x0e], hci_tp_phy_efuse[0x0f]);
888 }
889 else
890 {
891 hci_board_debug("\r\nhci_tp_phy_efuse[0]=0,\r\n");
892 }
893 bt_dump_iqk(&bt_iqk_data);
894 bt_lok_write(bt_iqk_data.IDAC, bt_iqk_data.QDAC);
895 return true;
896 }
897
898 if (bt_iqk_logic_efuse_valid(&bt_iqk_data))
899 {
900 bt_dump_iqk(&bt_iqk_data);
901 bt_lok_write(bt_iqk_data.IDAC, bt_iqk_data.QDAC);
902 hci_tp_phy_efuse[0] = 0;
903 hci_tp_phy_efuse[1] =hci_tp_phy_efuse[1] & (~BIT0);
904 //hci_tp_phy_efuse[1] = 0xfe;
905 //hci_tp_phy_efuse[2] = 0xff;
906 hci_tp_phy_efuse[3] = bt_iqk_data.IQK_xx & 0xff;
907 hci_tp_phy_efuse[4] = (bt_iqk_data.IQK_xx >> 8) & 0xff;
908 hci_tp_phy_efuse[5] = bt_iqk_data.IQK_yy & 0xff;
909 hci_tp_phy_efuse[6] = (bt_iqk_data.IQK_yy >> 8) & 0xff;
910 return true;
911 }
912 else
913 {
914 hci_board_debug("bt_check_iqk: NO IQK LOK DATA need start LOK,\r\n");
915 //bt_change_gnt_wifi_only();
916 //bt_adda_dck_8721d();
917 reset_iqk_type();
918 return false;
919 }
920 //return true;
921 }
922
hci_start_iqk(void)923 bool hci_start_iqk(void)
924 {
925 u32 ret = 0;
926 //bt_change_gnt_wifi_only();
927
928 if(rltk_wlan_is_mp()) //JUST FOR DEBUG
929 {
930 hci_board_debug("BT \\GNT_BT %x LOG...\n", HAL_READ32(0x40080000, 0x0764));
931 // os_sched_suspend();
932 //uint32_t flag = os_lock();
933 ret = bt_iqk_8721d(&g_iqk_data, 0);
934 //os_sched_resume();
935 // os_unlock(flag);
936 bt_dump_iqk(&g_iqk_data);
937
938 hci_board_debug("\r\n Please write logic efuse 0x1A6 =0x%02x", g_iqk_data.IQK_xx & 0xff);
939 hci_board_debug("\r\n Please write logic efuse 0x1A7 =0x%02x", (g_iqk_data.IQK_xx >> 8) & 0xff);
940 hci_board_debug("\r\n Please write logic efuse 0x1A8 =0x%02x", g_iqk_data.IQK_yy & 0xff);
941 hci_board_debug("\r\n Please write logic efuse 0x1A9 =0x%02x", (g_iqk_data.IQK_yy >> 8) & 0xff);
942 hci_board_debug("\r\n Please write logic efuse 0x1AA =0x%02x", g_iqk_data.QDAC);
943 hci_board_debug("\r\n Please write logic efuse 0x1AB =0x%02x\r\n", g_iqk_data.IDAC);
944
945 }
946 else
947 {
948 ret = bt_iqk_8721d(&g_iqk_data, 0);
949 bt_dump_iqk(&g_iqk_data);
950 }
951
952
953 if(_FAIL == ret)
954 {
955 hci_board_debug("bt_check_iqk:Warning: IQK Fail, please connect driver !!!!!!!!!\r\n");
956 return false;
957 }
958
959 bt_lok_write(g_iqk_data.IDAC, g_iqk_data.QDAC);
960
961 hci_tp_phy_efuse[0] = 0;
962 hci_tp_phy_efuse[1] =hci_tp_phy_efuse[1] & (~BIT0);
963 //hci_tp_phy_efuse[1] = 0xfe;
964 //hci_tp_phy_efuse[2] = 0xff;
965 hci_tp_phy_efuse[3] = g_iqk_data.IQK_xx & 0xff;
966 hci_tp_phy_efuse[4] = (g_iqk_data.IQK_xx >> 8) & 0xff;
967 hci_tp_phy_efuse[5] = g_iqk_data.IQK_yy & 0xff;
968 hci_tp_phy_efuse[6] = (g_iqk_data.IQK_yy >> 8) & 0xff;
969
970 //bt_write_lgc_efuse_value();
971
972 return true;
973 }
974
bt_write_lgc_efuse_value(void)975 void bt_write_lgc_efuse_value(void)
976 {
977 hci_tp_lgc_efuse[0x16] = g_iqk_data.IQK_xx & 0xff;
978 hci_tp_lgc_efuse[0x17] = (g_iqk_data.IQK_xx >> 8) & 0xff;
979 hci_tp_lgc_efuse[0x18] = g_iqk_data.IQK_yy & 0xff;
980 hci_tp_lgc_efuse[0x19] = (g_iqk_data.IQK_yy >> 8) & 0xff;
981 hci_tp_lgc_efuse[0x1a] = g_iqk_data.QDAC;
982 hci_tp_lgc_efuse[0x1b] = g_iqk_data.IDAC;
983
984 hci_board_debug("\r\n write logic efuse 0x1A6 =0x%02x", hci_tp_lgc_efuse[0x16]);
985 hci_board_debug("\r\n write logic efuse 0x1A7 =0x%02x", hci_tp_lgc_efuse[0x17]);
986 hci_board_debug("\r\n write logic efuse 0x1A8 =0x%02x", hci_tp_lgc_efuse[0x18]);
987 hci_board_debug("\r\n write logic efuse 0x1A9 =0x%02x", hci_tp_lgc_efuse[0x19]);
988 hci_board_debug("\r\n write logic efuse 0x1Aa =0x%02x", hci_tp_lgc_efuse[0x1a]);
989 hci_board_debug("\r\n write logic efuse 0x1Ab =0x%02x", hci_tp_lgc_efuse[0x1b]);
990 //EFUSE_LMAP_WRITE(0x1A4,8,(uint8_t *)&hci_tp_lgc_efuse[0x14]);
991 }
992
993
bt_show_efuse_value(void)994 void bt_show_efuse_value(void)
995 {
996 int i = 0;
997 for(i=0;i<0x10;i++)
998 {
999 hci_board_debug("\r\n write physical efuse 0x%x =0x%02x",0x120+i, hci_tp_phy_efuse[i]);
1000 }
1001 }
1002
1003
1004
1005