1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
4  *
5  * Nintendo Wii "Hollywood" interrupt controller support.
6  * Copyright (C) 2009 The GameCube Linux Team
7  * Copyright (C) 2009 Albert Herranz
8  */
9 #define DRV_MODULE_NAME "hlwd-pic"
10 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
11 
12 #include <linux/kernel.h>
13 #include <linux/irq.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <asm/io.h>
18 
19 #include "hlwd-pic.h"
20 
21 #define HLWD_NR_IRQS	32
22 
23 /*
24  * Each interrupt has a corresponding bit in both
25  * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
26  *
27  * Enabling/disabling an interrupt line involves asserting/clearing
28  * the corresponding bit in IMR. ACK'ing a request simply involves
29  * asserting the corresponding bit in ICR.
30  */
31 #define HW_BROADWAY_ICR		0x00
32 #define HW_BROADWAY_IMR		0x04
33 #define HW_STARLET_ICR		0x08
34 #define HW_STARLET_IMR		0x0c
35 
36 
37 /*
38  * IRQ chip hooks.
39  *
40  */
41 
hlwd_pic_mask_and_ack(struct irq_data * d)42 static void hlwd_pic_mask_and_ack(struct irq_data *d)
43 {
44 	int irq = irqd_to_hwirq(d);
45 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
46 	u32 mask = 1 << irq;
47 
48 	clrbits32(io_base + HW_BROADWAY_IMR, mask);
49 	out_be32(io_base + HW_BROADWAY_ICR, mask);
50 }
51 
hlwd_pic_ack(struct irq_data * d)52 static void hlwd_pic_ack(struct irq_data *d)
53 {
54 	int irq = irqd_to_hwirq(d);
55 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
56 
57 	out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
58 }
59 
hlwd_pic_mask(struct irq_data * d)60 static void hlwd_pic_mask(struct irq_data *d)
61 {
62 	int irq = irqd_to_hwirq(d);
63 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
64 
65 	clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
66 }
67 
hlwd_pic_unmask(struct irq_data * d)68 static void hlwd_pic_unmask(struct irq_data *d)
69 {
70 	int irq = irqd_to_hwirq(d);
71 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
72 
73 	setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
74 
75 	/* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */
76 	clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
77 }
78 
79 
80 static struct irq_chip hlwd_pic = {
81 	.name		= "hlwd-pic",
82 	.irq_ack	= hlwd_pic_ack,
83 	.irq_mask_ack	= hlwd_pic_mask_and_ack,
84 	.irq_mask	= hlwd_pic_mask,
85 	.irq_unmask	= hlwd_pic_unmask,
86 };
87 
88 /*
89  * IRQ host hooks.
90  *
91  */
92 
93 static struct irq_domain *hlwd_irq_host;
94 
hlwd_pic_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hwirq)95 static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
96 			   irq_hw_number_t hwirq)
97 {
98 	irq_set_chip_data(virq, h->host_data);
99 	irq_set_status_flags(virq, IRQ_LEVEL);
100 	irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
101 	return 0;
102 }
103 
104 static const struct irq_domain_ops hlwd_irq_domain_ops = {
105 	.map = hlwd_pic_map,
106 };
107 
__hlwd_pic_get_irq(struct irq_domain * h)108 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
109 {
110 	void __iomem *io_base = h->host_data;
111 	u32 irq_status;
112 
113 	irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
114 		     in_be32(io_base + HW_BROADWAY_IMR);
115 	if (irq_status == 0)
116 		return 0;	/* no more IRQs pending */
117 
118 	return __ffs(irq_status);
119 }
120 
hlwd_pic_irq_cascade(struct irq_desc * desc)121 static void hlwd_pic_irq_cascade(struct irq_desc *desc)
122 {
123 	struct irq_chip *chip = irq_desc_get_chip(desc);
124 	struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
125 	unsigned int hwirq;
126 
127 	raw_spin_lock(&desc->lock);
128 	chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
129 	raw_spin_unlock(&desc->lock);
130 
131 	hwirq = __hlwd_pic_get_irq(irq_domain);
132 	if (hwirq)
133 		generic_handle_domain_irq(irq_domain, hwirq);
134 	else
135 		pr_err("spurious interrupt!\n");
136 
137 	raw_spin_lock(&desc->lock);
138 	chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
139 	if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
140 		chip->irq_unmask(&desc->irq_data);
141 	raw_spin_unlock(&desc->lock);
142 }
143 
144 /*
145  * Platform hooks.
146  *
147  */
148 
__hlwd_quiesce(void __iomem * io_base)149 static void __hlwd_quiesce(void __iomem *io_base)
150 {
151 	/* mask and ack all IRQs */
152 	out_be32(io_base + HW_BROADWAY_IMR, 0);
153 	out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
154 }
155 
hlwd_pic_init(struct device_node * np)156 static struct irq_domain *__init hlwd_pic_init(struct device_node *np)
157 {
158 	struct irq_domain *irq_domain;
159 	struct resource res;
160 	void __iomem *io_base;
161 	int retval;
162 
163 	retval = of_address_to_resource(np, 0, &res);
164 	if (retval) {
165 		pr_err("no io memory range found\n");
166 		return NULL;
167 	}
168 	io_base = ioremap(res.start, resource_size(&res));
169 	if (!io_base) {
170 		pr_err("ioremap failed\n");
171 		return NULL;
172 	}
173 
174 	pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
175 
176 	__hlwd_quiesce(io_base);
177 
178 	irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
179 					   &hlwd_irq_domain_ops, io_base);
180 	if (!irq_domain) {
181 		pr_err("failed to allocate irq_domain\n");
182 		iounmap(io_base);
183 		return NULL;
184 	}
185 
186 	return irq_domain;
187 }
188 
hlwd_pic_get_irq(void)189 unsigned int hlwd_pic_get_irq(void)
190 {
191 	unsigned int hwirq = __hlwd_pic_get_irq(hlwd_irq_host);
192 	return hwirq ? irq_linear_revmap(hlwd_irq_host, hwirq) : 0;
193 }
194 
195 /*
196  * Probe function.
197  *
198  */
199 
hlwd_pic_probe(void)200 void __init hlwd_pic_probe(void)
201 {
202 	struct irq_domain *host;
203 	struct device_node *np;
204 	const u32 *interrupts;
205 	int cascade_virq;
206 
207 	for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
208 		interrupts = of_get_property(np, "interrupts", NULL);
209 		if (interrupts) {
210 			host = hlwd_pic_init(np);
211 			BUG_ON(!host);
212 			cascade_virq = irq_of_parse_and_map(np, 0);
213 			irq_set_handler_data(cascade_virq, host);
214 			irq_set_chained_handler(cascade_virq,
215 						hlwd_pic_irq_cascade);
216 			hlwd_irq_host = host;
217 			of_node_put(np);
218 			break;
219 		}
220 	}
221 }
222 
223 /**
224  * hlwd_quiesce() - quiesce hollywood irq controller
225  *
226  * Mask and ack all interrupt sources.
227  *
228  */
hlwd_quiesce(void)229 void hlwd_quiesce(void)
230 {
231 	void __iomem *io_base = hlwd_irq_host->host_data;
232 
233 	__hlwd_quiesce(io_base);
234 }
235 
236