1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     DDR-PHY500 driver
9  */
10 #ifndef MOD_DDR_PHY500_H
11 #define MOD_DDR_PHY500_H
12 
13 #include <fwk_id.h>
14 #include <fwk_macros.h>
15 #include <fwk_module.h>
16 
17 #include <stdbool.h>
18 #include <stdint.h>
19 
20 /*!
21  * \addtogroup GroupModules Modules
22  * \{
23  */
24 
25 /*!
26  * \addtogroup GroupDDR DDR PHY500 Driver
27  * \{
28  */
29 
30 /*!
31  * \brief DDR PHY500 register definitions.
32  */
33 struct mod_ddr_phy500_reg {
34     /*!
35      * \cond
36      */
37     FWK_RW  uint32_t      INIT_COMPLETE;
38     FWK_RW  uint32_t      MEMORY_WIDTH;
39     FWK_RW  uint32_t      READ_DELAY;
40     FWK_RW  uint32_t      CAPTURE_MASK;
41     FWK_RW  uint32_t      CAS_LATENCY;
42     FWK_RW  uint32_t      T_CTRL_DELAY;
43     FWK_RW  uint32_t      T_WRLAT;
44     FWK_RW  uint32_t      T_RDDATA_EN;
45     FWK_RW  uint32_t      T_RDLAT;
46     FWK_RW  uint32_t      DFI_PHYUPD_REQ;
47     FWK_R   uint32_t      DFI_PHYUPD_ACK;
48     FWK_R   uint32_t      DFI_LP_REQ;
49     FWK_RW  uint32_t      DFI_LP_ACK;
50     FWK_RW  uint32_t      DFI_RDLVL_REQ;
51     FWK_R   uint32_t      DFI_RDLVL_EN;
52     FWK_RW  uint32_t      DFI_WRLVL_REQ;
53     FWK_R   uint32_t      DFI_WRLVL_EN;
54     FWK_RW  uint32_t      DFI_PHYMSTR_REQ;
55     FWK_RW  uint32_t      DFI_PHYMSTR_ACK;
56     FWK_RW  uint32_t      DFI_WR_PREMBL;
57             uint8_t       RESERVED[0x820 - 0x50];
58     FWK_RW  uint32_t      DELAY_SEL;
59     FWK_RW  uint32_t      REF_EN;
60     FWK_RW  uint32_t      T_CTRL_UPD_MIN;
61     /*!
62      * \endcond
63      */
64 };
65 
66 /*!
67  * \brief Element configuration.
68  */
69 struct mod_ddr_phy500_element_config {
70     /*! Base address of a device configuration register. */
71     uintptr_t ddr;
72 };
73 
74 /*!
75  * \brief DDR PHY500 module configuration.
76  */
77 struct mod_ddr_phy500_module_config {
78     /*!
79     * Pointer to a structure containing default values for a subset of the PHY's
80     * configuration registers. These values are common to all PHYs that are
81     * represented by elements in the module's element table.
82     */
83     const struct mod_ddr_phy500_reg *ddr_reg_val;
84 
85     /*!
86      * Indicate whether the \c INIT_COMPLETE register of the peripheral needs to
87      * be initialized.
88      */
89     bool initialize_init_complete;
90 
91     /*!
92      * Indicate whether the \c REF_EN register of the peripheral needs to be
93      * initialized.
94      */
95     bool initialize_ref_en;
96 };
97 
98 /*!
99  * \}
100  */
101 
102 /*!
103  * \}
104  */
105 
106 #endif /* MOD_DDR_PHY500_H */
107