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Searched defs:inst_idx (Results 1 – 7 of 7) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v2_5.c451 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode()
665 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode()
774 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, in vcn_v2_6_enable_ras()
801 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_start_dpg_mode()
1336 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v2_5_stop_dpg_mode()
1433 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_5_pause_dpg_mode()
A Dvcn_v4_0.c422 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_mc_resume_dpg_mode()
762 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode()
869 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, in vcn_v4_0_enable_ras()
900 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_start_dpg_mode()
1417 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_stop_dpg_mode()
1529 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, in vcn_v4_0_pause_dpg_mode()
A Dvcn_v3_0.c496 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_mc_resume_dpg_mode()
825 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode()
940 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_start_dpg_mode()
1491 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v3_0_stop_dpg_mode()
1598 int inst_idx, struct dpg_pause_state *new_state) in vcn_v3_0_pause_dpg_mode()
A Damdgpu_vcn.h81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ argument
144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ argument
A Dvcn_v1_0.c1210 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode()
A Dvcn_v2_0.c1202 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode()
A Damdgpu_psp.c2831 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, in psp_update_vcn_sram()

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