1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35
36 #include "i915_drv.h"
37 #include "i915_irq.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crt.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
43 #include "intel_ddi_buf_trans.h"
44 #include "intel_de.h"
45 #include "intel_display_types.h"
46 #include "intel_fdi.h"
47 #include "intel_fifo_underrun.h"
48 #include "intel_gmbus.h"
49 #include "intel_hotplug.h"
50 #include "intel_pch_display.h"
51 #include "intel_pch_refclk.h"
52
53 /* Here's the desired hotplug mode */
54 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
55 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
56 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
57 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
58 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
59 ADPA_CRT_HOTPLUG_ENABLE)
60
61 struct intel_crt {
62 struct intel_encoder base;
63 /* DPMS state is stored in the connector, which we need in the
64 * encoder's enable/disable callbacks */
65 struct intel_connector *connector;
66 bool force_hotplug_required;
67 i915_reg_t adpa_reg;
68 };
69
intel_encoder_to_crt(struct intel_encoder * encoder)70 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
71 {
72 return container_of(encoder, struct intel_crt, base);
73 }
74
intel_attached_crt(struct intel_connector * connector)75 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
76 {
77 return intel_encoder_to_crt(intel_attached_encoder(connector));
78 }
79
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)80 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
81 i915_reg_t adpa_reg, enum pipe *pipe)
82 {
83 u32 val;
84
85 val = intel_de_read(dev_priv, adpa_reg);
86
87 /* asserts want to know the pipe even if the port is disabled */
88 if (HAS_PCH_CPT(dev_priv))
89 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
90 else
91 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
92
93 return val & ADPA_DAC_ENABLE;
94 }
95
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)96 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
97 enum pipe *pipe)
98 {
99 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
100 struct intel_crt *crt = intel_encoder_to_crt(encoder);
101 intel_wakeref_t wakeref;
102 bool ret;
103
104 wakeref = intel_display_power_get_if_enabled(dev_priv,
105 encoder->power_domain);
106 if (!wakeref)
107 return false;
108
109 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
110
111 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
112
113 return ret;
114 }
115
intel_crt_get_flags(struct intel_encoder * encoder)116 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
117 {
118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
119 struct intel_crt *crt = intel_encoder_to_crt(encoder);
120 u32 tmp, flags = 0;
121
122 tmp = intel_de_read(dev_priv, crt->adpa_reg);
123
124 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
125 flags |= DRM_MODE_FLAG_PHSYNC;
126 else
127 flags |= DRM_MODE_FLAG_NHSYNC;
128
129 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
130 flags |= DRM_MODE_FLAG_PVSYNC;
131 else
132 flags |= DRM_MODE_FLAG_NVSYNC;
133
134 return flags;
135 }
136
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)137 static void intel_crt_get_config(struct intel_encoder *encoder,
138 struct intel_crtc_state *pipe_config)
139 {
140 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
141
142 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
143
144 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
145 }
146
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)147 static void hsw_crt_get_config(struct intel_encoder *encoder,
148 struct intel_crtc_state *pipe_config)
149 {
150 lpt_pch_get_config(pipe_config);
151
152 hsw_ddi_get_config(encoder, pipe_config);
153
154 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
155 DRM_MODE_FLAG_NHSYNC |
156 DRM_MODE_FLAG_PVSYNC |
157 DRM_MODE_FLAG_NVSYNC);
158 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
159 }
160
161 /* Note: The caller is required to filter out dpms modes not supported by the
162 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)163 static void intel_crt_set_dpms(struct intel_encoder *encoder,
164 const struct intel_crtc_state *crtc_state,
165 int mode)
166 {
167 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
168 struct intel_crt *crt = intel_encoder_to_crt(encoder);
169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
170 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
171 u32 adpa;
172
173 if (DISPLAY_VER(dev_priv) >= 5)
174 adpa = ADPA_HOTPLUG_BITS;
175 else
176 adpa = 0;
177
178 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
179 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
180 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
181 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
182
183 /* For CPT allow 3 pipe config, for others just use A or B */
184 if (HAS_PCH_LPT(dev_priv))
185 ; /* Those bits don't exist here */
186 else if (HAS_PCH_CPT(dev_priv))
187 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
188 else
189 adpa |= ADPA_PIPE_SEL(crtc->pipe);
190
191 if (!HAS_PCH_SPLIT(dev_priv))
192 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
193
194 switch (mode) {
195 case DRM_MODE_DPMS_ON:
196 adpa |= ADPA_DAC_ENABLE;
197 break;
198 case DRM_MODE_DPMS_STANDBY:
199 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
200 break;
201 case DRM_MODE_DPMS_SUSPEND:
202 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
203 break;
204 case DRM_MODE_DPMS_OFF:
205 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
206 break;
207 }
208
209 intel_de_write(dev_priv, crt->adpa_reg, adpa);
210 }
211
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)212 static void intel_disable_crt(struct intel_atomic_state *state,
213 struct intel_encoder *encoder,
214 const struct intel_crtc_state *old_crtc_state,
215 const struct drm_connector_state *old_conn_state)
216 {
217 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
218 }
219
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)220 static void pch_disable_crt(struct intel_atomic_state *state,
221 struct intel_encoder *encoder,
222 const struct intel_crtc_state *old_crtc_state,
223 const struct drm_connector_state *old_conn_state)
224 {
225 }
226
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)227 static void pch_post_disable_crt(struct intel_atomic_state *state,
228 struct intel_encoder *encoder,
229 const struct intel_crtc_state *old_crtc_state,
230 const struct drm_connector_state *old_conn_state)
231 {
232 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
233 }
234
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)235 static void hsw_disable_crt(struct intel_atomic_state *state,
236 struct intel_encoder *encoder,
237 const struct intel_crtc_state *old_crtc_state,
238 const struct drm_connector_state *old_conn_state)
239 {
240 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241
242 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
243
244 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
245 }
246
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)247 static void hsw_post_disable_crt(struct intel_atomic_state *state,
248 struct intel_encoder *encoder,
249 const struct intel_crtc_state *old_crtc_state,
250 const struct drm_connector_state *old_conn_state)
251 {
252 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254
255 intel_crtc_vblank_off(old_crtc_state);
256
257 intel_disable_transcoder(old_crtc_state);
258
259 intel_ddi_disable_transcoder_func(old_crtc_state);
260
261 ilk_pfit_disable(old_crtc_state);
262
263 intel_ddi_disable_pipe_clock(old_crtc_state);
264
265 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
266
267 lpt_pch_disable(state, crtc);
268
269 hsw_fdi_disable(encoder);
270
271 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
272
273 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
274 }
275
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)276 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
277 struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
279 const struct drm_connector_state *conn_state)
280 {
281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
282
283 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
284
285 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
286 }
287
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)288 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
289 struct intel_encoder *encoder,
290 const struct intel_crtc_state *crtc_state,
291 const struct drm_connector_state *conn_state)
292 {
293 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
294 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
295 enum pipe pipe = crtc->pipe;
296
297 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
298
299 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
300
301 hsw_fdi_link_train(encoder, crtc_state);
302
303 intel_ddi_enable_pipe_clock(encoder, crtc_state);
304 }
305
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)306 static void hsw_enable_crt(struct intel_atomic_state *state,
307 struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
309 const struct drm_connector_state *conn_state)
310 {
311 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
312 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
313 enum pipe pipe = crtc->pipe;
314
315 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
316
317 intel_ddi_enable_transcoder_func(encoder, crtc_state);
318
319 intel_enable_transcoder(crtc_state);
320
321 lpt_pch_enable(state, crtc);
322
323 intel_crtc_vblank_on(crtc_state);
324
325 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
326
327 intel_crtc_wait_for_next_vblank(crtc);
328 intel_crtc_wait_for_next_vblank(crtc);
329 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
330 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
331 }
332
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)333 static void intel_enable_crt(struct intel_atomic_state *state,
334 struct intel_encoder *encoder,
335 const struct intel_crtc_state *crtc_state,
336 const struct drm_connector_state *conn_state)
337 {
338 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
339 }
340
341 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)342 intel_crt_mode_valid(struct drm_connector *connector,
343 struct drm_display_mode *mode)
344 {
345 struct drm_device *dev = connector->dev;
346 struct drm_i915_private *dev_priv = to_i915(dev);
347 int max_dotclk = dev_priv->max_dotclk_freq;
348 int max_clock;
349
350 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
351 return MODE_NO_DBLESCAN;
352
353 if (mode->clock < 25000)
354 return MODE_CLOCK_LOW;
355
356 if (HAS_PCH_LPT(dev_priv))
357 max_clock = 180000;
358 else if (IS_VALLEYVIEW(dev_priv))
359 /*
360 * 270 MHz due to current DPLL limits,
361 * DAC limit supposedly 355 MHz.
362 */
363 max_clock = 270000;
364 else if (IS_DISPLAY_VER(dev_priv, 3, 4))
365 max_clock = 400000;
366 else
367 max_clock = 350000;
368 if (mode->clock > max_clock)
369 return MODE_CLOCK_HIGH;
370
371 if (mode->clock > max_dotclk)
372 return MODE_CLOCK_HIGH;
373
374 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
375 if (HAS_PCH_LPT(dev_priv) &&
376 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
377 return MODE_CLOCK_HIGH;
378
379 /* HSW/BDW FDI limited to 4k */
380 if (mode->hdisplay > 4096)
381 return MODE_H_ILLEGAL;
382
383 return MODE_OK;
384 }
385
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)386 static int intel_crt_compute_config(struct intel_encoder *encoder,
387 struct intel_crtc_state *pipe_config,
388 struct drm_connector_state *conn_state)
389 {
390 struct drm_display_mode *adjusted_mode =
391 &pipe_config->hw.adjusted_mode;
392
393 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
394 return -EINVAL;
395
396 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
397
398 return 0;
399 }
400
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)401 static int pch_crt_compute_config(struct intel_encoder *encoder,
402 struct intel_crtc_state *pipe_config,
403 struct drm_connector_state *conn_state)
404 {
405 struct drm_display_mode *adjusted_mode =
406 &pipe_config->hw.adjusted_mode;
407
408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
409 return -EINVAL;
410
411 pipe_config->has_pch_encoder = true;
412 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
413
414 return 0;
415 }
416
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)417 static int hsw_crt_compute_config(struct intel_encoder *encoder,
418 struct intel_crtc_state *pipe_config,
419 struct drm_connector_state *conn_state)
420 {
421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
422 struct drm_display_mode *adjusted_mode =
423 &pipe_config->hw.adjusted_mode;
424
425 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
426 return -EINVAL;
427
428 /* HSW/BDW FDI limited to 4k */
429 if (adjusted_mode->crtc_hdisplay > 4096 ||
430 adjusted_mode->crtc_hblank_start > 4096)
431 return -EINVAL;
432
433 pipe_config->has_pch_encoder = true;
434 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
435
436 /* LPT FDI RX only supports 8bpc. */
437 if (HAS_PCH_LPT(dev_priv)) {
438 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
439 drm_dbg_kms(&dev_priv->drm,
440 "LPT only supports 24bpp\n");
441 return -EINVAL;
442 }
443
444 pipe_config->pipe_bpp = 24;
445 }
446
447 /* FDI must always be 2.7 GHz */
448 pipe_config->port_clock = 135000 * 2;
449
450 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
451
452 return 0;
453 }
454
ilk_crt_detect_hotplug(struct drm_connector * connector)455 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
456 {
457 struct drm_device *dev = connector->dev;
458 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
459 struct drm_i915_private *dev_priv = to_i915(dev);
460 u32 adpa;
461 bool ret;
462
463 /* The first time through, trigger an explicit detection cycle */
464 if (crt->force_hotplug_required) {
465 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
466 u32 save_adpa;
467
468 crt->force_hotplug_required = false;
469
470 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
471 drm_dbg_kms(&dev_priv->drm,
472 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
473
474 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
475 if (turn_off_dac)
476 adpa &= ~ADPA_DAC_ENABLE;
477
478 intel_de_write(dev_priv, crt->adpa_reg, adpa);
479
480 if (intel_de_wait_for_clear(dev_priv,
481 crt->adpa_reg,
482 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
483 1000))
484 drm_dbg_kms(&dev_priv->drm,
485 "timed out waiting for FORCE_TRIGGER");
486
487 if (turn_off_dac) {
488 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
489 intel_de_posting_read(dev_priv, crt->adpa_reg);
490 }
491 }
492
493 /* Check the status to see if both blue and green are on now */
494 adpa = intel_de_read(dev_priv, crt->adpa_reg);
495 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
496 ret = true;
497 else
498 ret = false;
499 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
500 adpa, ret);
501
502 return ret;
503 }
504
valleyview_crt_detect_hotplug(struct drm_connector * connector)505 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
506 {
507 struct drm_device *dev = connector->dev;
508 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
509 struct drm_i915_private *dev_priv = to_i915(dev);
510 bool reenable_hpd;
511 u32 adpa;
512 bool ret;
513 u32 save_adpa;
514
515 /*
516 * Doing a force trigger causes a hpd interrupt to get sent, which can
517 * get us stuck in a loop if we're polling:
518 * - We enable power wells and reset the ADPA
519 * - output_poll_exec does force probe on VGA, triggering a hpd
520 * - HPD handler waits for poll to unlock dev->mode_config.mutex
521 * - output_poll_exec shuts off the ADPA, unlocks
522 * dev->mode_config.mutex
523 * - HPD handler runs, resets ADPA and brings us back to the start
524 *
525 * Just disable HPD interrupts here to prevent this
526 */
527 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
528
529 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
530 drm_dbg_kms(&dev_priv->drm,
531 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
532
533 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
534
535 intel_de_write(dev_priv, crt->adpa_reg, adpa);
536
537 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
538 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
539 drm_dbg_kms(&dev_priv->drm,
540 "timed out waiting for FORCE_TRIGGER");
541 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
542 }
543
544 /* Check the status to see if both blue and green are on now */
545 adpa = intel_de_read(dev_priv, crt->adpa_reg);
546 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
547 ret = true;
548 else
549 ret = false;
550
551 drm_dbg_kms(&dev_priv->drm,
552 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
553
554 if (reenable_hpd)
555 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
556
557 return ret;
558 }
559
intel_crt_detect_hotplug(struct drm_connector * connector)560 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
561 {
562 struct drm_device *dev = connector->dev;
563 struct drm_i915_private *dev_priv = to_i915(dev);
564 u32 stat;
565 bool ret = false;
566 int i, tries = 0;
567
568 if (HAS_PCH_SPLIT(dev_priv))
569 return ilk_crt_detect_hotplug(connector);
570
571 if (IS_VALLEYVIEW(dev_priv))
572 return valleyview_crt_detect_hotplug(connector);
573
574 /*
575 * On 4 series desktop, CRT detect sequence need to be done twice
576 * to get a reliable result.
577 */
578
579 if (IS_G45(dev_priv))
580 tries = 2;
581 else
582 tries = 1;
583
584 for (i = 0; i < tries ; i++) {
585 /* turn on the FORCE_DETECT */
586 i915_hotplug_interrupt_update(dev_priv,
587 CRT_HOTPLUG_FORCE_DETECT,
588 CRT_HOTPLUG_FORCE_DETECT);
589 /* wait for FORCE_DETECT to go off */
590 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
591 CRT_HOTPLUG_FORCE_DETECT, 1000))
592 drm_dbg_kms(&dev_priv->drm,
593 "timed out waiting for FORCE_DETECT to go off");
594 }
595
596 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
597 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
598 ret = true;
599
600 /* clear the interrupt we just generated, if any */
601 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
602
603 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
604
605 return ret;
606 }
607
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)608 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
609 struct i2c_adapter *i2c)
610 {
611 struct edid *edid;
612
613 edid = drm_get_edid(connector, i2c);
614
615 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
616 drm_dbg_kms(connector->dev,
617 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
618 intel_gmbus_force_bit(i2c, true);
619 edid = drm_get_edid(connector, i2c);
620 intel_gmbus_force_bit(i2c, false);
621 }
622
623 return edid;
624 }
625
626 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)627 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
628 struct i2c_adapter *adapter)
629 {
630 struct edid *edid;
631 int ret;
632
633 edid = intel_crt_get_edid(connector, adapter);
634 if (!edid)
635 return 0;
636
637 ret = intel_connector_update_modes(connector, edid);
638 kfree(edid);
639
640 return ret;
641 }
642
intel_crt_detect_ddc(struct drm_connector * connector)643 static bool intel_crt_detect_ddc(struct drm_connector *connector)
644 {
645 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
646 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
647 struct edid *edid;
648 struct i2c_adapter *i2c;
649 bool ret = false;
650
651 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
652 edid = intel_crt_get_edid(connector, i2c);
653
654 if (edid) {
655 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
656
657 /*
658 * This may be a DVI-I connector with a shared DDC
659 * link between analog and digital outputs, so we
660 * have to check the EDID input spec of the attached device.
661 */
662 if (!is_digital) {
663 drm_dbg_kms(&dev_priv->drm,
664 "CRT detected via DDC:0x50 [EDID]\n");
665 ret = true;
666 } else {
667 drm_dbg_kms(&dev_priv->drm,
668 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
669 }
670 } else {
671 drm_dbg_kms(&dev_priv->drm,
672 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
673 }
674
675 kfree(edid);
676
677 return ret;
678 }
679
680 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,u32 pipe)681 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
682 {
683 struct drm_device *dev = crt->base.base.dev;
684 struct drm_i915_private *dev_priv = to_i915(dev);
685 u32 save_bclrpat;
686 u32 save_vtotal;
687 u32 vtotal, vactive;
688 u32 vsample;
689 u32 vblank, vblank_start, vblank_end;
690 u32 dsl;
691 u8 st00;
692 enum drm_connector_status status;
693
694 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
695
696 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(pipe));
697 save_vtotal = intel_de_read(dev_priv, VTOTAL(pipe));
698 vblank = intel_de_read(dev_priv, VBLANK(pipe));
699
700 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
701 vactive = (save_vtotal & 0x7ff) + 1;
702
703 vblank_start = (vblank & 0xfff) + 1;
704 vblank_end = ((vblank >> 16) & 0xfff) + 1;
705
706 /* Set the border color to purple. */
707 intel_de_write(dev_priv, BCLRPAT(pipe), 0x500050);
708
709 if (DISPLAY_VER(dev_priv) != 2) {
710 u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
711
712 intel_de_write(dev_priv, PIPECONF(pipe),
713 pipeconf | PIPECONF_FORCE_BORDER);
714 intel_de_posting_read(dev_priv, PIPECONF(pipe));
715 /* Wait for next Vblank to substitue
716 * border color for Color info */
717 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
718 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
719 status = ((st00 & (1 << 4)) != 0) ?
720 connector_status_connected :
721 connector_status_disconnected;
722
723 intel_de_write(dev_priv, PIPECONF(pipe), pipeconf);
724 } else {
725 bool restore_vblank = false;
726 int count, detect;
727
728 /*
729 * If there isn't any border, add some.
730 * Yes, this will flicker
731 */
732 if (vblank_start <= vactive && vblank_end >= vtotal) {
733 u32 vsync = intel_de_read(dev_priv, VSYNC(pipe));
734 u32 vsync_start = (vsync & 0xffff) + 1;
735
736 vblank_start = vsync_start;
737 intel_de_write(dev_priv, VBLANK(pipe),
738 (vblank_start - 1) | ((vblank_end - 1) << 16));
739 restore_vblank = true;
740 }
741 /* sample in the vertical border, selecting the larger one */
742 if (vblank_start - vactive >= vtotal - vblank_end)
743 vsample = (vblank_start + vactive) >> 1;
744 else
745 vsample = (vtotal + vblank_end) >> 1;
746
747 /*
748 * Wait for the border to be displayed
749 */
750 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
751 ;
752 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
753 ;
754 /*
755 * Watch ST00 for an entire scanline
756 */
757 detect = 0;
758 count = 0;
759 do {
760 count++;
761 /* Read the ST00 VGA status register */
762 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
763 if (st00 & (1 << 4))
764 detect++;
765 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
766
767 /* restore vblank if necessary */
768 if (restore_vblank)
769 intel_de_write(dev_priv, VBLANK(pipe), vblank);
770 /*
771 * If more than 3/4 of the scanline detected a monitor,
772 * then it is assumed to be present. This works even on i830,
773 * where there isn't any way to force the border color across
774 * the screen
775 */
776 status = detect * 4 > count * 3 ?
777 connector_status_connected :
778 connector_status_disconnected;
779 }
780
781 /* Restore previous settings */
782 intel_de_write(dev_priv, BCLRPAT(pipe), save_bclrpat);
783
784 return status;
785 }
786
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)787 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
788 {
789 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
790 return 1;
791 }
792
793 static const struct dmi_system_id intel_spurious_crt_detect[] = {
794 {
795 .callback = intel_spurious_crt_detect_dmi_callback,
796 .ident = "ACER ZGB",
797 .matches = {
798 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
799 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
800 },
801 },
802 {
803 .callback = intel_spurious_crt_detect_dmi_callback,
804 .ident = "Intel DZ77BH-55K",
805 .matches = {
806 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
807 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
808 },
809 },
810 { }
811 };
812
813 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)814 intel_crt_detect(struct drm_connector *connector,
815 struct drm_modeset_acquire_ctx *ctx,
816 bool force)
817 {
818 struct drm_i915_private *dev_priv = to_i915(connector->dev);
819 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
820 struct intel_encoder *intel_encoder = &crt->base;
821 intel_wakeref_t wakeref;
822 int status, ret;
823 struct intel_load_detect_pipe tmp;
824
825 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
826 connector->base.id, connector->name,
827 force);
828
829 if (!INTEL_DISPLAY_ENABLED(dev_priv))
830 return connector_status_disconnected;
831
832 if (dev_priv->params.load_detect_test) {
833 wakeref = intel_display_power_get(dev_priv,
834 intel_encoder->power_domain);
835 goto load_detect;
836 }
837
838 /* Skip machines without VGA that falsely report hotplug events */
839 if (dmi_check_system(intel_spurious_crt_detect))
840 return connector_status_disconnected;
841
842 wakeref = intel_display_power_get(dev_priv,
843 intel_encoder->power_domain);
844
845 if (I915_HAS_HOTPLUG(dev_priv)) {
846 /* We can not rely on the HPD pin always being correctly wired
847 * up, for example many KVM do not pass it through, and so
848 * only trust an assertion that the monitor is connected.
849 */
850 if (intel_crt_detect_hotplug(connector)) {
851 drm_dbg_kms(&dev_priv->drm,
852 "CRT detected via hotplug\n");
853 status = connector_status_connected;
854 goto out;
855 } else
856 drm_dbg_kms(&dev_priv->drm,
857 "CRT not detected via hotplug\n");
858 }
859
860 if (intel_crt_detect_ddc(connector)) {
861 status = connector_status_connected;
862 goto out;
863 }
864
865 /* Load detection is broken on HPD capable machines. Whoever wants a
866 * broken monitor (without edid) to work behind a broken kvm (that fails
867 * to have the right resistors for HP detection) needs to fix this up.
868 * For now just bail out. */
869 if (I915_HAS_HOTPLUG(dev_priv)) {
870 status = connector_status_disconnected;
871 goto out;
872 }
873
874 load_detect:
875 if (!force) {
876 status = connector->status;
877 goto out;
878 }
879
880 /* for pre-945g platforms use load detect */
881 ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
882 if (ret > 0) {
883 if (intel_crt_detect_ddc(connector))
884 status = connector_status_connected;
885 else if (DISPLAY_VER(dev_priv) < 4)
886 status = intel_crt_load_detect(crt,
887 to_intel_crtc(connector->state->crtc)->pipe);
888 else if (dev_priv->params.load_detect_test)
889 status = connector_status_disconnected;
890 else
891 status = connector_status_unknown;
892 intel_release_load_detect_pipe(connector, &tmp, ctx);
893 } else if (ret == 0) {
894 status = connector_status_unknown;
895 } else {
896 status = ret;
897 }
898
899 out:
900 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
901
902 /*
903 * Make sure the refs for power wells enabled during detect are
904 * dropped to avoid a new detect cycle triggered by HPD polling.
905 */
906 intel_display_power_flush_work(dev_priv);
907
908 return status;
909 }
910
intel_crt_get_modes(struct drm_connector * connector)911 static int intel_crt_get_modes(struct drm_connector *connector)
912 {
913 struct drm_device *dev = connector->dev;
914 struct drm_i915_private *dev_priv = to_i915(dev);
915 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
916 struct intel_encoder *intel_encoder = &crt->base;
917 intel_wakeref_t wakeref;
918 struct i2c_adapter *i2c;
919 int ret;
920
921 wakeref = intel_display_power_get(dev_priv,
922 intel_encoder->power_domain);
923
924 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
925 ret = intel_crt_ddc_get_modes(connector, i2c);
926 if (ret || !IS_G4X(dev_priv))
927 goto out;
928
929 /* Try to probe digital port for output in DVI-I -> VGA mode. */
930 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
931 ret = intel_crt_ddc_get_modes(connector, i2c);
932
933 out:
934 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
935
936 return ret;
937 }
938
intel_crt_reset(struct drm_encoder * encoder)939 void intel_crt_reset(struct drm_encoder *encoder)
940 {
941 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
942 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
943
944 if (DISPLAY_VER(dev_priv) >= 5) {
945 u32 adpa;
946
947 adpa = intel_de_read(dev_priv, crt->adpa_reg);
948 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
949 adpa |= ADPA_HOTPLUG_BITS;
950 intel_de_write(dev_priv, crt->adpa_reg, adpa);
951 intel_de_posting_read(dev_priv, crt->adpa_reg);
952
953 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
954 crt->force_hotplug_required = true;
955 }
956
957 }
958
959 /*
960 * Routines for controlling stuff on the analog port
961 */
962
963 static const struct drm_connector_funcs intel_crt_connector_funcs = {
964 .fill_modes = drm_helper_probe_single_connector_modes,
965 .late_register = intel_connector_register,
966 .early_unregister = intel_connector_unregister,
967 .destroy = intel_connector_destroy,
968 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
969 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
970 };
971
972 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
973 .detect_ctx = intel_crt_detect,
974 .mode_valid = intel_crt_mode_valid,
975 .get_modes = intel_crt_get_modes,
976 };
977
978 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
979 .reset = intel_crt_reset,
980 .destroy = intel_encoder_destroy,
981 };
982
intel_crt_init(struct drm_i915_private * dev_priv)983 void intel_crt_init(struct drm_i915_private *dev_priv)
984 {
985 struct drm_connector *connector;
986 struct intel_crt *crt;
987 struct intel_connector *intel_connector;
988 i915_reg_t adpa_reg;
989 u32 adpa;
990
991 if (HAS_PCH_SPLIT(dev_priv))
992 adpa_reg = PCH_ADPA;
993 else if (IS_VALLEYVIEW(dev_priv))
994 adpa_reg = VLV_ADPA;
995 else
996 adpa_reg = ADPA;
997
998 adpa = intel_de_read(dev_priv, adpa_reg);
999 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1000 /*
1001 * On some machines (some IVB at least) CRT can be
1002 * fused off, but there's no known fuse bit to
1003 * indicate that. On these machine the ADPA register
1004 * works normally, except the DAC enable bit won't
1005 * take. So the only way to tell is attempt to enable
1006 * it and see what happens.
1007 */
1008 intel_de_write(dev_priv, adpa_reg,
1009 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1010 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1011 return;
1012 intel_de_write(dev_priv, adpa_reg, adpa);
1013 }
1014
1015 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1016 if (!crt)
1017 return;
1018
1019 intel_connector = intel_connector_alloc();
1020 if (!intel_connector) {
1021 kfree(crt);
1022 return;
1023 }
1024
1025 connector = &intel_connector->base;
1026 crt->connector = intel_connector;
1027 drm_connector_init(&dev_priv->drm, &intel_connector->base,
1028 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1029
1030 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1031 DRM_MODE_ENCODER_DAC, "CRT");
1032
1033 intel_connector_attach_encoder(intel_connector, &crt->base);
1034
1035 crt->base.type = INTEL_OUTPUT_ANALOG;
1036 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1037 if (IS_I830(dev_priv))
1038 crt->base.pipe_mask = BIT(PIPE_A);
1039 else
1040 crt->base.pipe_mask = ~0;
1041
1042 if (DISPLAY_VER(dev_priv) != 2)
1043 connector->interlace_allowed = true;
1044
1045 crt->adpa_reg = adpa_reg;
1046
1047 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1048
1049 if (I915_HAS_HOTPLUG(dev_priv) &&
1050 !dmi_check_system(intel_spurious_crt_detect)) {
1051 crt->base.hpd_pin = HPD_CRT;
1052 crt->base.hotplug = intel_encoder_hotplug;
1053 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1054 } else {
1055 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1056 }
1057
1058 if (HAS_DDI(dev_priv)) {
1059 crt->base.port = PORT_E;
1060 crt->base.get_config = hsw_crt_get_config;
1061 crt->base.get_hw_state = intel_ddi_get_hw_state;
1062 crt->base.compute_config = hsw_crt_compute_config;
1063 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1064 crt->base.pre_enable = hsw_pre_enable_crt;
1065 crt->base.enable = hsw_enable_crt;
1066 crt->base.disable = hsw_disable_crt;
1067 crt->base.post_disable = hsw_post_disable_crt;
1068 crt->base.enable_clock = hsw_ddi_enable_clock;
1069 crt->base.disable_clock = hsw_ddi_disable_clock;
1070 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1071
1072 intel_ddi_buf_trans_init(&crt->base);
1073 } else {
1074 if (HAS_PCH_SPLIT(dev_priv)) {
1075 crt->base.compute_config = pch_crt_compute_config;
1076 crt->base.disable = pch_disable_crt;
1077 crt->base.post_disable = pch_post_disable_crt;
1078 } else {
1079 crt->base.compute_config = intel_crt_compute_config;
1080 crt->base.disable = intel_disable_crt;
1081 }
1082 crt->base.port = PORT_NONE;
1083 crt->base.get_config = intel_crt_get_config;
1084 crt->base.get_hw_state = intel_crt_get_hw_state;
1085 crt->base.enable = intel_enable_crt;
1086 }
1087 intel_connector->get_hw_state = intel_connector_get_hw_state;
1088
1089 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1090
1091 /*
1092 * TODO: find a proper way to discover whether we need to set the the
1093 * polarity and link reversal bits or not, instead of relying on the
1094 * BIOS.
1095 */
1096 if (HAS_PCH_LPT(dev_priv)) {
1097 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1098 FDI_RX_LINK_REVERSAL_OVERRIDE;
1099
1100 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1101 FDI_RX_CTL(PIPE_A)) & fdi_config;
1102 }
1103
1104 intel_crt_reset(&crt->base.base);
1105 }
1106