1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include <drm/drm_device.h>
7 #include <linux/sysfs.h>
8 #include <linux/printk.h>
9
10 #include "i915_drv.h"
11 #include "i915_reg.h"
12 #include "i915_sysfs.h"
13 #include "intel_gt.h"
14 #include "intel_gt_print.h"
15 #include "intel_gt_regs.h"
16 #include "intel_gt_sysfs.h"
17 #include "intel_gt_sysfs_pm.h"
18 #include "intel_pcode.h"
19 #include "intel_rc6.h"
20 #include "intel_rps.h"
21
22 enum intel_gt_sysfs_op {
23 INTEL_GT_SYSFS_MIN = 0,
24 INTEL_GT_SYSFS_MAX,
25 };
26
27 static int
sysfs_gt_attribute_w_func(struct kobject * kobj,struct attribute * attr,int (func)(struct intel_gt * gt,u32 val),u32 val)28 sysfs_gt_attribute_w_func(struct kobject *kobj, struct attribute *attr,
29 int (func)(struct intel_gt *gt, u32 val), u32 val)
30 {
31 struct intel_gt *gt;
32 int ret;
33
34 if (!is_object_gt(kobj)) {
35 int i;
36 struct device *dev = kobj_to_dev(kobj);
37 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
38
39 for_each_gt(gt, i915, i) {
40 ret = func(gt, val);
41 if (ret)
42 break;
43 }
44 } else {
45 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
46 ret = func(gt, val);
47 }
48
49 return ret;
50 }
51
52 static u32
sysfs_gt_attribute_r_func(struct kobject * kobj,struct attribute * attr,u32 (func)(struct intel_gt * gt),enum intel_gt_sysfs_op op)53 sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
54 u32 (func)(struct intel_gt *gt),
55 enum intel_gt_sysfs_op op)
56 {
57 struct intel_gt *gt;
58 u32 ret;
59
60 ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
61
62 if (!is_object_gt(kobj)) {
63 int i;
64 struct device *dev = kobj_to_dev(kobj);
65 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
66
67 for_each_gt(gt, i915, i) {
68 u32 val = func(gt);
69
70 switch (op) {
71 case INTEL_GT_SYSFS_MIN:
72 if (val < ret)
73 ret = val;
74 break;
75
76 case INTEL_GT_SYSFS_MAX:
77 if (val > ret)
78 ret = val;
79 break;
80 }
81 }
82 } else {
83 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
84 ret = func(gt);
85 }
86
87 return ret;
88 }
89
90 /* RC6 interfaces will show the minimum RC6 residency value */
91 #define sysfs_gt_attribute_r_min_func(d, a, f) \
92 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
93
94 /* Frequency interfaces will show the maximum frequency value */
95 #define sysfs_gt_attribute_r_max_func(d, a, f) \
96 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
97
98 #define INTEL_GT_SYSFS_SHOW(_name, _attr_type) \
99 static ssize_t _name##_show_common(struct kobject *kobj, \
100 struct attribute *attr, char *buff) \
101 { \
102 u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
103 __##_name##_show); \
104 \
105 return sysfs_emit(buff, "%u\n", val); \
106 } \
107 static ssize_t _name##_show(struct kobject *kobj, \
108 struct kobj_attribute *attr, char *buff) \
109 { \
110 return _name ##_show_common(kobj, &attr->attr, buff); \
111 } \
112 static ssize_t _name##_dev_show(struct device *dev, \
113 struct device_attribute *attr, char *buff) \
114 { \
115 return _name##_show_common(&dev->kobj, &attr->attr, buff); \
116 }
117
118 #define INTEL_GT_SYSFS_STORE(_name, _func) \
119 static ssize_t _name##_store_common(struct kobject *kobj, \
120 struct attribute *attr, \
121 const char *buff, size_t count) \
122 { \
123 int ret; \
124 u32 val; \
125 \
126 ret = kstrtou32(buff, 0, &val); \
127 if (ret) \
128 return ret; \
129 \
130 ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
131 \
132 return ret ?: count; \
133 } \
134 static ssize_t _name##_store(struct kobject *kobj, \
135 struct kobj_attribute *attr, const char *buff, \
136 size_t count) \
137 { \
138 return _name##_store_common(kobj, &attr->attr, buff, count); \
139 } \
140 static ssize_t _name##_dev_store(struct device *dev, \
141 struct device_attribute *attr, \
142 const char *buff, size_t count) \
143 { \
144 return _name##_store_common(&dev->kobj, &attr->attr, buff, count); \
145 }
146
147 #define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max)
148 #define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min)
149
150 #define INTEL_GT_ATTR_RW(_name) \
151 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
152
153 #define INTEL_GT_ATTR_RO(_name) \
154 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
155
156 #define INTEL_GT_DUAL_ATTR_RW(_name) \
157 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
158 _name##_dev_show, \
159 _name##_dev_store); \
160 INTEL_GT_ATTR_RW(_name)
161
162 #define INTEL_GT_DUAL_ATTR_RO(_name) \
163 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
164 _name##_dev_show, \
165 NULL); \
166 INTEL_GT_ATTR_RO(_name)
167
get_residency(struct intel_gt * gt,enum intel_rc6_res_type id)168 static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
169 {
170 intel_wakeref_t wakeref;
171 u64 res = 0;
172
173 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
174 res = intel_rc6_residency_us(>->rc6, id);
175
176 return DIV_ROUND_CLOSEST_ULL(res, 1000);
177 }
178
get_rc6_mask(struct intel_gt * gt)179 static u8 get_rc6_mask(struct intel_gt *gt)
180 {
181 u8 mask = 0;
182
183 if (HAS_RC6(gt->i915))
184 mask |= BIT(0);
185 if (HAS_RC6p(gt->i915))
186 mask |= BIT(1);
187 if (HAS_RC6pp(gt->i915))
188 mask |= BIT(2);
189
190 return mask;
191 }
192
rc6_enable_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)193 static ssize_t rc6_enable_show(struct kobject *kobj,
194 struct kobj_attribute *attr,
195 char *buff)
196 {
197 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
198
199 return sysfs_emit(buff, "%x\n", get_rc6_mask(gt));
200 }
201
rc6_enable_dev_show(struct device * dev,struct device_attribute * attr,char * buff)202 static ssize_t rc6_enable_dev_show(struct device *dev,
203 struct device_attribute *attr,
204 char *buff)
205 {
206 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(&dev->kobj, attr->attr.name);
207
208 return sysfs_emit(buff, "%x\n", get_rc6_mask(gt));
209 }
210
__rc6_residency_ms_show(struct intel_gt * gt)211 static u32 __rc6_residency_ms_show(struct intel_gt *gt)
212 {
213 return get_residency(gt, INTEL_RC6_RES_RC6);
214 }
215
__rc6p_residency_ms_show(struct intel_gt * gt)216 static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
217 {
218 return get_residency(gt, INTEL_RC6_RES_RC6p);
219 }
220
__rc6pp_residency_ms_show(struct intel_gt * gt)221 static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
222 {
223 return get_residency(gt, INTEL_RC6_RES_RC6pp);
224 }
225
__media_rc6_residency_ms_show(struct intel_gt * gt)226 static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
227 {
228 return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
229 }
230
231 INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);
232 INTEL_GT_SYSFS_SHOW_MIN(rc6p_residency_ms);
233 INTEL_GT_SYSFS_SHOW_MIN(rc6pp_residency_ms);
234 INTEL_GT_SYSFS_SHOW_MIN(media_rc6_residency_ms);
235
236 INTEL_GT_DUAL_ATTR_RO(rc6_enable);
237 INTEL_GT_DUAL_ATTR_RO(rc6_residency_ms);
238 INTEL_GT_DUAL_ATTR_RO(rc6p_residency_ms);
239 INTEL_GT_DUAL_ATTR_RO(rc6pp_residency_ms);
240 INTEL_GT_DUAL_ATTR_RO(media_rc6_residency_ms);
241
242 static struct attribute *rc6_attrs[] = {
243 &attr_rc6_enable.attr,
244 &attr_rc6_residency_ms.attr,
245 NULL
246 };
247
248 static struct attribute *rc6p_attrs[] = {
249 &attr_rc6p_residency_ms.attr,
250 &attr_rc6pp_residency_ms.attr,
251 NULL
252 };
253
254 static struct attribute *media_rc6_attrs[] = {
255 &attr_media_rc6_residency_ms.attr,
256 NULL
257 };
258
259 static struct attribute *rc6_dev_attrs[] = {
260 &dev_attr_rc6_enable.attr,
261 &dev_attr_rc6_residency_ms.attr,
262 NULL
263 };
264
265 static struct attribute *rc6p_dev_attrs[] = {
266 &dev_attr_rc6p_residency_ms.attr,
267 &dev_attr_rc6pp_residency_ms.attr,
268 NULL
269 };
270
271 static struct attribute *media_rc6_dev_attrs[] = {
272 &dev_attr_media_rc6_residency_ms.attr,
273 NULL
274 };
275
276 static const struct attribute_group rc6_attr_group[] = {
277 { .attrs = rc6_attrs, },
278 { .name = power_group_name, .attrs = rc6_dev_attrs, },
279 };
280
281 static const struct attribute_group rc6p_attr_group[] = {
282 { .attrs = rc6p_attrs, },
283 { .name = power_group_name, .attrs = rc6p_dev_attrs, },
284 };
285
286 static const struct attribute_group media_rc6_attr_group[] = {
287 { .attrs = media_rc6_attrs, },
288 { .name = power_group_name, .attrs = media_rc6_dev_attrs, },
289 };
290
__intel_gt_sysfs_create_group(struct kobject * kobj,const struct attribute_group * grp)291 static int __intel_gt_sysfs_create_group(struct kobject *kobj,
292 const struct attribute_group *grp)
293 {
294 return is_object_gt(kobj) ?
295 sysfs_create_group(kobj, &grp[0]) :
296 sysfs_merge_group(kobj, &grp[1]);
297 }
298
intel_sysfs_rc6_init(struct intel_gt * gt,struct kobject * kobj)299 static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
300 {
301 int ret;
302
303 if (!IS_ENABLED(CONFIG_PM) || !HAS_RC6(gt->i915))
304 return;
305
306 ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
307 if (ret)
308 gt_warn(gt, "failed to create RC6 sysfs files (%pe)\n", ERR_PTR(ret));
309
310 /*
311 * cannot use the is_visible() attribute because
312 * the upper object inherits from the parent group.
313 */
314 if (HAS_RC6p(gt->i915)) {
315 ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
316 if (ret)
317 gt_warn(gt, "failed to create RC6p sysfs files (%pe)\n", ERR_PTR(ret));
318 }
319
320 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
321 ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
322 if (ret)
323 gt_warn(gt, "failed to create media RC6 sysfs files (%pe)\n", ERR_PTR(ret));
324 }
325 }
326
__act_freq_mhz_show(struct intel_gt * gt)327 static u32 __act_freq_mhz_show(struct intel_gt *gt)
328 {
329 return intel_rps_read_actual_frequency(>->rps);
330 }
331
__cur_freq_mhz_show(struct intel_gt * gt)332 static u32 __cur_freq_mhz_show(struct intel_gt *gt)
333 {
334 return intel_rps_get_requested_frequency(>->rps);
335 }
336
__boost_freq_mhz_show(struct intel_gt * gt)337 static u32 __boost_freq_mhz_show(struct intel_gt *gt)
338 {
339 return intel_rps_get_boost_frequency(>->rps);
340 }
341
__boost_freq_mhz_store(struct intel_gt * gt,u32 val)342 static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
343 {
344 return intel_rps_set_boost_frequency(>->rps, val);
345 }
346
__RP0_freq_mhz_show(struct intel_gt * gt)347 static u32 __RP0_freq_mhz_show(struct intel_gt *gt)
348 {
349 return intel_rps_get_rp0_frequency(>->rps);
350 }
351
__RPn_freq_mhz_show(struct intel_gt * gt)352 static u32 __RPn_freq_mhz_show(struct intel_gt *gt)
353 {
354 return intel_rps_get_rpn_frequency(>->rps);
355 }
356
__RP1_freq_mhz_show(struct intel_gt * gt)357 static u32 __RP1_freq_mhz_show(struct intel_gt *gt)
358 {
359 return intel_rps_get_rp1_frequency(>->rps);
360 }
361
__max_freq_mhz_show(struct intel_gt * gt)362 static u32 __max_freq_mhz_show(struct intel_gt *gt)
363 {
364 return intel_rps_get_max_frequency(>->rps);
365 }
366
__set_max_freq(struct intel_gt * gt,u32 val)367 static int __set_max_freq(struct intel_gt *gt, u32 val)
368 {
369 return intel_rps_set_max_frequency(>->rps, val);
370 }
371
__min_freq_mhz_show(struct intel_gt * gt)372 static u32 __min_freq_mhz_show(struct intel_gt *gt)
373 {
374 return intel_rps_get_min_frequency(>->rps);
375 }
376
__set_min_freq(struct intel_gt * gt,u32 val)377 static int __set_min_freq(struct intel_gt *gt, u32 val)
378 {
379 return intel_rps_set_min_frequency(>->rps, val);
380 }
381
__vlv_rpe_freq_mhz_show(struct intel_gt * gt)382 static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
383 {
384 struct intel_rps *rps = >->rps;
385
386 return intel_gpu_freq(rps, rps->efficient_freq);
387 }
388
389 INTEL_GT_SYSFS_SHOW_MAX(act_freq_mhz);
390 INTEL_GT_SYSFS_SHOW_MAX(boost_freq_mhz);
391 INTEL_GT_SYSFS_SHOW_MAX(cur_freq_mhz);
392 INTEL_GT_SYSFS_SHOW_MAX(RP0_freq_mhz);
393 INTEL_GT_SYSFS_SHOW_MAX(RP1_freq_mhz);
394 INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);
395 INTEL_GT_SYSFS_SHOW_MAX(max_freq_mhz);
396 INTEL_GT_SYSFS_SHOW_MIN(min_freq_mhz);
397 INTEL_GT_SYSFS_SHOW_MAX(vlv_rpe_freq_mhz);
398 INTEL_GT_SYSFS_STORE(boost_freq_mhz, __boost_freq_mhz_store);
399 INTEL_GT_SYSFS_STORE(max_freq_mhz, __set_max_freq);
400 INTEL_GT_SYSFS_STORE(min_freq_mhz, __set_min_freq);
401
402 #define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, _store_dev) \
403 static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, \
404 _show_dev, _store_dev); \
405 static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, _mode, \
406 _show, _store)
407
408 #define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
409 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
410 _name##_dev_show, NULL)
411 #define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
412 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
413 _name##_dev_show, _name##_dev_store)
414
415 /* The below macros generate static structures */
416 INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
417 INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
418 INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
419 INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
420 INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
421 INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
422 INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
423 INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
424 INTEL_GT_RPS_SYSFS_ATTR_RO(vlv_rpe_freq_mhz);
425
426 #define GEN6_ATTR(p, s) { \
427 &p##attr_##s##_act_freq_mhz.attr, \
428 &p##attr_##s##_cur_freq_mhz.attr, \
429 &p##attr_##s##_boost_freq_mhz.attr, \
430 &p##attr_##s##_max_freq_mhz.attr, \
431 &p##attr_##s##_min_freq_mhz.attr, \
432 &p##attr_##s##_RP0_freq_mhz.attr, \
433 &p##attr_##s##_RP1_freq_mhz.attr, \
434 &p##attr_##s##_RPn_freq_mhz.attr, \
435 NULL, \
436 }
437
438 #define GEN6_RPS_ATTR GEN6_ATTR(, rps)
439 #define GEN6_GT_ATTR GEN6_ATTR(dev_, gt)
440
441 static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
442 static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
443
punit_req_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)444 static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
445 struct kobj_attribute *attr,
446 char *buff)
447 {
448 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
449 u32 preq = intel_rps_read_punit_req_frequency(>->rps);
450
451 return sysfs_emit(buff, "%u\n", preq);
452 }
453
454 struct intel_gt_bool_throttle_attr {
455 struct attribute attr;
456 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
457 char *buf);
458 i915_reg_t (*reg32)(struct intel_gt *gt);
459 u32 mask;
460 };
461
throttle_reason_bool_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)462 static ssize_t throttle_reason_bool_show(struct kobject *kobj,
463 struct kobj_attribute *attr,
464 char *buff)
465 {
466 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
467 struct intel_gt_bool_throttle_attr *t_attr =
468 (struct intel_gt_bool_throttle_attr *) attr;
469 bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
470
471 return sysfs_emit(buff, "%u\n", val);
472 }
473
474 #define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
475 struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
476 .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
477 .show = throttle_reason_bool_show, \
478 .reg32 = intel_gt_perf_limit_reasons_reg, \
479 .mask = mask__, \
480 }
481
482 INTEL_GT_ATTR_RO(punit_req_freq_mhz);
483 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
484 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
485 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
486 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
487 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
488 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
489 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
490 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
491 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
492
493 static const struct attribute *throttle_reason_attrs[] = {
494 &attr_throttle_reason_status.attr,
495 &attr_throttle_reason_pl1.attr,
496 &attr_throttle_reason_pl2.attr,
497 &attr_throttle_reason_pl4.attr,
498 &attr_throttle_reason_thermal.attr,
499 &attr_throttle_reason_prochot.attr,
500 &attr_throttle_reason_ratl.attr,
501 &attr_throttle_reason_vr_thermalert.attr,
502 &attr_throttle_reason_vr_tdc.attr,
503 NULL
504 };
505
506 /*
507 * Scaling for multipliers (aka frequency factors).
508 * The format of the value in the register is u8.8.
509 *
510 * The presentation to userspace is inspired by the perf event framework.
511 * See:
512 * Documentation/ABI/testing/sysfs-bus-event_source-devices-events
513 * for description of:
514 * /sys/bus/event_source/devices/<pmu>/events/<event>.scale
515 *
516 * Summary: Expose two sysfs files for each multiplier.
517 *
518 * 1. File <attr> contains a raw hardware value.
519 * 2. File <attr>.scale contains the multiplicative scale factor to be
520 * used by userspace to compute the actual value.
521 *
522 * So userspace knows that to get the frequency_factor it multiplies the
523 * provided value by the specified scale factor and vice-versa.
524 *
525 * That way there is no precision loss in the kernel interface and API
526 * is future proof should one day the hardware register change to u16.u16,
527 * on some platform. (Or any other fixed point representation.)
528 *
529 * Example:
530 * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
531 * is comprised of:
532 * - an integer part of 2
533 * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
534 * File <attr>.scale contains a string representation of floating point
535 * value 0.00390625 (which is (1 / 256)).
536 * Userspace computes the actual value:
537 * 0x0280 * 0.00390625 -> 2.5
538 * or converts an actual value to the value to be written into <attr>:
539 * 2.5 / 0.00390625 -> 0x0280
540 */
541
542 #define U8_8_VAL_MASK 0xffff
543 #define U8_8_SCALE_TO_VALUE "0.00390625"
544
freq_factor_scale_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)545 static ssize_t freq_factor_scale_show(struct kobject *kobj,
546 struct kobj_attribute *attr,
547 char *buff)
548 {
549 return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
550 }
551
media_ratio_mode_to_factor(u32 mode)552 static u32 media_ratio_mode_to_factor(u32 mode)
553 {
554 /* 0 -> 0, 1 -> 256, 2 -> 128 */
555 return !mode ? mode : 256 / mode;
556 }
557
media_freq_factor_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)558 static ssize_t media_freq_factor_show(struct kobject *kobj,
559 struct kobj_attribute *attr,
560 char *buff)
561 {
562 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
563 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
564 intel_wakeref_t wakeref;
565 u32 mode;
566
567 /*
568 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
569 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
570 */
571 if (IS_XEHPSDV(gt->i915) &&
572 slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
573 /*
574 * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
575 * the media_ratio_mode, just return the cached media ratio
576 */
577 mode = slpc->media_ratio_mode;
578 } else {
579 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
580 mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
581 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
582 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
583 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
584 }
585
586 return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
587 }
588
media_freq_factor_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buff,size_t count)589 static ssize_t media_freq_factor_store(struct kobject *kobj,
590 struct kobj_attribute *attr,
591 const char *buff, size_t count)
592 {
593 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
594 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
595 u32 factor, mode;
596 int err;
597
598 err = kstrtou32(buff, 0, &factor);
599 if (err)
600 return err;
601
602 for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
603 mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
604 if (factor == media_ratio_mode_to_factor(mode))
605 break;
606
607 if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
608 return -EINVAL;
609
610 err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
611 if (!err) {
612 slpc->media_ratio_mode = mode;
613 DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
614 }
615 return err ?: count;
616 }
617
media_RP0_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)618 static ssize_t media_RP0_freq_mhz_show(struct kobject *kobj,
619 struct kobj_attribute *attr,
620 char *buff)
621 {
622 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
623 u32 val;
624 int err;
625
626 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
627 PCODE_MBOX_FC_SC_READ_FUSED_P0,
628 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
629
630 if (err)
631 return err;
632
633 /* Fused media RP0 read from pcode is in units of 50 MHz */
634 val *= GT_FREQUENCY_MULTIPLIER;
635
636 return sysfs_emit(buff, "%u\n", val);
637 }
638
media_RPn_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)639 static ssize_t media_RPn_freq_mhz_show(struct kobject *kobj,
640 struct kobj_attribute *attr,
641 char *buff)
642 {
643 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
644 u32 val;
645 int err;
646
647 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
648 PCODE_MBOX_FC_SC_READ_FUSED_PN,
649 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
650
651 if (err)
652 return err;
653
654 /* Fused media RPn read from pcode is in units of 50 MHz */
655 val *= GT_FREQUENCY_MULTIPLIER;
656
657 return sysfs_emit(buff, "%u\n", val);
658 }
659
660 INTEL_GT_ATTR_RW(media_freq_factor);
661 static struct kobj_attribute attr_media_freq_factor_scale =
662 __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
663 INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
664 INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
665
666 static const struct attribute *media_perf_power_attrs[] = {
667 &attr_media_freq_factor.attr,
668 &attr_media_freq_factor_scale.attr,
669 &attr_media_RP0_freq_mhz.attr,
670 &attr_media_RPn_freq_mhz.attr,
671 NULL
672 };
673
674 static ssize_t
default_min_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)675 default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
676 {
677 struct intel_gt *gt = kobj_to_gt(kobj->parent);
678
679 return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
680 }
681
682 static struct kobj_attribute default_min_freq_mhz =
683 __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
684
685 static ssize_t
default_max_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)686 default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
687 {
688 struct intel_gt *gt = kobj_to_gt(kobj->parent);
689
690 return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
691 }
692
693 static struct kobj_attribute default_max_freq_mhz =
694 __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
695
696 static const struct attribute * const rps_defaults_attrs[] = {
697 &default_min_freq_mhz.attr,
698 &default_max_freq_mhz.attr,
699 NULL
700 };
701
intel_sysfs_rps_init(struct intel_gt * gt,struct kobject * kobj)702 static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
703 {
704 const struct attribute * const *attrs;
705 struct attribute *vlv_attr;
706 int ret;
707
708 if (GRAPHICS_VER(gt->i915) < 6)
709 return 0;
710
711 if (is_object_gt(kobj)) {
712 attrs = gen6_rps_attrs;
713 vlv_attr = &attr_rps_vlv_rpe_freq_mhz.attr;
714 } else {
715 attrs = gen6_gt_attrs;
716 vlv_attr = &dev_attr_gt_vlv_rpe_freq_mhz.attr;
717 }
718
719 ret = sysfs_create_files(kobj, attrs);
720 if (ret)
721 return ret;
722
723 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
724 ret = sysfs_create_file(kobj, vlv_attr);
725
726 return ret;
727 }
728
intel_gt_sysfs_pm_init(struct intel_gt * gt,struct kobject * kobj)729 void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
730 {
731 int ret;
732
733 intel_sysfs_rc6_init(gt, kobj);
734
735 ret = intel_sysfs_rps_init(gt, kobj);
736 if (ret)
737 gt_warn(gt, "failed to create RPS sysfs files (%pe)", ERR_PTR(ret));
738
739 /* end of the legacy interfaces */
740 if (!is_object_gt(kobj))
741 return;
742
743 ret = sysfs_create_file(kobj, &attr_punit_req_freq_mhz.attr);
744 if (ret)
745 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
746
747 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
748 ret = sysfs_create_files(kobj, throttle_reason_attrs);
749 if (ret)
750 gt_warn(gt, "failed to create throttle sysfs files (%pe)", ERR_PTR(ret));
751 }
752
753 if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(>->uc)) {
754 ret = sysfs_create_files(kobj, media_perf_power_attrs);
755 if (ret)
756 gt_warn(gt, "failed to create media_perf_power_attrs sysfs (%pe)\n",
757 ERR_PTR(ret));
758 }
759
760 ret = sysfs_create_files(gt->sysfs_defaults, rps_defaults_attrs);
761 if (ret)
762 gt_warn(gt, "failed to add rps defaults (%pe)\n", ERR_PTR(ret));
763 }
764