1 /*
2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <common/debug.h>
9 #include <common/runtime_svc.h>
10 #include <lib/mmio.h>
11 #include <tools_share/uuid.h>
12
13 #include "socfpga_fcs.h"
14 #include "socfpga_mailbox.h"
15 #include "socfpga_reset_manager.h"
16 #include "socfpga_sip_svc.h"
17
18
19 /* Total buffer the driver can hold */
20 #define FPGA_CONFIG_BUFFER_SIZE 4
21
22 static config_type request_type = NO_REQUEST;
23 static int current_block, current_buffer;
24 static int read_block, max_blocks;
25 static uint32_t send_id, rcv_id;
26 static uint32_t bytes_per_block, blocks_submitted;
27 static bool bridge_disable;
28
29 /* RSU static variables */
30 static uint32_t rsu_dcmf_ver[4] = {0};
31 static uint16_t rsu_dcmf_stat[4] = {0};
32 static uint32_t rsu_max_retry;
33
34 /* SiP Service UUID */
35 DEFINE_SVC_UUID2(intl_svc_uid,
36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
38
socfpga_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)39 static uint64_t socfpga_sip_handler(uint32_t smc_fid,
40 uint64_t x1,
41 uint64_t x2,
42 uint64_t x3,
43 uint64_t x4,
44 void *cookie,
45 void *handle,
46 uint64_t flags)
47 {
48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
49 SMC_RET1(handle, SMC_UNK);
50 }
51
52 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
53
intel_fpga_sdm_write_buffer(struct fpga_config_info * buffer)54 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
55 {
56 uint32_t args[3];
57
58 while (max_blocks > 0 && buffer->size > buffer->size_written) {
59 args[0] = (1<<8);
60 args[1] = buffer->addr + buffer->size_written;
61 if (buffer->size - buffer->size_written <= bytes_per_block) {
62 args[2] = buffer->size - buffer->size_written;
63 current_buffer++;
64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
65 } else {
66 args[2] = bytes_per_block;
67 }
68
69 buffer->size_written += args[2];
70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
71 3U, CMD_INDIRECT);
72
73 buffer->subblocks_sent++;
74 max_blocks--;
75 }
76
77 return !max_blocks;
78 }
79
intel_fpga_sdm_write_all(void)80 static int intel_fpga_sdm_write_all(void)
81 {
82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
83 if (intel_fpga_sdm_write_buffer(
84 &fpga_config_buffers[current_buffer])) {
85 break;
86 }
87 }
88 return 0;
89 }
90
intel_mailbox_fpga_config_isdone(void)91 static uint32_t intel_mailbox_fpga_config_isdone(void)
92 {
93 uint32_t ret;
94
95 switch (request_type) {
96 case RECONFIGURATION:
97 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
98 true);
99 break;
100 case BITSTREAM_AUTH:
101 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
102 false);
103 break;
104 default:
105 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
106 false);
107 break;
108 }
109
110 if (ret != 0U) {
111 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
112 return INTEL_SIP_SMC_STATUS_BUSY;
113 } else {
114 request_type = NO_REQUEST;
115 return INTEL_SIP_SMC_STATUS_ERROR;
116 }
117 }
118
119 if (bridge_disable != 0U) {
120 socfpga_bridges_enable(~0); /* Enable bridge */
121 bridge_disable = false;
122 }
123 request_type = NO_REQUEST;
124
125 return INTEL_SIP_SMC_STATUS_OK;
126 }
127
mark_last_buffer_xfer_completed(uint32_t * buffer_addr_completed)128 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
129 {
130 int i;
131
132 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
133 if (fpga_config_buffers[i].block_number == current_block) {
134 fpga_config_buffers[i].subblocks_sent--;
135 if (fpga_config_buffers[i].subblocks_sent == 0
136 && fpga_config_buffers[i].size <=
137 fpga_config_buffers[i].size_written) {
138 fpga_config_buffers[i].write_requested = 0;
139 current_block++;
140 *buffer_addr_completed =
141 fpga_config_buffers[i].addr;
142 return 0;
143 }
144 }
145 }
146
147 return -1;
148 }
149
intel_fpga_config_completed_write(uint32_t * completed_addr,uint32_t * count,uint32_t * job_id)150 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
151 uint32_t *count, uint32_t *job_id)
152 {
153 uint32_t resp[5];
154 unsigned int resp_len = ARRAY_SIZE(resp);
155 int status = INTEL_SIP_SMC_STATUS_OK;
156 int all_completed = 1;
157 *count = 0;
158
159 while (*count < 3) {
160
161 status = mailbox_read_response(job_id,
162 resp, &resp_len);
163
164 if (status < 0) {
165 break;
166 }
167
168 max_blocks++;
169
170 if (mark_last_buffer_xfer_completed(
171 &completed_addr[*count]) == 0) {
172 *count = *count + 1;
173 } else {
174 break;
175 }
176 }
177
178 if (*count <= 0) {
179 if (status != MBOX_NO_RESPONSE &&
180 status != MBOX_TIMEOUT && resp_len != 0) {
181 mailbox_clear_response();
182 request_type = NO_REQUEST;
183 return INTEL_SIP_SMC_STATUS_ERROR;
184 }
185
186 *count = 0;
187 }
188
189 intel_fpga_sdm_write_all();
190
191 if (*count > 0) {
192 status = INTEL_SIP_SMC_STATUS_OK;
193 } else if (*count == 0) {
194 status = INTEL_SIP_SMC_STATUS_BUSY;
195 }
196
197 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
198 if (fpga_config_buffers[i].write_requested != 0) {
199 all_completed = 0;
200 break;
201 }
202 }
203
204 if (all_completed == 1) {
205 return INTEL_SIP_SMC_STATUS_OK;
206 }
207
208 return status;
209 }
210
intel_fpga_config_start(uint32_t flag)211 static int intel_fpga_config_start(uint32_t flag)
212 {
213 uint32_t argument = 0x1;
214 uint32_t response[3];
215 int status = 0;
216 unsigned int size = 0;
217 unsigned int resp_len = ARRAY_SIZE(response);
218
219 request_type = RECONFIGURATION;
220
221 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
222 bridge_disable = true;
223 }
224
225 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
226 size = 1;
227 bridge_disable = false;
228 request_type = BITSTREAM_AUTH;
229 }
230
231 mailbox_clear_response();
232
233 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
234 CMD_CASUAL, NULL, NULL);
235
236 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
237 CMD_CASUAL, response, &resp_len);
238
239 if (status < 0) {
240 bridge_disable = false;
241 request_type = NO_REQUEST;
242 return INTEL_SIP_SMC_STATUS_ERROR;
243 }
244
245 max_blocks = response[0];
246 bytes_per_block = response[1];
247
248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
249 fpga_config_buffers[i].size = 0;
250 fpga_config_buffers[i].size_written = 0;
251 fpga_config_buffers[i].addr = 0;
252 fpga_config_buffers[i].write_requested = 0;
253 fpga_config_buffers[i].block_number = 0;
254 fpga_config_buffers[i].subblocks_sent = 0;
255 }
256
257 blocks_submitted = 0;
258 current_block = 0;
259 read_block = 0;
260 current_buffer = 0;
261
262 /* Disable bridge on full reconfiguration */
263 if (bridge_disable) {
264 socfpga_bridges_disable(~0);
265 }
266
267 return INTEL_SIP_SMC_STATUS_OK;
268 }
269
is_fpga_config_buffer_full(void)270 static bool is_fpga_config_buffer_full(void)
271 {
272 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
273 if (!fpga_config_buffers[i].write_requested) {
274 return false;
275 }
276 }
277 return true;
278 }
279
is_address_in_ddr_range(uint64_t addr,uint64_t size)280 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
281 {
282 if (!addr && !size) {
283 return true;
284 }
285 if (size > (UINT64_MAX - addr)) {
286 return false;
287 }
288 if (addr < BL31_LIMIT) {
289 return false;
290 }
291 if (addr + size > DRAM_BASE + DRAM_SIZE) {
292 return false;
293 }
294
295 return true;
296 }
297
intel_fpga_config_write(uint64_t mem,uint64_t size)298 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
299 {
300 int i;
301
302 intel_fpga_sdm_write_all();
303
304 if (!is_address_in_ddr_range(mem, size) ||
305 is_fpga_config_buffer_full()) {
306 return INTEL_SIP_SMC_STATUS_REJECTED;
307 }
308
309 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
310 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
311
312 if (!fpga_config_buffers[j].write_requested) {
313 fpga_config_buffers[j].addr = mem;
314 fpga_config_buffers[j].size = size;
315 fpga_config_buffers[j].size_written = 0;
316 fpga_config_buffers[j].write_requested = 1;
317 fpga_config_buffers[j].block_number =
318 blocks_submitted++;
319 fpga_config_buffers[j].subblocks_sent = 0;
320 break;
321 }
322 }
323
324 if (is_fpga_config_buffer_full()) {
325 return INTEL_SIP_SMC_STATUS_BUSY;
326 }
327
328 return INTEL_SIP_SMC_STATUS_OK;
329 }
330
is_out_of_sec_range(uint64_t reg_addr)331 static int is_out_of_sec_range(uint64_t reg_addr)
332 {
333 #if DEBUG
334 return 0;
335 #endif
336
337 switch (reg_addr) {
338 case(0xF8011100): /* ECCCTRL1 */
339 case(0xF8011104): /* ECCCTRL2 */
340 case(0xF8011110): /* ERRINTEN */
341 case(0xF8011114): /* ERRINTENS */
342 case(0xF8011118): /* ERRINTENR */
343 case(0xF801111C): /* INTMODE */
344 case(0xF8011120): /* INTSTAT */
345 case(0xF8011124): /* DIAGINTTEST */
346 case(0xF801112C): /* DERRADDRA */
347 case(0xFFD12028): /* SDMMCGRP_CTRL */
348 case(0xFFD12044): /* EMAC0 */
349 case(0xFFD12048): /* EMAC1 */
350 case(0xFFD1204C): /* EMAC2 */
351 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
352 case(0xFFD12094): /* ECC_INT_MASK_SET */
353 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
354 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
355 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
356 case(0xFFD120C0): /* NOC_TIMEOUT */
357 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
358 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
359 case(0xFFD120D0): /* NOC_IDLEACK */
360 case(0xFFD120D4): /* NOC_IDLESTATUS */
361 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
362 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
363 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
364 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
365 return 0;
366
367 default:
368 break;
369 }
370
371 return -1;
372 }
373
374 /* Secure register access */
intel_secure_reg_read(uint64_t reg_addr,uint32_t * retval)375 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
376 {
377 if (is_out_of_sec_range(reg_addr)) {
378 return INTEL_SIP_SMC_STATUS_ERROR;
379 }
380
381 *retval = mmio_read_32(reg_addr);
382
383 return INTEL_SIP_SMC_STATUS_OK;
384 }
385
intel_secure_reg_write(uint64_t reg_addr,uint32_t val,uint32_t * retval)386 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
387 uint32_t *retval)
388 {
389 if (is_out_of_sec_range(reg_addr)) {
390 return INTEL_SIP_SMC_STATUS_ERROR;
391 }
392
393 mmio_write_32(reg_addr, val);
394
395 return intel_secure_reg_read(reg_addr, retval);
396 }
397
intel_secure_reg_update(uint64_t reg_addr,uint32_t mask,uint32_t val,uint32_t * retval)398 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
399 uint32_t val, uint32_t *retval)
400 {
401 if (!intel_secure_reg_read(reg_addr, retval)) {
402 *retval &= ~mask;
403 *retval |= val & mask;
404 return intel_secure_reg_write(reg_addr, *retval, retval);
405 }
406
407 return INTEL_SIP_SMC_STATUS_ERROR;
408 }
409
410 /* Intel Remote System Update (RSU) services */
411 uint64_t intel_rsu_update_address;
412
intel_rsu_status(uint64_t * respbuf,unsigned int respbuf_sz)413 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
414 {
415 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
416 return INTEL_SIP_SMC_RSU_ERROR;
417 }
418
419 return INTEL_SIP_SMC_STATUS_OK;
420 }
421
intel_rsu_update(uint64_t update_address)422 static uint32_t intel_rsu_update(uint64_t update_address)
423 {
424 intel_rsu_update_address = update_address;
425 return INTEL_SIP_SMC_STATUS_OK;
426 }
427
intel_rsu_notify(uint32_t execution_stage)428 static uint32_t intel_rsu_notify(uint32_t execution_stage)
429 {
430 if (mailbox_hps_stage_notify(execution_stage) < 0) {
431 return INTEL_SIP_SMC_RSU_ERROR;
432 }
433
434 return INTEL_SIP_SMC_STATUS_OK;
435 }
436
intel_rsu_retry_counter(uint32_t * respbuf,uint32_t respbuf_sz,uint32_t * ret_stat)437 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
438 uint32_t *ret_stat)
439 {
440 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
441 return INTEL_SIP_SMC_RSU_ERROR;
442 }
443
444 *ret_stat = respbuf[8];
445 return INTEL_SIP_SMC_STATUS_OK;
446 }
447
intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,uint64_t dcmf_ver_3_2)448 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
449 uint64_t dcmf_ver_3_2)
450 {
451 rsu_dcmf_ver[0] = dcmf_ver_1_0;
452 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
453 rsu_dcmf_ver[2] = dcmf_ver_3_2;
454 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
455
456 return INTEL_SIP_SMC_STATUS_OK;
457 }
458
intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)459 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
460 {
461 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
462 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
463 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
464 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
465
466 return INTEL_SIP_SMC_STATUS_OK;
467 }
468
469 /* Intel HWMON services */
intel_hwmon_readtemp(uint32_t chan,uint32_t * retval)470 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
471 {
472 if (chan > TEMP_CHANNEL_MAX) {
473 return INTEL_SIP_SMC_STATUS_ERROR;
474 }
475
476 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
477 return INTEL_SIP_SMC_STATUS_ERROR;
478 }
479
480 return INTEL_SIP_SMC_STATUS_OK;
481 }
482
intel_hwmon_readvolt(uint32_t chan,uint32_t * retval)483 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
484 {
485 if (chan > VOLT_CHANNEL_MAX) {
486 return INTEL_SIP_SMC_STATUS_ERROR;
487 }
488
489 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
490 return INTEL_SIP_SMC_STATUS_ERROR;
491 }
492
493 return INTEL_SIP_SMC_STATUS_OK;
494 }
495
496 /* Mailbox services */
intel_smc_fw_version(uint32_t * fw_version)497 static uint32_t intel_smc_fw_version(uint32_t *fw_version)
498 {
499 int status;
500 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
501 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
502
503 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
504 CMD_CASUAL, resp_data, &resp_len);
505
506 if (status < 0) {
507 return INTEL_SIP_SMC_STATUS_ERROR;
508 }
509
510 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
511 return INTEL_SIP_SMC_STATUS_ERROR;
512 }
513
514 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
515
516 return INTEL_SIP_SMC_STATUS_OK;
517 }
518
intel_mbox_send_cmd(uint32_t cmd,uint32_t * args,unsigned int len,uint32_t urgent,uint64_t response,unsigned int resp_len,int * mbox_status,unsigned int * len_in_resp)519 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
520 unsigned int len, uint32_t urgent, uint64_t response,
521 unsigned int resp_len, int *mbox_status,
522 unsigned int *len_in_resp)
523 {
524 *len_in_resp = 0;
525 *mbox_status = GENERIC_RESPONSE_ERROR;
526
527 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
528 return INTEL_SIP_SMC_STATUS_REJECTED;
529 }
530
531 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
532 (uint32_t *) response, &resp_len);
533
534 if (status < 0) {
535 *mbox_status = -status;
536 return INTEL_SIP_SMC_STATUS_ERROR;
537 }
538
539 *mbox_status = 0;
540 *len_in_resp = resp_len;
541
542 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
543
544 return INTEL_SIP_SMC_STATUS_OK;
545 }
546
intel_smc_get_usercode(uint32_t * user_code)547 static int intel_smc_get_usercode(uint32_t *user_code)
548 {
549 int status;
550 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
551
552 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
553 0U, CMD_CASUAL, user_code, &resp_len);
554
555 if (status < 0) {
556 return INTEL_SIP_SMC_STATUS_ERROR;
557 }
558
559 return INTEL_SIP_SMC_STATUS_OK;
560 }
561
intel_smc_service_completed(uint64_t addr,uint32_t size,uint32_t mode,uint32_t * job_id,uint32_t * ret_size,uint32_t * mbox_error)562 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
563 uint32_t mode, uint32_t *job_id,
564 uint32_t *ret_size, uint32_t *mbox_error)
565 {
566 int status = 0;
567 uint32_t resp_len = size / MBOX_WORD_BYTE;
568
569 if (resp_len > MBOX_DATA_MAX_LEN) {
570 return INTEL_SIP_SMC_STATUS_REJECTED;
571 }
572
573 if (!is_address_in_ddr_range(addr, size)) {
574 return INTEL_SIP_SMC_STATUS_REJECTED;
575 }
576
577 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
578 status = mailbox_read_response_async(job_id,
579 NULL, (uint32_t *) addr, &resp_len, 0);
580 } else {
581 status = mailbox_read_response(job_id,
582 (uint32_t *) addr, &resp_len);
583
584 if (status == MBOX_NO_RESPONSE) {
585 status = MBOX_BUSY;
586 }
587 }
588
589 if (status == MBOX_NO_RESPONSE) {
590 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
591 }
592
593 if (status == MBOX_BUSY) {
594 return INTEL_SIP_SMC_STATUS_BUSY;
595 }
596
597 *ret_size = resp_len * MBOX_WORD_BYTE;
598 flush_dcache_range(addr, *ret_size);
599
600 if (status != MBOX_RET_OK) {
601 *mbox_error = -status;
602 return INTEL_SIP_SMC_STATUS_ERROR;
603 }
604
605 return INTEL_SIP_SMC_STATUS_OK;
606 }
607
608 /* Miscellaneous HPS services */
intel_hps_set_bridges(uint64_t enable,uint64_t mask)609 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
610 {
611 int status = 0;
612
613 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
614 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
615 status = socfpga_bridges_enable((uint32_t)mask);
616 } else {
617 status = socfpga_bridges_enable(~0);
618 }
619 } else {
620 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
621 status = socfpga_bridges_disable((uint32_t)mask);
622 } else {
623 status = socfpga_bridges_disable(~0);
624 }
625 }
626
627 if (status < 0) {
628 return INTEL_SIP_SMC_STATUS_ERROR;
629 }
630
631 return INTEL_SIP_SMC_STATUS_OK;
632 }
633
634 /*
635 * This function is responsible for handling all SiP calls from the NS world
636 */
637
sip_smc_handler_v1(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)638 uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
639 u_register_t x1,
640 u_register_t x2,
641 u_register_t x3,
642 u_register_t x4,
643 void *cookie,
644 void *handle,
645 u_register_t flags)
646 {
647 uint32_t retval = 0, completed_addr[3];
648 uint32_t retval2 = 0;
649 uint32_t mbox_error = 0;
650 uint64_t retval64, rsu_respbuf[9];
651 int status = INTEL_SIP_SMC_STATUS_OK;
652 int mbox_status;
653 unsigned int len_in_resp;
654 u_register_t x5, x6, x7;
655
656 switch (smc_fid) {
657 case SIP_SVC_UID:
658 /* Return UID to the caller */
659 SMC_UUID_RET(handle, intl_svc_uid);
660
661 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
662 status = intel_mailbox_fpga_config_isdone();
663 SMC_RET4(handle, status, 0, 0, 0);
664
665 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
666 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
667 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
668 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
669 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
670
671 case INTEL_SIP_SMC_FPGA_CONFIG_START:
672 status = intel_fpga_config_start(x1);
673 SMC_RET4(handle, status, 0, 0, 0);
674
675 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
676 status = intel_fpga_config_write(x1, x2);
677 SMC_RET4(handle, status, 0, 0, 0);
678
679 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
680 status = intel_fpga_config_completed_write(completed_addr,
681 &retval, &rcv_id);
682 switch (retval) {
683 case 1:
684 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
685 completed_addr[0], 0, 0);
686
687 case 2:
688 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
689 completed_addr[0],
690 completed_addr[1], 0);
691
692 case 3:
693 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
694 completed_addr[0],
695 completed_addr[1],
696 completed_addr[2]);
697
698 case 0:
699 SMC_RET4(handle, status, 0, 0, 0);
700
701 default:
702 mailbox_clear_response();
703 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
704 }
705
706 case INTEL_SIP_SMC_REG_READ:
707 status = intel_secure_reg_read(x1, &retval);
708 SMC_RET3(handle, status, retval, x1);
709
710 case INTEL_SIP_SMC_REG_WRITE:
711 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
712 SMC_RET3(handle, status, retval, x1);
713
714 case INTEL_SIP_SMC_REG_UPDATE:
715 status = intel_secure_reg_update(x1, (uint32_t)x2,
716 (uint32_t)x3, &retval);
717 SMC_RET3(handle, status, retval, x1);
718
719 case INTEL_SIP_SMC_RSU_STATUS:
720 status = intel_rsu_status(rsu_respbuf,
721 ARRAY_SIZE(rsu_respbuf));
722 if (status) {
723 SMC_RET1(handle, status);
724 } else {
725 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
726 rsu_respbuf[2], rsu_respbuf[3]);
727 }
728
729 case INTEL_SIP_SMC_RSU_UPDATE:
730 status = intel_rsu_update(x1);
731 SMC_RET1(handle, status);
732
733 case INTEL_SIP_SMC_RSU_NOTIFY:
734 status = intel_rsu_notify(x1);
735 SMC_RET1(handle, status);
736
737 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
738 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
739 ARRAY_SIZE(rsu_respbuf), &retval);
740 if (status) {
741 SMC_RET1(handle, status);
742 } else {
743 SMC_RET2(handle, status, retval);
744 }
745
746 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
747 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
748 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
749 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
750
751 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
752 status = intel_rsu_copy_dcmf_version(x1, x2);
753 SMC_RET1(handle, status);
754
755 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
756 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
757 ((uint64_t)rsu_dcmf_stat[3] << 48) |
758 ((uint64_t)rsu_dcmf_stat[2] << 32) |
759 ((uint64_t)rsu_dcmf_stat[1] << 16) |
760 rsu_dcmf_stat[0]);
761
762 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
763 status = intel_rsu_copy_dcmf_status(x1);
764 SMC_RET1(handle, status);
765
766 case INTEL_SIP_SMC_RSU_MAX_RETRY:
767 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
768
769 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
770 rsu_max_retry = x1;
771 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
772
773 case INTEL_SIP_SMC_ECC_DBE:
774 status = intel_ecc_dbe_notification(x1);
775 SMC_RET1(handle, status);
776
777 case INTEL_SIP_SMC_SERVICE_COMPLETED:
778 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
779 &len_in_resp, &mbox_error);
780 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
781
782 case INTEL_SIP_SMC_FIRMWARE_VERSION:
783 status = intel_smc_fw_version(&retval);
784 SMC_RET2(handle, status, retval);
785
786 case INTEL_SIP_SMC_MBOX_SEND_CMD:
787 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
788 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
789 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
790 &mbox_status, &len_in_resp);
791 SMC_RET3(handle, status, mbox_status, len_in_resp);
792
793 case INTEL_SIP_SMC_GET_USERCODE:
794 status = intel_smc_get_usercode(&retval);
795 SMC_RET2(handle, status, retval);
796
797 case INTEL_SIP_SMC_FCS_CRYPTION:
798 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
799
800 if (x1 == FCS_MODE_DECRYPT) {
801 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
802 } else if (x1 == FCS_MODE_ENCRYPT) {
803 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
804 } else {
805 status = INTEL_SIP_SMC_STATUS_REJECTED;
806 }
807
808 SMC_RET3(handle, status, x4, x5);
809
810 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
811 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
812 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
813 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
814
815 if (x3 == FCS_MODE_DECRYPT) {
816 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
817 (uint32_t *) &x7, &mbox_error);
818 } else if (x3 == FCS_MODE_ENCRYPT) {
819 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
820 (uint32_t *) &x7, &mbox_error);
821 } else {
822 status = INTEL_SIP_SMC_STATUS_REJECTED;
823 }
824
825 SMC_RET4(handle, status, mbox_error, x6, x7);
826
827 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
828 status = intel_fcs_random_number_gen(x1, &retval64,
829 &mbox_error);
830 SMC_RET4(handle, status, mbox_error, x1, retval64);
831
832 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
833 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
834 &send_id);
835 SMC_RET1(handle, status);
836
837 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
838 status = intel_fcs_send_cert(x1, x2, &send_id);
839 SMC_RET1(handle, status);
840
841 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
842 status = intel_fcs_get_provision_data(&send_id);
843 SMC_RET1(handle, status);
844
845 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
846 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
847 &mbox_error);
848 SMC_RET2(handle, status, mbox_error);
849
850 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
851 status = intel_hps_set_bridges(x1, x2);
852 SMC_RET1(handle, status);
853
854 case INTEL_SIP_SMC_HWMON_READTEMP:
855 status = intel_hwmon_readtemp(x1, &retval);
856 SMC_RET2(handle, status, retval);
857
858 case INTEL_SIP_SMC_HWMON_READVOLT:
859 status = intel_hwmon_readvolt(x1, &retval);
860 SMC_RET2(handle, status, retval);
861
862 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
863 status = intel_fcs_sigma_teardown(x1, &mbox_error);
864 SMC_RET2(handle, status, mbox_error);
865
866 case INTEL_SIP_SMC_FCS_CHIP_ID:
867 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
868 SMC_RET4(handle, status, mbox_error, retval, retval2);
869
870 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
871 status = intel_fcs_attestation_subkey(x1, x2, x3,
872 (uint32_t *) &x4, &mbox_error);
873 SMC_RET4(handle, status, mbox_error, x3, x4);
874
875 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
876 status = intel_fcs_get_measurement(x1, x2, x3,
877 (uint32_t *) &x4, &mbox_error);
878 SMC_RET4(handle, status, mbox_error, x3, x4);
879
880 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
881 status = intel_fcs_get_attestation_cert(x1, x2,
882 (uint32_t *) &x3, &mbox_error);
883 SMC_RET4(handle, status, mbox_error, x2, x3);
884
885 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
886 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
887 SMC_RET2(handle, status, mbox_error);
888
889 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
890 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
891 SMC_RET3(handle, status, mbox_error, retval);
892
893 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
894 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
895 SMC_RET2(handle, status, mbox_error);
896
897 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
898 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
899 SMC_RET1(handle, status);
900
901 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
902 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
903 (uint32_t *) &x4, &mbox_error);
904 SMC_RET4(handle, status, mbox_error, x3, x4);
905
906 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
907 status = intel_fcs_remove_crypto_service_key(x1, x2,
908 &mbox_error);
909 SMC_RET2(handle, status, mbox_error);
910
911 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
912 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
913 (uint32_t *) &x4, &mbox_error);
914 SMC_RET4(handle, status, mbox_error, x3, x4);
915
916 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
917 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
918 status = intel_fcs_get_digest_init(x1, x2, x3,
919 x4, x5, &mbox_error);
920 SMC_RET2(handle, status, mbox_error);
921
922 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
923 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
924 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
925 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
926 x4, x5, (uint32_t *) &x6, false,
927 &mbox_error);
928 SMC_RET4(handle, status, mbox_error, x5, x6);
929
930 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
931 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
932 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
933 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
934 x4, x5, (uint32_t *) &x6, true,
935 &mbox_error);
936 SMC_RET4(handle, status, mbox_error, x5, x6);
937
938 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
939 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
940 status = intel_fcs_mac_verify_init(x1, x2, x3,
941 x4, x5, &mbox_error);
942 SMC_RET2(handle, status, mbox_error);
943
944 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
945 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
946 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
947 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
948 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
949 x4, x5, (uint32_t *) &x6, x7,
950 false, &mbox_error);
951 SMC_RET4(handle, status, mbox_error, x5, x6);
952
953 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
954 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
955 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
956 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
957 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
958 x4, x5, (uint32_t *) &x6, x7,
959 true, &mbox_error);
960 SMC_RET4(handle, status, mbox_error, x5, x6);
961
962 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
964 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
965 x4, x5, &mbox_error);
966 SMC_RET2(handle, status, mbox_error);
967
968 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
971 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
972 x3, x4, x5, (uint32_t *) &x6, false,
973 &mbox_error);
974 SMC_RET4(handle, status, mbox_error, x5, x6);
975
976 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
977 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
978 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
979 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
980 x3, x4, x5, (uint32_t *) &x6, true,
981 &mbox_error);
982 SMC_RET4(handle, status, mbox_error, x5, x6);
983
984 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
985 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
986 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
987 x4, x5, &mbox_error);
988 SMC_RET2(handle, status, mbox_error);
989
990 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
993 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
994 x4, x5, (uint32_t *) &x6, &mbox_error);
995 SMC_RET4(handle, status, mbox_error, x5, x6);
996
997 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
998 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
999 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1000 x4, x5, &mbox_error);
1001 SMC_RET2(handle, status, mbox_error);
1002
1003 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1004 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1005 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1006 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1007 x4, x5, (uint32_t *) &x6, &mbox_error);
1008 SMC_RET4(handle, status, mbox_error, x5, x6);
1009
1010 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1012 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1013 x4, x5, &mbox_error);
1014 SMC_RET2(handle, status, mbox_error);
1015
1016 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1019 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1020 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1021 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1022 x7, false, &mbox_error);
1023 SMC_RET4(handle, status, mbox_error, x5, x6);
1024
1025 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1026 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1027 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1028 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1029 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1030 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1031 x7, true, &mbox_error);
1032 SMC_RET4(handle, status, mbox_error, x5, x6);
1033
1034 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1035 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1036 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1037 x4, x5, &mbox_error);
1038 SMC_RET2(handle, status, mbox_error);
1039
1040 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1041 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1042 (uint32_t *) &x4, &mbox_error);
1043 SMC_RET4(handle, status, mbox_error, x3, x4);
1044
1045 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1046 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1047 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1048 x4, x5, &mbox_error);
1049 SMC_RET2(handle, status, mbox_error);
1050
1051 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1052 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1053 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1054 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1055 x4, x5, (uint32_t *) &x6, &mbox_error);
1056 SMC_RET4(handle, status, mbox_error, x5, x6);
1057
1058 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1059 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1060 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1061 &mbox_error);
1062 SMC_RET2(handle, status, mbox_error);
1063
1064 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1065 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1066 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1067 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1068 x5, x6, false, &send_id);
1069 SMC_RET1(handle, status);
1070
1071 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1072 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1073 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1074 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1075 x5, x6, true, &send_id);
1076 SMC_RET1(handle, status);
1077
1078 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1079 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1080 &mbox_error);
1081 SMC_RET4(handle, status, mbox_error, x1, retval64);
1082
1083 case INTEL_SIP_SMC_SVC_VERSION:
1084 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1085 SIP_SVC_VERSION_MAJOR,
1086 SIP_SVC_VERSION_MINOR);
1087
1088 default:
1089 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1090 cookie, handle, flags);
1091 }
1092 }
1093
sip_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)1094 uintptr_t sip_smc_handler(uint32_t smc_fid,
1095 u_register_t x1,
1096 u_register_t x2,
1097 u_register_t x3,
1098 u_register_t x4,
1099 void *cookie,
1100 void *handle,
1101 u_register_t flags)
1102 {
1103 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1104
1105 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1106 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1107 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1108 cookie, handle, flags);
1109 } else {
1110 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1111 cookie, handle, flags);
1112 }
1113 }
1114
1115 DECLARE_RT_SVC(
1116 socfpga_sip_svc,
1117 OEN_SIP_START,
1118 OEN_SIP_END,
1119 SMC_TYPE_FAST,
1120 NULL,
1121 sip_smc_handler
1122 );
1123
1124 DECLARE_RT_SVC(
1125 socfpga_sip_svc_std,
1126 OEN_SIP_START,
1127 OEN_SIP_END,
1128 SMC_TYPE_YIELD,
1129 NULL,
1130 sip_smc_handler
1131 );
1132