1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30 #include <acpi/button.h>
31 #include <linux/acpi.h>
32 #include <linux/dmi.h>
33 #include <linux/i2c.h>
34 #include <linux/slab.h>
35 #include <linux/vga_switcheroo.h>
36
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_edid.h>
40
41 #include "i915_drv.h"
42 #include "i915_reg.h"
43 #include "intel_atomic.h"
44 #include "intel_backlight.h"
45 #include "intel_connector.h"
46 #include "intel_de.h"
47 #include "intel_display_types.h"
48 #include "intel_dpll.h"
49 #include "intel_fdi.h"
50 #include "intel_gmbus.h"
51 #include "intel_lvds.h"
52 #include "intel_panel.h"
53
54 /* Private structure for the integrated LVDS support */
55 struct intel_lvds_pps {
56 /* 100us units */
57 int t1_t2;
58 int t3;
59 int t4;
60 int t5;
61 int tx;
62
63 int divider;
64
65 int port;
66 bool powerdown_on_reset;
67 };
68
69 struct intel_lvds_encoder {
70 struct intel_encoder base;
71
72 bool is_dual_link;
73 i915_reg_t reg;
74 u32 a3_power;
75
76 struct intel_lvds_pps init_pps;
77 u32 init_lvds_val;
78
79 struct intel_connector *attached_connector;
80 };
81
to_lvds_encoder(struct intel_encoder * encoder)82 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
83 {
84 return container_of(encoder, struct intel_lvds_encoder, base);
85 }
86
intel_lvds_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t lvds_reg,enum pipe * pipe)87 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
88 i915_reg_t lvds_reg, enum pipe *pipe)
89 {
90 u32 val;
91
92 val = intel_de_read(dev_priv, lvds_reg);
93
94 /* asserts want to know the pipe even if the port is disabled */
95 if (HAS_PCH_CPT(dev_priv))
96 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
97 else
98 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
99
100 return val & LVDS_PORT_EN;
101 }
102
intel_lvds_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)103 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
104 enum pipe *pipe)
105 {
106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
107 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
108 intel_wakeref_t wakeref;
109 bool ret;
110
111 wakeref = intel_display_power_get_if_enabled(dev_priv,
112 encoder->power_domain);
113 if (!wakeref)
114 return false;
115
116 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
117
118 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
119
120 return ret;
121 }
122
intel_lvds_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)123 static void intel_lvds_get_config(struct intel_encoder *encoder,
124 struct intel_crtc_state *pipe_config)
125 {
126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
128 u32 tmp, flags = 0;
129
130 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
131
132 tmp = intel_de_read(dev_priv, lvds_encoder->reg);
133 if (tmp & LVDS_HSYNC_POLARITY)
134 flags |= DRM_MODE_FLAG_NHSYNC;
135 else
136 flags |= DRM_MODE_FLAG_PHSYNC;
137 if (tmp & LVDS_VSYNC_POLARITY)
138 flags |= DRM_MODE_FLAG_NVSYNC;
139 else
140 flags |= DRM_MODE_FLAG_PVSYNC;
141
142 pipe_config->hw.adjusted_mode.flags |= flags;
143
144 if (DISPLAY_VER(dev_priv) < 5)
145 pipe_config->gmch_pfit.lvds_border_bits =
146 tmp & LVDS_BORDER_ENABLE;
147
148 /* gen2/3 store dither state in pfit control, needs to match */
149 if (DISPLAY_VER(dev_priv) < 4) {
150 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
151
152 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
153 }
154
155 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
156 }
157
intel_lvds_pps_get_hw_state(struct drm_i915_private * dev_priv,struct intel_lvds_pps * pps)158 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
159 struct intel_lvds_pps *pps)
160 {
161 u32 val;
162
163 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
164
165 val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
167 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
168 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
169
170 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
171 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
172 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
173
174 val = intel_de_read(dev_priv, PP_DIVISOR(0));
175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
176 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
177 /*
178 * Remove the BSpec specified +1 (100ms) offset that accounts for a
179 * too short power-cycle delay due to the asynchronous programming of
180 * the register.
181 */
182 if (val)
183 val--;
184 /* Convert from 100ms to 100us units */
185 pps->t4 = val * 1000;
186
187 if (DISPLAY_VER(dev_priv) <= 4 &&
188 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
189 drm_dbg_kms(&dev_priv->drm,
190 "Panel power timings uninitialized, "
191 "setting defaults\n");
192 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
193 pps->t1_t2 = 40 * 10;
194 pps->t5 = 200 * 10;
195 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
196 pps->t3 = 35 * 10;
197 pps->tx = 200 * 10;
198 }
199
200 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
201 "divider %d port %d powerdown_on_reset %d\n",
202 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
203 pps->divider, pps->port, pps->powerdown_on_reset);
204 }
205
intel_lvds_pps_init_hw(struct drm_i915_private * dev_priv,struct intel_lvds_pps * pps)206 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
207 struct intel_lvds_pps *pps)
208 {
209 u32 val;
210
211 val = intel_de_read(dev_priv, PP_CONTROL(0));
212 drm_WARN_ON(&dev_priv->drm,
213 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
214 if (pps->powerdown_on_reset)
215 val |= PANEL_POWER_RESET;
216 intel_de_write(dev_priv, PP_CONTROL(0), val);
217
218 intel_de_write(dev_priv, PP_ON_DELAYS(0),
219 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
220
221 intel_de_write(dev_priv, PP_OFF_DELAYS(0),
222 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
223
224 intel_de_write(dev_priv, PP_DIVISOR(0),
225 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
226 }
227
intel_pre_enable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)228 static void intel_pre_enable_lvds(struct intel_atomic_state *state,
229 struct intel_encoder *encoder,
230 const struct intel_crtc_state *pipe_config,
231 const struct drm_connector_state *conn_state)
232 {
233 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
235 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
236 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
237 enum pipe pipe = crtc->pipe;
238 u32 temp;
239
240 if (HAS_PCH_SPLIT(dev_priv)) {
241 assert_fdi_rx_pll_disabled(dev_priv, pipe);
242 assert_shared_dpll_disabled(dev_priv,
243 pipe_config->shared_dpll);
244 } else {
245 assert_pll_disabled(dev_priv, pipe);
246 }
247
248 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
249
250 temp = lvds_encoder->init_lvds_val;
251 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
252
253 if (HAS_PCH_CPT(dev_priv)) {
254 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
255 temp |= LVDS_PIPE_SEL_CPT(pipe);
256 } else {
257 temp &= ~LVDS_PIPE_SEL_MASK;
258 temp |= LVDS_PIPE_SEL(pipe);
259 }
260
261 /* set the corresponsding LVDS_BORDER bit */
262 temp &= ~LVDS_BORDER_ENABLE;
263 temp |= pipe_config->gmch_pfit.lvds_border_bits;
264
265 /*
266 * Set the B0-B3 data pairs corresponding to whether we're going to
267 * set the DPLLs for dual-channel mode or not.
268 */
269 if (lvds_encoder->is_dual_link)
270 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
271 else
272 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
273
274 /*
275 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
276 * appropriately here, but we need to look more thoroughly into how
277 * panels behave in the two modes. For now, let's just maintain the
278 * value we got from the BIOS.
279 */
280 temp &= ~LVDS_A3_POWER_MASK;
281 temp |= lvds_encoder->a3_power;
282
283 /*
284 * Set the dithering flag on LVDS as needed, note that there is no
285 * special lvds dither control bit on pch-split platforms, dithering is
286 * only controlled through the PIPECONF reg.
287 */
288 if (DISPLAY_VER(dev_priv) == 4) {
289 /*
290 * Bspec wording suggests that LVDS port dithering only exists
291 * for 18bpp panels.
292 */
293 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
294 temp |= LVDS_ENABLE_DITHER;
295 else
296 temp &= ~LVDS_ENABLE_DITHER;
297 }
298 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
299 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
300 temp |= LVDS_HSYNC_POLARITY;
301 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
302 temp |= LVDS_VSYNC_POLARITY;
303
304 intel_de_write(dev_priv, lvds_encoder->reg, temp);
305 }
306
307 /*
308 * Sets the power state for the panel.
309 */
intel_enable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)310 static void intel_enable_lvds(struct intel_atomic_state *state,
311 struct intel_encoder *encoder,
312 const struct intel_crtc_state *pipe_config,
313 const struct drm_connector_state *conn_state)
314 {
315 struct drm_device *dev = encoder->base.dev;
316 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
317 struct drm_i915_private *dev_priv = to_i915(dev);
318
319 intel_de_write(dev_priv, lvds_encoder->reg,
320 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN);
321
322 intel_de_write(dev_priv, PP_CONTROL(0),
323 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON);
324 intel_de_posting_read(dev_priv, lvds_encoder->reg);
325
326 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
327 drm_err(&dev_priv->drm,
328 "timed out waiting for panel to power on\n");
329
330 intel_backlight_enable(pipe_config, conn_state);
331 }
332
intel_disable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)333 static void intel_disable_lvds(struct intel_atomic_state *state,
334 struct intel_encoder *encoder,
335 const struct intel_crtc_state *old_crtc_state,
336 const struct drm_connector_state *old_conn_state)
337 {
338 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
339 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
340
341 intel_de_write(dev_priv, PP_CONTROL(0),
342 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON);
343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
344 drm_err(&dev_priv->drm,
345 "timed out waiting for panel to power off\n");
346
347 intel_de_write(dev_priv, lvds_encoder->reg,
348 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN);
349 intel_de_posting_read(dev_priv, lvds_encoder->reg);
350 }
351
gmch_disable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)352 static void gmch_disable_lvds(struct intel_atomic_state *state,
353 struct intel_encoder *encoder,
354 const struct intel_crtc_state *old_crtc_state,
355 const struct drm_connector_state *old_conn_state)
356
357 {
358 intel_backlight_disable(old_conn_state);
359
360 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
361 }
362
pch_disable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)363 static void pch_disable_lvds(struct intel_atomic_state *state,
364 struct intel_encoder *encoder,
365 const struct intel_crtc_state *old_crtc_state,
366 const struct drm_connector_state *old_conn_state)
367 {
368 intel_backlight_disable(old_conn_state);
369 }
370
pch_post_disable_lvds(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)371 static void pch_post_disable_lvds(struct intel_atomic_state *state,
372 struct intel_encoder *encoder,
373 const struct intel_crtc_state *old_crtc_state,
374 const struct drm_connector_state *old_conn_state)
375 {
376 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
377 }
378
intel_lvds_shutdown(struct intel_encoder * encoder)379 static void intel_lvds_shutdown(struct intel_encoder *encoder)
380 {
381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
382
383 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
384 drm_err(&dev_priv->drm,
385 "timed out waiting for panel power cycle delay\n");
386 }
387
388 static enum drm_mode_status
intel_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)389 intel_lvds_mode_valid(struct drm_connector *connector,
390 struct drm_display_mode *mode)
391 {
392 struct intel_connector *intel_connector = to_intel_connector(connector);
393 const struct drm_display_mode *fixed_mode =
394 intel_panel_fixed_mode(intel_connector, mode);
395 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
396 enum drm_mode_status status;
397
398 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
399 return MODE_NO_DBLESCAN;
400
401 status = intel_panel_mode_valid(intel_connector, mode);
402 if (status != MODE_OK)
403 return status;
404
405 if (fixed_mode->clock > max_pixclk)
406 return MODE_CLOCK_HIGH;
407
408 return MODE_OK;
409 }
410
intel_lvds_compute_config(struct intel_encoder * intel_encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)411 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
412 struct intel_crtc_state *pipe_config,
413 struct drm_connector_state *conn_state)
414 {
415 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
416 struct intel_lvds_encoder *lvds_encoder =
417 to_lvds_encoder(intel_encoder);
418 struct intel_connector *intel_connector =
419 lvds_encoder->attached_connector;
420 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
421 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
422 unsigned int lvds_bpp;
423 int ret;
424
425 /* Should never happen!! */
426 if (DISPLAY_VER(dev_priv) < 4 && crtc->pipe == 0) {
427 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n");
428 return -EINVAL;
429 }
430
431 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
432 lvds_bpp = 8*3;
433 else
434 lvds_bpp = 6*3;
435
436 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
437 drm_dbg_kms(&dev_priv->drm,
438 "forcing display bpp (was %d) to LVDS (%d)\n",
439 pipe_config->pipe_bpp, lvds_bpp);
440 pipe_config->pipe_bpp = lvds_bpp;
441 }
442
443 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
444
445 /*
446 * We have timings from the BIOS for the panel, put them in
447 * to the adjusted mode. The CRTC will be set up for this mode,
448 * with the panel scaling set up to source from the H/VDisplay
449 * of the original mode.
450 */
451 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
452 if (ret)
453 return ret;
454
455 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
456 return -EINVAL;
457
458 if (HAS_PCH_SPLIT(dev_priv))
459 pipe_config->has_pch_encoder = true;
460
461 ret = intel_panel_fitting(pipe_config, conn_state);
462 if (ret)
463 return ret;
464
465 /*
466 * XXX: It would be nice to support lower refresh rates on the
467 * panels to reduce power consumption, and perhaps match the
468 * user's requested refresh rate.
469 */
470
471 return 0;
472 }
473
474 /*
475 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
476 */
intel_lvds_get_modes(struct drm_connector * connector)477 static int intel_lvds_get_modes(struct drm_connector *connector)
478 {
479 struct intel_connector *intel_connector = to_intel_connector(connector);
480 const struct drm_edid *fixed_edid = intel_connector->panel.fixed_edid;
481
482 /* Use panel fixed edid if we have one */
483 if (!IS_ERR_OR_NULL(fixed_edid)) {
484 drm_edid_connector_update(connector, fixed_edid);
485
486 return drm_edid_connector_add_modes(connector);
487 }
488
489 return intel_panel_get_modes(intel_connector);
490 }
491
492 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
493 .get_modes = intel_lvds_get_modes,
494 .mode_valid = intel_lvds_mode_valid,
495 .atomic_check = intel_digital_connector_atomic_check,
496 };
497
498 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
499 .detect = intel_panel_detect,
500 .fill_modes = drm_helper_probe_single_connector_modes,
501 .atomic_get_property = intel_digital_connector_atomic_get_property,
502 .atomic_set_property = intel_digital_connector_atomic_set_property,
503 .late_register = intel_connector_register,
504 .early_unregister = intel_connector_unregister,
505 .destroy = intel_connector_destroy,
506 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
507 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
508 };
509
510 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
511 .destroy = intel_encoder_destroy,
512 };
513
intel_no_lvds_dmi_callback(const struct dmi_system_id * id)514 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
515 {
516 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
517 return 1;
518 }
519
520 /* These systems claim to have LVDS, but really don't */
521 static const struct dmi_system_id intel_no_lvds[] = {
522 {
523 .callback = intel_no_lvds_dmi_callback,
524 .ident = "Apple Mac Mini (Core series)",
525 .matches = {
526 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
527 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
528 },
529 },
530 {
531 .callback = intel_no_lvds_dmi_callback,
532 .ident = "Apple Mac Mini (Core 2 series)",
533 .matches = {
534 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
535 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
536 },
537 },
538 {
539 .callback = intel_no_lvds_dmi_callback,
540 .ident = "MSI IM-945GSE-A",
541 .matches = {
542 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
543 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
544 },
545 },
546 {
547 .callback = intel_no_lvds_dmi_callback,
548 .ident = "Dell Studio Hybrid",
549 .matches = {
550 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
551 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
552 },
553 },
554 {
555 .callback = intel_no_lvds_dmi_callback,
556 .ident = "Dell OptiPlex FX170",
557 .matches = {
558 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
559 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
560 },
561 },
562 {
563 .callback = intel_no_lvds_dmi_callback,
564 .ident = "AOpen Mini PC",
565 .matches = {
566 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
567 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
568 },
569 },
570 {
571 .callback = intel_no_lvds_dmi_callback,
572 .ident = "AOpen Mini PC MP915",
573 .matches = {
574 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
575 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
576 },
577 },
578 {
579 .callback = intel_no_lvds_dmi_callback,
580 .ident = "AOpen i915GMm-HFS",
581 .matches = {
582 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
583 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
584 },
585 },
586 {
587 .callback = intel_no_lvds_dmi_callback,
588 .ident = "AOpen i45GMx-I",
589 .matches = {
590 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
591 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
592 },
593 },
594 {
595 .callback = intel_no_lvds_dmi_callback,
596 .ident = "Aopen i945GTt-VFA",
597 .matches = {
598 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
599 },
600 },
601 {
602 .callback = intel_no_lvds_dmi_callback,
603 .ident = "Clientron U800",
604 .matches = {
605 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
606 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
607 },
608 },
609 {
610 .callback = intel_no_lvds_dmi_callback,
611 .ident = "Clientron E830",
612 .matches = {
613 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
614 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
615 },
616 },
617 {
618 .callback = intel_no_lvds_dmi_callback,
619 .ident = "Asus EeeBox PC EB1007",
620 .matches = {
621 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
622 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
623 },
624 },
625 {
626 .callback = intel_no_lvds_dmi_callback,
627 .ident = "Asus AT5NM10T-I",
628 .matches = {
629 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
630 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
631 },
632 },
633 {
634 .callback = intel_no_lvds_dmi_callback,
635 .ident = "Hewlett-Packard HP t5740",
636 .matches = {
637 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
638 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
639 },
640 },
641 {
642 .callback = intel_no_lvds_dmi_callback,
643 .ident = "Hewlett-Packard t5745",
644 .matches = {
645 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
646 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
647 },
648 },
649 {
650 .callback = intel_no_lvds_dmi_callback,
651 .ident = "Hewlett-Packard st5747",
652 .matches = {
653 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
654 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
655 },
656 },
657 {
658 .callback = intel_no_lvds_dmi_callback,
659 .ident = "MSI Wind Box DC500",
660 .matches = {
661 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
662 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
663 },
664 },
665 {
666 .callback = intel_no_lvds_dmi_callback,
667 .ident = "Gigabyte GA-D525TUD",
668 .matches = {
669 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
670 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
671 },
672 },
673 {
674 .callback = intel_no_lvds_dmi_callback,
675 .ident = "Supermicro X7SPA-H",
676 .matches = {
677 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
678 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
679 },
680 },
681 {
682 .callback = intel_no_lvds_dmi_callback,
683 .ident = "Fujitsu Esprimo Q900",
684 .matches = {
685 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
686 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
687 },
688 },
689 {
690 .callback = intel_no_lvds_dmi_callback,
691 .ident = "Intel D410PT",
692 .matches = {
693 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
694 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
695 },
696 },
697 {
698 .callback = intel_no_lvds_dmi_callback,
699 .ident = "Intel D425KT",
700 .matches = {
701 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
702 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
703 },
704 },
705 {
706 .callback = intel_no_lvds_dmi_callback,
707 .ident = "Intel D510MO",
708 .matches = {
709 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
710 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
711 },
712 },
713 {
714 .callback = intel_no_lvds_dmi_callback,
715 .ident = "Intel D525MW",
716 .matches = {
717 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
718 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
719 },
720 },
721 {
722 .callback = intel_no_lvds_dmi_callback,
723 .ident = "Radiant P845",
724 .matches = {
725 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
726 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
727 },
728 },
729
730 { } /* terminating entry */
731 };
732
intel_dual_link_lvds_callback(const struct dmi_system_id * id)733 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
734 {
735 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
736 return 1;
737 }
738
739 static const struct dmi_system_id intel_dual_link_lvds[] = {
740 {
741 .callback = intel_dual_link_lvds_callback,
742 .ident = "Apple MacBook Pro 15\" (2010)",
743 .matches = {
744 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
745 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
746 },
747 },
748 {
749 .callback = intel_dual_link_lvds_callback,
750 .ident = "Apple MacBook Pro 15\" (2011)",
751 .matches = {
752 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
753 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
754 },
755 },
756 {
757 .callback = intel_dual_link_lvds_callback,
758 .ident = "Apple MacBook Pro 15\" (2012)",
759 .matches = {
760 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
761 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
762 },
763 },
764 { } /* terminating entry */
765 };
766
intel_get_lvds_encoder(struct drm_i915_private * dev_priv)767 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
768 {
769 struct intel_encoder *encoder;
770
771 for_each_intel_encoder(&dev_priv->drm, encoder) {
772 if (encoder->type == INTEL_OUTPUT_LVDS)
773 return encoder;
774 }
775
776 return NULL;
777 }
778
intel_is_dual_link_lvds(struct drm_i915_private * dev_priv)779 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
780 {
781 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
782
783 return encoder && to_lvds_encoder(encoder)->is_dual_link;
784 }
785
compute_is_dual_link_lvds(struct intel_lvds_encoder * lvds_encoder)786 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
787 {
788 struct drm_i915_private *dev_priv = to_i915(lvds_encoder->base.base.dev);
789 struct intel_connector *connector = lvds_encoder->attached_connector;
790 const struct drm_display_mode *fixed_mode =
791 intel_panel_preferred_fixed_mode(connector);
792 unsigned int val;
793
794 /* use the module option value if specified */
795 if (dev_priv->params.lvds_channel_mode > 0)
796 return dev_priv->params.lvds_channel_mode == 2;
797
798 /* single channel LVDS is limited to 112 MHz */
799 if (fixed_mode->clock > 112999)
800 return true;
801
802 if (dmi_check_system(intel_dual_link_lvds))
803 return true;
804
805 /*
806 * BIOS should set the proper LVDS register value at boot, but
807 * in reality, it doesn't set the value when the lid is closed;
808 * we need to check "the value to be set" in VBT when LVDS
809 * register is uninitialized.
810 */
811 val = intel_de_read(dev_priv, lvds_encoder->reg);
812 if (HAS_PCH_CPT(dev_priv))
813 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
814 else
815 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
816 if (val == 0)
817 val = connector->panel.vbt.bios_lvds_val;
818
819 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
820 }
821
intel_lvds_add_properties(struct drm_connector * connector)822 static void intel_lvds_add_properties(struct drm_connector *connector)
823 {
824 intel_attach_scaling_mode_property(connector);
825 }
826
827 /**
828 * intel_lvds_init - setup LVDS connectors on this device
829 * @dev_priv: i915 device
830 *
831 * Create the connector, register the LVDS DDC bus, and try to figure out what
832 * modes we can display on the LVDS panel (if present).
833 */
intel_lvds_init(struct drm_i915_private * dev_priv)834 void intel_lvds_init(struct drm_i915_private *dev_priv)
835 {
836 struct intel_lvds_encoder *lvds_encoder;
837 struct intel_encoder *intel_encoder;
838 struct intel_connector *intel_connector;
839 struct drm_connector *connector;
840 struct drm_encoder *encoder;
841 const struct drm_edid *drm_edid;
842 i915_reg_t lvds_reg;
843 u32 lvds;
844 u8 pin;
845
846 /* Skip init on machines we know falsely report LVDS */
847 if (dmi_check_system(intel_no_lvds)) {
848 drm_WARN(&dev_priv->drm, !dev_priv->display.vbt.int_lvds_support,
849 "Useless DMI match. Internal LVDS support disabled by VBT\n");
850 return;
851 }
852
853 if (!dev_priv->display.vbt.int_lvds_support) {
854 drm_dbg_kms(&dev_priv->drm,
855 "Internal LVDS support disabled by VBT\n");
856 return;
857 }
858
859 if (HAS_PCH_SPLIT(dev_priv))
860 lvds_reg = PCH_LVDS;
861 else
862 lvds_reg = LVDS;
863
864 lvds = intel_de_read(dev_priv, lvds_reg);
865
866 if (HAS_PCH_SPLIT(dev_priv)) {
867 if ((lvds & LVDS_DETECTED) == 0)
868 return;
869 }
870
871 pin = GMBUS_PIN_PANEL;
872 if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
873 if ((lvds & LVDS_PORT_EN) == 0) {
874 drm_dbg_kms(&dev_priv->drm,
875 "LVDS is not present in VBT\n");
876 return;
877 }
878 drm_dbg_kms(&dev_priv->drm,
879 "LVDS is not present in VBT, but enabled anyway\n");
880 }
881
882 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
883 if (!lvds_encoder)
884 return;
885
886 intel_connector = intel_connector_alloc();
887 if (!intel_connector) {
888 kfree(lvds_encoder);
889 return;
890 }
891
892 lvds_encoder->attached_connector = intel_connector;
893
894 intel_encoder = &lvds_encoder->base;
895 encoder = &intel_encoder->base;
896 connector = &intel_connector->base;
897 drm_connector_init(&dev_priv->drm, &intel_connector->base, &intel_lvds_connector_funcs,
898 DRM_MODE_CONNECTOR_LVDS);
899
900 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_lvds_enc_funcs,
901 DRM_MODE_ENCODER_LVDS, "LVDS");
902
903 intel_encoder->enable = intel_enable_lvds;
904 intel_encoder->pre_enable = intel_pre_enable_lvds;
905 intel_encoder->compute_config = intel_lvds_compute_config;
906 if (HAS_PCH_SPLIT(dev_priv)) {
907 intel_encoder->disable = pch_disable_lvds;
908 intel_encoder->post_disable = pch_post_disable_lvds;
909 } else {
910 intel_encoder->disable = gmch_disable_lvds;
911 }
912 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
913 intel_encoder->get_config = intel_lvds_get_config;
914 intel_encoder->update_pipe = intel_backlight_update;
915 intel_encoder->shutdown = intel_lvds_shutdown;
916 intel_connector->get_hw_state = intel_connector_get_hw_state;
917
918 intel_connector_attach_encoder(intel_connector, intel_encoder);
919
920 intel_encoder->type = INTEL_OUTPUT_LVDS;
921 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
922 intel_encoder->port = PORT_NONE;
923 intel_encoder->cloneable = 0;
924 if (DISPLAY_VER(dev_priv) < 4)
925 intel_encoder->pipe_mask = BIT(PIPE_B);
926 else
927 intel_encoder->pipe_mask = ~0;
928
929 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
930 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
931
932 lvds_encoder->reg = lvds_reg;
933
934 intel_lvds_add_properties(connector);
935
936 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
937 lvds_encoder->init_lvds_val = lvds;
938
939 /*
940 * LVDS discovery:
941 * 1) check for EDID on DDC
942 * 2) check for VBT data
943 * 3) check to see if LVDS is already on
944 * if none of the above, no panel
945 */
946
947 /*
948 * Attempt to get the fixed panel mode from DDC. Assume that the
949 * preferred mode is the right one.
950 */
951 mutex_lock(&dev_priv->drm.mode_config.mutex);
952 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) {
953 const struct edid *edid;
954
955 /* FIXME: Make drm_get_edid_switcheroo() return drm_edid */
956 edid = drm_get_edid_switcheroo(connector,
957 intel_gmbus_get_adapter(dev_priv, pin));
958 if (edid) {
959 drm_edid = drm_edid_alloc(edid, (edid->extensions + 1) * EDID_LENGTH);
960 kfree(edid);
961 } else {
962 drm_edid = NULL;
963 }
964 } else {
965 drm_edid = drm_edid_read_ddc(connector,
966 intel_gmbus_get_adapter(dev_priv, pin));
967 }
968 if (drm_edid) {
969 if (drm_edid_connector_update(connector, drm_edid) ||
970 !drm_edid_connector_add_modes(connector)) {
971 drm_edid_connector_update(connector, NULL);
972 drm_edid_free(drm_edid);
973 drm_edid = ERR_PTR(-EINVAL);
974 }
975 } else {
976 drm_edid = ERR_PTR(-ENOENT);
977 }
978 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL,
979 IS_ERR(drm_edid) ? NULL : drm_edid);
980
981 /* Try EDID first */
982 intel_panel_add_edid_fixed_modes(intel_connector, true);
983
984 /* Failed to get EDID, what about VBT? */
985 if (!intel_panel_preferred_fixed_mode(intel_connector))
986 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
987
988 /*
989 * If we didn't get a fixed mode from EDID or VBT, try checking
990 * if the panel is already turned on. If so, assume that
991 * whatever is currently programmed is the correct mode.
992 */
993 if (!intel_panel_preferred_fixed_mode(intel_connector))
994 intel_panel_add_encoder_fixed_mode(intel_connector, intel_encoder);
995
996 mutex_unlock(&dev_priv->drm.mode_config.mutex);
997
998 /* If we still don't have a mode after all that, give up. */
999 if (!intel_panel_preferred_fixed_mode(intel_connector))
1000 goto failed;
1001
1002 intel_panel_init(intel_connector, drm_edid);
1003
1004 intel_backlight_setup(intel_connector, INVALID_PIPE);
1005
1006 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1007 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n",
1008 lvds_encoder->is_dual_link ? "dual" : "single");
1009
1010 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1011
1012 return;
1013
1014 failed:
1015 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n");
1016 drm_connector_cleanup(connector);
1017 drm_encoder_cleanup(encoder);
1018 kfree(lvds_encoder);
1019 intel_connector_free(intel_connector);
1020 return;
1021 }
1022