1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/string_helpers.h>
26
27 #include <drm/drm_print.h>
28 #include <drm/i915_pciids.h>
29
30 #include "display/intel_cdclk.h"
31 #include "display/intel_de.h"
32 #include "display/intel_display.h"
33 #include "gt/intel_gt_regs.h"
34 #include "i915_drv.h"
35 #include "i915_reg.h"
36 #include "i915_utils.h"
37 #include "intel_device_info.h"
38
39 #define PLATFORM_NAME(x) [INTEL_##x] = #x
40 static const char * const platform_names[] = {
41 PLATFORM_NAME(I830),
42 PLATFORM_NAME(I845G),
43 PLATFORM_NAME(I85X),
44 PLATFORM_NAME(I865G),
45 PLATFORM_NAME(I915G),
46 PLATFORM_NAME(I915GM),
47 PLATFORM_NAME(I945G),
48 PLATFORM_NAME(I945GM),
49 PLATFORM_NAME(G33),
50 PLATFORM_NAME(PINEVIEW),
51 PLATFORM_NAME(I965G),
52 PLATFORM_NAME(I965GM),
53 PLATFORM_NAME(G45),
54 PLATFORM_NAME(GM45),
55 PLATFORM_NAME(IRONLAKE),
56 PLATFORM_NAME(SANDYBRIDGE),
57 PLATFORM_NAME(IVYBRIDGE),
58 PLATFORM_NAME(VALLEYVIEW),
59 PLATFORM_NAME(HASWELL),
60 PLATFORM_NAME(BROADWELL),
61 PLATFORM_NAME(CHERRYVIEW),
62 PLATFORM_NAME(SKYLAKE),
63 PLATFORM_NAME(BROXTON),
64 PLATFORM_NAME(KABYLAKE),
65 PLATFORM_NAME(GEMINILAKE),
66 PLATFORM_NAME(COFFEELAKE),
67 PLATFORM_NAME(COMETLAKE),
68 PLATFORM_NAME(ICELAKE),
69 PLATFORM_NAME(ELKHARTLAKE),
70 PLATFORM_NAME(JASPERLAKE),
71 PLATFORM_NAME(TIGERLAKE),
72 PLATFORM_NAME(ROCKETLAKE),
73 PLATFORM_NAME(DG1),
74 PLATFORM_NAME(ALDERLAKE_S),
75 PLATFORM_NAME(ALDERLAKE_P),
76 PLATFORM_NAME(XEHPSDV),
77 PLATFORM_NAME(DG2),
78 PLATFORM_NAME(PONTEVECCHIO),
79 PLATFORM_NAME(METEORLAKE),
80 };
81 #undef PLATFORM_NAME
82
intel_platform_name(enum intel_platform platform)83 const char *intel_platform_name(enum intel_platform platform)
84 {
85 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
86
87 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
88 platform_names[platform] == NULL))
89 return "<unknown>";
90
91 return platform_names[platform];
92 }
93
intel_device_info_print(const struct intel_device_info * info,const struct intel_runtime_info * runtime,struct drm_printer * p)94 void intel_device_info_print(const struct intel_device_info *info,
95 const struct intel_runtime_info *runtime,
96 struct drm_printer *p)
97 {
98 if (runtime->graphics.ip.rel)
99 drm_printf(p, "graphics version: %u.%02u\n",
100 runtime->graphics.ip.ver,
101 runtime->graphics.ip.rel);
102 else
103 drm_printf(p, "graphics version: %u\n",
104 runtime->graphics.ip.ver);
105
106 if (runtime->media.ip.rel)
107 drm_printf(p, "media version: %u.%02u\n",
108 runtime->media.ip.ver,
109 runtime->media.ip.rel);
110 else
111 drm_printf(p, "media version: %u\n",
112 runtime->media.ip.ver);
113
114 if (runtime->display.ip.rel)
115 drm_printf(p, "display version: %u.%02u\n",
116 runtime->display.ip.ver,
117 runtime->display.ip.rel);
118 else
119 drm_printf(p, "display version: %u\n",
120 runtime->display.ip.ver);
121
122 drm_printf(p, "gt: %d\n", info->gt);
123 drm_printf(p, "memory-regions: %x\n", runtime->memory_regions);
124 drm_printf(p, "page-sizes: %x\n", runtime->page_sizes);
125 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
126 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
127 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
128 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
129
130 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
131 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
132 #undef PRINT_FLAG
133
134 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
135
136 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name))
137 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
138 #undef PRINT_FLAG
139
140 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
141 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
142 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
143
144 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
145 }
146
147 #undef INTEL_VGA_DEVICE
148 #define INTEL_VGA_DEVICE(id, info) (id)
149
150 static const u16 subplatform_ult_ids[] = {
151 INTEL_HSW_ULT_GT1_IDS(0),
152 INTEL_HSW_ULT_GT2_IDS(0),
153 INTEL_HSW_ULT_GT3_IDS(0),
154 INTEL_BDW_ULT_GT1_IDS(0),
155 INTEL_BDW_ULT_GT2_IDS(0),
156 INTEL_BDW_ULT_GT3_IDS(0),
157 INTEL_BDW_ULT_RSVD_IDS(0),
158 INTEL_SKL_ULT_GT1_IDS(0),
159 INTEL_SKL_ULT_GT2_IDS(0),
160 INTEL_SKL_ULT_GT3_IDS(0),
161 INTEL_KBL_ULT_GT1_IDS(0),
162 INTEL_KBL_ULT_GT2_IDS(0),
163 INTEL_KBL_ULT_GT3_IDS(0),
164 INTEL_CFL_U_GT2_IDS(0),
165 INTEL_CFL_U_GT3_IDS(0),
166 INTEL_WHL_U_GT1_IDS(0),
167 INTEL_WHL_U_GT2_IDS(0),
168 INTEL_WHL_U_GT3_IDS(0),
169 INTEL_CML_U_GT1_IDS(0),
170 INTEL_CML_U_GT2_IDS(0),
171 };
172
173 static const u16 subplatform_ulx_ids[] = {
174 INTEL_HSW_ULX_GT1_IDS(0),
175 INTEL_HSW_ULX_GT2_IDS(0),
176 INTEL_BDW_ULX_GT1_IDS(0),
177 INTEL_BDW_ULX_GT2_IDS(0),
178 INTEL_BDW_ULX_GT3_IDS(0),
179 INTEL_BDW_ULX_RSVD_IDS(0),
180 INTEL_SKL_ULX_GT1_IDS(0),
181 INTEL_SKL_ULX_GT2_IDS(0),
182 INTEL_KBL_ULX_GT1_IDS(0),
183 INTEL_KBL_ULX_GT2_IDS(0),
184 INTEL_AML_KBL_GT2_IDS(0),
185 INTEL_AML_CFL_GT2_IDS(0),
186 };
187
188 static const u16 subplatform_portf_ids[] = {
189 INTEL_ICL_PORT_F_IDS(0),
190 };
191
192 static const u16 subplatform_uy_ids[] = {
193 INTEL_TGL_12_GT2_IDS(0),
194 };
195
196 static const u16 subplatform_n_ids[] = {
197 INTEL_ADLN_IDS(0),
198 };
199
200 static const u16 subplatform_rpl_ids[] = {
201 INTEL_RPLS_IDS(0),
202 INTEL_RPLP_IDS(0),
203 };
204
205 static const u16 subplatform_g10_ids[] = {
206 INTEL_DG2_G10_IDS(0),
207 INTEL_ATS_M150_IDS(0),
208 };
209
210 static const u16 subplatform_g11_ids[] = {
211 INTEL_DG2_G11_IDS(0),
212 INTEL_ATS_M75_IDS(0),
213 };
214
215 static const u16 subplatform_g12_ids[] = {
216 INTEL_DG2_G12_IDS(0),
217 };
218
219 static const u16 subplatform_m_ids[] = {
220 INTEL_MTL_M_IDS(0),
221 };
222
223 static const u16 subplatform_p_ids[] = {
224 INTEL_MTL_P_IDS(0),
225 };
226
find_devid(u16 id,const u16 * p,unsigned int num)227 static bool find_devid(u16 id, const u16 *p, unsigned int num)
228 {
229 for (; num; num--, p++) {
230 if (*p == id)
231 return true;
232 }
233
234 return false;
235 }
236
intel_device_info_subplatform_init(struct drm_i915_private * i915)237 static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
238 {
239 const struct intel_device_info *info = INTEL_INFO(i915);
240 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
241 const unsigned int pi = __platform_mask_index(rinfo, info->platform);
242 const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
243 u16 devid = INTEL_DEVID(i915);
244 u32 mask = 0;
245
246 /* Make sure IS_<platform> checks are working. */
247 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
248
249 /* Find and mark subplatform bits based on the PCI device id. */
250 if (find_devid(devid, subplatform_ult_ids,
251 ARRAY_SIZE(subplatform_ult_ids))) {
252 mask = BIT(INTEL_SUBPLATFORM_ULT);
253 } else if (find_devid(devid, subplatform_ulx_ids,
254 ARRAY_SIZE(subplatform_ulx_ids))) {
255 mask = BIT(INTEL_SUBPLATFORM_ULX);
256 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
257 /* ULX machines are also considered ULT. */
258 mask |= BIT(INTEL_SUBPLATFORM_ULT);
259 }
260 } else if (find_devid(devid, subplatform_portf_ids,
261 ARRAY_SIZE(subplatform_portf_ids))) {
262 mask = BIT(INTEL_SUBPLATFORM_PORTF);
263 } else if (find_devid(devid, subplatform_uy_ids,
264 ARRAY_SIZE(subplatform_uy_ids))) {
265 mask = BIT(INTEL_SUBPLATFORM_UY);
266 } else if (find_devid(devid, subplatform_n_ids,
267 ARRAY_SIZE(subplatform_n_ids))) {
268 mask = BIT(INTEL_SUBPLATFORM_N);
269 } else if (find_devid(devid, subplatform_rpl_ids,
270 ARRAY_SIZE(subplatform_rpl_ids))) {
271 mask = BIT(INTEL_SUBPLATFORM_RPL);
272 } else if (find_devid(devid, subplatform_g10_ids,
273 ARRAY_SIZE(subplatform_g10_ids))) {
274 mask = BIT(INTEL_SUBPLATFORM_G10);
275 } else if (find_devid(devid, subplatform_g11_ids,
276 ARRAY_SIZE(subplatform_g11_ids))) {
277 mask = BIT(INTEL_SUBPLATFORM_G11);
278 } else if (find_devid(devid, subplatform_g12_ids,
279 ARRAY_SIZE(subplatform_g12_ids))) {
280 mask = BIT(INTEL_SUBPLATFORM_G12);
281 } else if (find_devid(devid, subplatform_m_ids,
282 ARRAY_SIZE(subplatform_m_ids))) {
283 mask = BIT(INTEL_SUBPLATFORM_M);
284 } else if (find_devid(devid, subplatform_p_ids,
285 ARRAY_SIZE(subplatform_p_ids))) {
286 mask = BIT(INTEL_SUBPLATFORM_P);
287 }
288
289 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
290
291 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
292 }
293
ip_ver_read(struct drm_i915_private * i915,u32 offset,struct intel_ip_version * ip)294 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
295 {
296 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
297 void __iomem *addr;
298 u32 val;
299 u8 expected_ver = ip->ver;
300 u8 expected_rel = ip->rel;
301
302 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
303 if (drm_WARN_ON(&i915->drm, !addr))
304 return;
305
306 val = ioread32(addr);
307 pci_iounmap(pdev, addr);
308
309 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
310 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
311 ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
312
313 /* Sanity check against expected versions from device info */
314 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
315 drm_dbg(&i915->drm,
316 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
317 ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
318 }
319
320 /*
321 * Setup the graphics version for the current device. This must be done before
322 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
323 * function should be called very early in the driver initialization sequence.
324 *
325 * Regular MMIO access is not yet setup at the point this function is called so
326 * we peek at the appropriate MMIO offset directly. The GMD_ID register is
327 * part of an 'always on' power well by design, so we don't need to worry about
328 * forcewake while reading it.
329 */
intel_ipver_early_init(struct drm_i915_private * i915)330 static void intel_ipver_early_init(struct drm_i915_private *i915)
331 {
332 struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
333
334 if (!HAS_GMD_ID(i915)) {
335 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
336 /*
337 * On older platforms, graphics and media share the same ip
338 * version and release.
339 */
340 RUNTIME_INFO(i915)->media.ip =
341 RUNTIME_INFO(i915)->graphics.ip;
342 return;
343 }
344
345 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
346 &runtime->graphics.ip);
347 /* Wa_22012778468 */
348 if (runtime->graphics.ip.ver == 0x0 &&
349 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
350 RUNTIME_INFO(i915)->graphics.ip.ver = 12;
351 RUNTIME_INFO(i915)->graphics.ip.rel = 70;
352 }
353 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY),
354 &runtime->display.ip);
355 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
356 &runtime->media.ip);
357 }
358
359 /**
360 * intel_device_info_runtime_init_early - initialize early runtime info
361 * @i915: the i915 device
362 *
363 * Determine early intel_device_info fields at runtime. This function needs
364 * to be called before the MMIO has been setup.
365 */
intel_device_info_runtime_init_early(struct drm_i915_private * i915)366 void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
367 {
368 intel_ipver_early_init(i915);
369 intel_device_info_subplatform_init(i915);
370 }
371
372 /**
373 * intel_device_info_runtime_init - initialize runtime info
374 * @dev_priv: the i915 device
375 *
376 * Determine various intel_device_info fields at runtime.
377 *
378 * Use it when either:
379 * - it's judged too laborious to fill n static structures with the limit
380 * when a simple if statement does the job,
381 * - run-time checks (eg read fuse/strap registers) are needed.
382 *
383 * This function needs to be called:
384 * - after the MMIO has been setup as we are reading registers,
385 * - after the PCH has been detected,
386 * - before the first usage of the fields it can tweak.
387 */
intel_device_info_runtime_init(struct drm_i915_private * dev_priv)388 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
389 {
390 struct intel_device_info *info = mkwrite_device_info(dev_priv);
391 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
392 enum pipe pipe;
393
394 /* Wa_14011765242: adl-s A0,A1 */
395 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
396 for_each_pipe(dev_priv, pipe)
397 runtime->num_scalers[pipe] = 0;
398 else if (DISPLAY_VER(dev_priv) >= 11) {
399 for_each_pipe(dev_priv, pipe)
400 runtime->num_scalers[pipe] = 2;
401 } else if (DISPLAY_VER(dev_priv) >= 9) {
402 runtime->num_scalers[PIPE_A] = 2;
403 runtime->num_scalers[PIPE_B] = 2;
404 runtime->num_scalers[PIPE_C] = 1;
405 }
406
407 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
408
409 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
410 for_each_pipe(dev_priv, pipe)
411 runtime->num_sprites[pipe] = 4;
412 else if (DISPLAY_VER(dev_priv) >= 11)
413 for_each_pipe(dev_priv, pipe)
414 runtime->num_sprites[pipe] = 6;
415 else if (DISPLAY_VER(dev_priv) == 10)
416 for_each_pipe(dev_priv, pipe)
417 runtime->num_sprites[pipe] = 3;
418 else if (IS_BROXTON(dev_priv)) {
419 /*
420 * Skylake and Broxton currently don't expose the topmost plane as its
421 * use is exclusive with the legacy cursor and we only want to expose
422 * one of those, not both. Until we can safely expose the topmost plane
423 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
424 * we don't expose the topmost plane at all to prevent ABI breakage
425 * down the line.
426 */
427
428 runtime->num_sprites[PIPE_A] = 2;
429 runtime->num_sprites[PIPE_B] = 2;
430 runtime->num_sprites[PIPE_C] = 1;
431 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
432 for_each_pipe(dev_priv, pipe)
433 runtime->num_sprites[pipe] = 2;
434 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
435 for_each_pipe(dev_priv, pipe)
436 runtime->num_sprites[pipe] = 1;
437 }
438
439 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
440 HAS_PCH_SPLIT(dev_priv)) {
441 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
442 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
443
444 /*
445 * SFUSE_STRAP is supposed to have a bit signalling the display
446 * is fused off. Unfortunately it seems that, at least in
447 * certain cases, fused off display means that PCH display
448 * reads don't land anywhere. In that case, we read 0s.
449 *
450 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
451 * should be set when taking over after the firmware.
452 */
453 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
454 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
455 (HAS_PCH_CPT(dev_priv) &&
456 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
457 drm_info(&dev_priv->drm,
458 "Display fused off, disabling\n");
459 runtime->pipe_mask = 0;
460 runtime->cpu_transcoder_mask = 0;
461 runtime->fbc_mask = 0;
462 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
463 drm_info(&dev_priv->drm, "PipeC fused off\n");
464 runtime->pipe_mask &= ~BIT(PIPE_C);
465 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
466 }
467 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
468 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
469
470 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
471 runtime->pipe_mask &= ~BIT(PIPE_A);
472 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
473 runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
474 }
475 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
476 runtime->pipe_mask &= ~BIT(PIPE_B);
477 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
478 }
479 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
480 runtime->pipe_mask &= ~BIT(PIPE_C);
481 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
482 }
483
484 if (DISPLAY_VER(dev_priv) >= 12 &&
485 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
486 runtime->pipe_mask &= ~BIT(PIPE_D);
487 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
488 }
489
490 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
491 runtime->has_hdcp = 0;
492
493 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
494 runtime->fbc_mask = 0;
495
496 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
497 runtime->has_dmc = 0;
498
499 if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
500 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
501 runtime->has_dsc = 0;
502 }
503
504 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
505 drm_info(&dev_priv->drm,
506 "Disabling ppGTT for VT-d support\n");
507 runtime->ppgtt_type = INTEL_PPGTT_NONE;
508 }
509
510 runtime->rawclk_freq = intel_read_rawclk(dev_priv);
511 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
512
513 if (!HAS_DISPLAY(dev_priv)) {
514 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
515 DRIVER_ATOMIC);
516 memset(&info->display, 0, sizeof(info->display));
517
518 runtime->cpu_transcoder_mask = 0;
519 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
520 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
521 runtime->fbc_mask = 0;
522 runtime->has_hdcp = false;
523 runtime->has_dmc = false;
524 runtime->has_dsc = false;
525 }
526
527 /* Disable nuclear pageflip by default on pre-g4x */
528 if (!dev_priv->params.nuclear_pageflip &&
529 DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
530 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
531 }
532
intel_driver_caps_print(const struct intel_driver_caps * caps,struct drm_printer * p)533 void intel_driver_caps_print(const struct intel_driver_caps *caps,
534 struct drm_printer *p)
535 {
536 drm_printf(p, "Has logical contexts? %s\n",
537 str_yes_no(caps->has_logical_contexts));
538 drm_printf(p, "scheduler: %x\n", caps->scheduler);
539 }
540