1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_de.h"
9 #include "intel_display.h"
10 #include "intel_display_power_map.h"
11 #include "intel_display_types.h"
12 #include "intel_dkl_phy_regs.h"
13 #include "intel_dp_mst.h"
14 #include "intel_mg_phy_regs.h"
15 #include "intel_tc.h"
16 
tc_port_mode_name(enum tc_port_mode mode)17 static const char *tc_port_mode_name(enum tc_port_mode mode)
18 {
19 	static const char * const names[] = {
20 		[TC_PORT_DISCONNECTED] = "disconnected",
21 		[TC_PORT_TBT_ALT] = "tbt-alt",
22 		[TC_PORT_DP_ALT] = "dp-alt",
23 		[TC_PORT_LEGACY] = "legacy",
24 	};
25 
26 	if (WARN_ON(mode >= ARRAY_SIZE(names)))
27 		mode = TC_PORT_DISCONNECTED;
28 
29 	return names[mode];
30 }
31 
intel_tc_port_in_mode(struct intel_digital_port * dig_port,enum tc_port_mode mode)32 static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port,
33 				  enum tc_port_mode mode)
34 {
35 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
36 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
37 
38 	return intel_phy_is_tc(i915, phy) && dig_port->tc_mode == mode;
39 }
40 
intel_tc_port_in_tbt_alt_mode(struct intel_digital_port * dig_port)41 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port)
42 {
43 	return intel_tc_port_in_mode(dig_port, TC_PORT_TBT_ALT);
44 }
45 
intel_tc_port_in_dp_alt_mode(struct intel_digital_port * dig_port)46 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port)
47 {
48 	return intel_tc_port_in_mode(dig_port, TC_PORT_DP_ALT);
49 }
50 
intel_tc_port_in_legacy_mode(struct intel_digital_port * dig_port)51 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
52 {
53 	return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY);
54 }
55 
intel_tc_cold_requires_aux_pw(struct intel_digital_port * dig_port)56 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
57 {
58 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
59 
60 	return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
61 		IS_ALDERLAKE_P(i915);
62 }
63 
64 static enum intel_display_power_domain
tc_cold_get_power_domain(struct intel_digital_port * dig_port,enum tc_port_mode mode)65 tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode)
66 {
67 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
68 
69 	if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port))
70 		return POWER_DOMAIN_TC_COLD_OFF;
71 
72 	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
73 }
74 
75 static intel_wakeref_t
tc_cold_block_in_mode(struct intel_digital_port * dig_port,enum tc_port_mode mode,enum intel_display_power_domain * domain)76 tc_cold_block_in_mode(struct intel_digital_port *dig_port, enum tc_port_mode mode,
77 		      enum intel_display_power_domain *domain)
78 {
79 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
80 
81 	*domain = tc_cold_get_power_domain(dig_port, mode);
82 
83 	return intel_display_power_get(i915, *domain);
84 }
85 
86 static intel_wakeref_t
tc_cold_block(struct intel_digital_port * dig_port,enum intel_display_power_domain * domain)87 tc_cold_block(struct intel_digital_port *dig_port, enum intel_display_power_domain *domain)
88 {
89 	return tc_cold_block_in_mode(dig_port, dig_port->tc_mode, domain);
90 }
91 
92 static void
tc_cold_unblock(struct intel_digital_port * dig_port,enum intel_display_power_domain domain,intel_wakeref_t wakeref)93 tc_cold_unblock(struct intel_digital_port *dig_port, enum intel_display_power_domain domain,
94 		intel_wakeref_t wakeref)
95 {
96 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
97 
98 	/*
99 	 * wakeref == -1, means some error happened saving save_depot_stack but
100 	 * power should still be put down and 0 is a invalid save_depot_stack
101 	 * id so can be used to skip it for non TC legacy ports.
102 	 */
103 	if (wakeref == 0)
104 		return;
105 
106 	intel_display_power_put(i915, domain, wakeref);
107 }
108 
109 static void
assert_tc_cold_blocked(struct intel_digital_port * dig_port)110 assert_tc_cold_blocked(struct intel_digital_port *dig_port)
111 {
112 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
113 	bool enabled;
114 
115 	enabled = intel_display_power_is_enabled(i915,
116 						 tc_cold_get_power_domain(dig_port,
117 									  dig_port->tc_mode));
118 	drm_WARN_ON(&i915->drm, !enabled);
119 }
120 
intel_tc_port_get_lane_mask(struct intel_digital_port * dig_port)121 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
122 {
123 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
124 	u32 lane_mask;
125 
126 	lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
127 
128 	drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
129 	assert_tc_cold_blocked(dig_port);
130 
131 	lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
132 	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
133 }
134 
intel_tc_port_get_pin_assignment_mask(struct intel_digital_port * dig_port)135 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
136 {
137 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
138 	u32 pin_mask;
139 
140 	pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
141 
142 	drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
143 	assert_tc_cold_blocked(dig_port);
144 
145 	return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
146 	       DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
147 }
148 
intel_tc_port_fia_max_lane_count(struct intel_digital_port * dig_port)149 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
150 {
151 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
152 	intel_wakeref_t wakeref;
153 	u32 lane_mask;
154 
155 	if (dig_port->tc_mode != TC_PORT_DP_ALT)
156 		return 4;
157 
158 	assert_tc_cold_blocked(dig_port);
159 
160 	lane_mask = 0;
161 	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
162 		lane_mask = intel_tc_port_get_lane_mask(dig_port);
163 
164 	switch (lane_mask) {
165 	default:
166 		MISSING_CASE(lane_mask);
167 		fallthrough;
168 	case 0x1:
169 	case 0x2:
170 	case 0x4:
171 	case 0x8:
172 		return 1;
173 	case 0x3:
174 	case 0xc:
175 		return 2;
176 	case 0xf:
177 		return 4;
178 	}
179 }
180 
intel_tc_port_set_fia_lane_count(struct intel_digital_port * dig_port,int required_lanes)181 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
182 				      int required_lanes)
183 {
184 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
185 	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
186 	u32 val;
187 
188 	drm_WARN_ON(&i915->drm,
189 		    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
190 
191 	assert_tc_cold_blocked(dig_port);
192 
193 	val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
194 	val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
195 
196 	switch (required_lanes) {
197 	case 1:
198 		val |= lane_reversal ?
199 			DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
200 			DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
201 		break;
202 	case 2:
203 		val |= lane_reversal ?
204 			DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
205 			DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
206 		break;
207 	case 4:
208 		val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
209 		break;
210 	default:
211 		MISSING_CASE(required_lanes);
212 	}
213 
214 	intel_de_write(i915, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
215 }
216 
tc_port_fixup_legacy_flag(struct intel_digital_port * dig_port,u32 live_status_mask)217 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
218 				      u32 live_status_mask)
219 {
220 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
221 	u32 valid_hpd_mask;
222 
223 	if (dig_port->tc_legacy_port)
224 		valid_hpd_mask = BIT(TC_PORT_LEGACY);
225 	else
226 		valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
227 				 BIT(TC_PORT_TBT_ALT);
228 
229 	if (!(live_status_mask & ~valid_hpd_mask))
230 		return;
231 
232 	/* If live status mismatches the VBT flag, trust the live status. */
233 	drm_dbg_kms(&i915->drm,
234 		    "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
235 		    dig_port->tc_port_name, live_status_mask, valid_hpd_mask);
236 
237 	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
238 }
239 
icl_tc_port_live_status_mask(struct intel_digital_port * dig_port)240 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
241 {
242 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
243 	u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
244 	u32 mask = 0;
245 	u32 val;
246 
247 	val = intel_de_read(i915, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
248 
249 	if (val == 0xffffffff) {
250 		drm_dbg_kms(&i915->drm,
251 			    "Port %s: PHY in TCCOLD, nothing connected\n",
252 			    dig_port->tc_port_name);
253 		return mask;
254 	}
255 
256 	if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
257 		mask |= BIT(TC_PORT_TBT_ALT);
258 	if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
259 		mask |= BIT(TC_PORT_DP_ALT);
260 
261 	if (intel_de_read(i915, SDEISR) & isr_bit)
262 		mask |= BIT(TC_PORT_LEGACY);
263 
264 	/* The sink can be connected only in a single mode. */
265 	if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
266 		tc_port_fixup_legacy_flag(dig_port, mask);
267 
268 	return mask;
269 }
270 
adl_tc_port_live_status_mask(struct intel_digital_port * dig_port)271 static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
272 {
273 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
274 	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
275 	u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
276 	u32 val, mask = 0;
277 
278 	/*
279 	 * On ADL-P HW/FW will wake from TCCOLD to complete the read access of
280 	 * registers in IOM. Note that this doesn't apply to PHY and FIA
281 	 * registers.
282 	 */
283 	val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
284 	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
285 		mask |= BIT(TC_PORT_DP_ALT);
286 	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
287 		mask |= BIT(TC_PORT_TBT_ALT);
288 
289 	if (intel_de_read(i915, SDEISR) & isr_bit)
290 		mask |= BIT(TC_PORT_LEGACY);
291 
292 	/* The sink can be connected only in a single mode. */
293 	if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
294 		tc_port_fixup_legacy_flag(dig_port, mask);
295 
296 	return mask;
297 }
298 
tc_port_live_status_mask(struct intel_digital_port * dig_port)299 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
300 {
301 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
302 
303 	if (IS_ALDERLAKE_P(i915))
304 		return adl_tc_port_live_status_mask(dig_port);
305 
306 	return icl_tc_port_live_status_mask(dig_port);
307 }
308 
309 /*
310  * Return the PHY status complete flag indicating that display can acquire the
311  * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink
312  * is connected and it's ready to switch the ownership to display. The flag
313  * will be left cleared when a TBT-alt sink is connected, where the PHY is
314  * owned by the TBT subsystem and so switching the ownership to display is not
315  * required.
316  */
icl_tc_phy_status_complete(struct intel_digital_port * dig_port)317 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
318 {
319 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
320 	u32 val;
321 
322 	val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
323 	if (val == 0xffffffff) {
324 		drm_dbg_kms(&i915->drm,
325 			    "Port %s: PHY in TCCOLD, assuming not complete\n",
326 			    dig_port->tc_port_name);
327 		return false;
328 	}
329 
330 	return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
331 }
332 
333 /*
334  * Return the PHY status complete flag indicating that display can acquire the
335  * PHY ownership. The IOM firmware sets this flag when it's ready to switch
336  * the ownership to display, regardless of what sink is connected (TBT-alt,
337  * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT
338  * subsystem and so switching the ownership to display is not required.
339  */
adl_tc_phy_status_complete(struct intel_digital_port * dig_port)340 static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
341 {
342 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
343 	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
344 	u32 val;
345 
346 	val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
347 	if (val == 0xffffffff) {
348 		drm_dbg_kms(&i915->drm,
349 			    "Port %s: PHY in TCCOLD, assuming not complete\n",
350 			    dig_port->tc_port_name);
351 		return false;
352 	}
353 
354 	return val & TCSS_DDI_STATUS_READY;
355 }
356 
tc_phy_status_complete(struct intel_digital_port * dig_port)357 static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
358 {
359 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
360 
361 	if (IS_ALDERLAKE_P(i915))
362 		return adl_tc_phy_status_complete(dig_port);
363 
364 	return icl_tc_phy_status_complete(dig_port);
365 }
366 
icl_tc_phy_take_ownership(struct intel_digital_port * dig_port,bool take)367 static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
368 				      bool take)
369 {
370 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
371 	u32 val;
372 
373 	val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
374 	if (val == 0xffffffff) {
375 		drm_dbg_kms(&i915->drm,
376 			    "Port %s: PHY in TCCOLD, can't %s ownership\n",
377 			    dig_port->tc_port_name, take ? "take" : "release");
378 
379 		return false;
380 	}
381 
382 	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
383 	if (take)
384 		val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
385 
386 	intel_de_write(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
387 
388 	return true;
389 }
390 
adl_tc_phy_take_ownership(struct intel_digital_port * dig_port,bool take)391 static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
392 				      bool take)
393 {
394 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
395 	enum port port = dig_port->base.port;
396 
397 	intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,
398 		     take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0);
399 
400 	return true;
401 }
402 
tc_phy_take_ownership(struct intel_digital_port * dig_port,bool take)403 static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
404 {
405 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
406 
407 	if (IS_ALDERLAKE_P(i915))
408 		return adl_tc_phy_take_ownership(dig_port, take);
409 
410 	return icl_tc_phy_take_ownership(dig_port, take);
411 }
412 
icl_tc_phy_is_owned(struct intel_digital_port * dig_port)413 static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
414 {
415 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
416 	u32 val;
417 
418 	val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
419 	if (val == 0xffffffff) {
420 		drm_dbg_kms(&i915->drm,
421 			    "Port %s: PHY in TCCOLD, assume safe mode\n",
422 			    dig_port->tc_port_name);
423 		return true;
424 	}
425 
426 	return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
427 }
428 
adl_tc_phy_is_owned(struct intel_digital_port * dig_port)429 static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
430 {
431 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
432 	enum port port = dig_port->base.port;
433 	u32 val;
434 
435 	val = intel_de_read(i915, DDI_BUF_CTL(port));
436 	return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
437 }
438 
tc_phy_is_owned(struct intel_digital_port * dig_port)439 static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
440 {
441 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
442 
443 	if (IS_ALDERLAKE_P(i915))
444 		return adl_tc_phy_is_owned(dig_port);
445 
446 	return icl_tc_phy_is_owned(dig_port);
447 }
448 
449 /*
450  * This function implements the first part of the Connect Flow described by our
451  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
452  * lanes, EDID, etc) is done as needed in the typical places.
453  *
454  * Unlike the other ports, type-C ports are not available to use as soon as we
455  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
456  * display, USB, etc. As a result, handshaking through FIA is required around
457  * connect and disconnect to cleanly transfer ownership with the controller and
458  * set the type-C power state.
459  */
icl_tc_phy_connect(struct intel_digital_port * dig_port,int required_lanes)460 static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
461 			       int required_lanes)
462 {
463 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
464 	u32 live_status_mask;
465 	int max_lanes;
466 
467 	if (!tc_phy_status_complete(dig_port)) {
468 		drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
469 			    dig_port->tc_port_name);
470 		goto out_set_tbt_alt_mode;
471 	}
472 
473 	live_status_mask = tc_port_live_status_mask(dig_port);
474 	if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY))) &&
475 	    !dig_port->tc_legacy_port) {
476 		drm_dbg_kms(&i915->drm, "Port %s: PHY ownership not required (live status %02x)\n",
477 			    dig_port->tc_port_name, live_status_mask);
478 		goto out_set_tbt_alt_mode;
479 	}
480 
481 	if (!tc_phy_take_ownership(dig_port, true) &&
482 	    !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
483 		goto out_set_tbt_alt_mode;
484 
485 	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
486 	if (dig_port->tc_legacy_port) {
487 		drm_WARN_ON(&i915->drm, max_lanes != 4);
488 		dig_port->tc_mode = TC_PORT_LEGACY;
489 
490 		return;
491 	}
492 
493 	/*
494 	 * Now we have to re-check the live state, in case the port recently
495 	 * became disconnected. Not necessary for legacy mode.
496 	 */
497 	if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
498 		drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
499 			    dig_port->tc_port_name);
500 		goto out_release_phy;
501 	}
502 
503 	if (max_lanes < required_lanes) {
504 		drm_dbg_kms(&i915->drm,
505 			    "Port %s: PHY max lanes %d < required lanes %d\n",
506 			    dig_port->tc_port_name,
507 			    max_lanes, required_lanes);
508 		goto out_release_phy;
509 	}
510 
511 	dig_port->tc_mode = TC_PORT_DP_ALT;
512 
513 	return;
514 
515 out_release_phy:
516 	tc_phy_take_ownership(dig_port, false);
517 out_set_tbt_alt_mode:
518 	dig_port->tc_mode = TC_PORT_TBT_ALT;
519 }
520 
521 /*
522  * See the comment at the connect function. This implements the Disconnect
523  * Flow.
524  */
icl_tc_phy_disconnect(struct intel_digital_port * dig_port)525 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
526 {
527 	switch (dig_port->tc_mode) {
528 	case TC_PORT_LEGACY:
529 	case TC_PORT_DP_ALT:
530 		tc_phy_take_ownership(dig_port, false);
531 		fallthrough;
532 	case TC_PORT_TBT_ALT:
533 		dig_port->tc_mode = TC_PORT_DISCONNECTED;
534 		fallthrough;
535 	case TC_PORT_DISCONNECTED:
536 		break;
537 	default:
538 		MISSING_CASE(dig_port->tc_mode);
539 	}
540 }
541 
icl_tc_phy_is_connected(struct intel_digital_port * dig_port)542 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
543 {
544 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
545 
546 	if (!tc_phy_status_complete(dig_port)) {
547 		drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
548 			    dig_port->tc_port_name);
549 		return dig_port->tc_mode == TC_PORT_TBT_ALT;
550 	}
551 
552 	/* On ADL-P the PHY complete flag is set in TBT mode as well. */
553 	if (IS_ALDERLAKE_P(i915) && dig_port->tc_mode == TC_PORT_TBT_ALT)
554 		return true;
555 
556 	if (!tc_phy_is_owned(dig_port)) {
557 		drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
558 			    dig_port->tc_port_name);
559 
560 		return false;
561 	}
562 
563 	return dig_port->tc_mode == TC_PORT_DP_ALT ||
564 	       dig_port->tc_mode == TC_PORT_LEGACY;
565 }
566 
567 static enum tc_port_mode
intel_tc_port_get_current_mode(struct intel_digital_port * dig_port)568 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
569 {
570 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
571 	u32 live_status_mask = tc_port_live_status_mask(dig_port);
572 	enum tc_port_mode mode;
573 
574 	if (!tc_phy_is_owned(dig_port) ||
575 	    drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
576 		return TC_PORT_TBT_ALT;
577 
578 	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
579 	if (live_status_mask) {
580 		enum tc_port_mode live_mode = fls(live_status_mask) - 1;
581 
582 		if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT))
583 			mode = live_mode;
584 	}
585 
586 	return mode;
587 }
588 
589 static enum tc_port_mode
intel_tc_port_get_target_mode(struct intel_digital_port * dig_port)590 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
591 {
592 	u32 live_status_mask = tc_port_live_status_mask(dig_port);
593 
594 	if (live_status_mask)
595 		return fls(live_status_mask) - 1;
596 
597 	return TC_PORT_TBT_ALT;
598 }
599 
intel_tc_port_reset_mode(struct intel_digital_port * dig_port,int required_lanes,bool force_disconnect)600 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
601 				     int required_lanes, bool force_disconnect)
602 {
603 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
604 	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
605 
606 	intel_display_power_flush_work(i915);
607 	if (!intel_tc_cold_requires_aux_pw(dig_port)) {
608 		enum intel_display_power_domain aux_domain;
609 		bool aux_powered;
610 
611 		aux_domain = intel_aux_power_domain(dig_port);
612 		aux_powered = intel_display_power_is_enabled(i915, aux_domain);
613 		drm_WARN_ON(&i915->drm, aux_powered);
614 	}
615 
616 	icl_tc_phy_disconnect(dig_port);
617 	if (!force_disconnect)
618 		icl_tc_phy_connect(dig_port, required_lanes);
619 
620 	drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n",
621 		    dig_port->tc_port_name,
622 		    tc_port_mode_name(old_tc_mode),
623 		    tc_port_mode_name(dig_port->tc_mode));
624 }
625 
intel_tc_port_needs_reset(struct intel_digital_port * dig_port)626 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
627 {
628 	return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
629 }
630 
intel_tc_port_update_mode(struct intel_digital_port * dig_port,int required_lanes,bool force_disconnect)631 static void intel_tc_port_update_mode(struct intel_digital_port *dig_port,
632 				      int required_lanes, bool force_disconnect)
633 {
634 	enum intel_display_power_domain domain;
635 	intel_wakeref_t wref;
636 	bool needs_reset = force_disconnect;
637 
638 	if (!needs_reset) {
639 		/* Get power domain required to check the hotplug live status. */
640 		wref = tc_cold_block(dig_port, &domain);
641 		needs_reset = intel_tc_port_needs_reset(dig_port);
642 		tc_cold_unblock(dig_port, domain, wref);
643 	}
644 
645 	if (!needs_reset)
646 		return;
647 
648 	/* Get power domain required for resetting the mode. */
649 	wref = tc_cold_block_in_mode(dig_port, TC_PORT_DISCONNECTED, &domain);
650 
651 	intel_tc_port_reset_mode(dig_port, required_lanes, force_disconnect);
652 
653 	/* Get power domain matching the new mode after reset. */
654 	tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain,
655 			fetch_and_zero(&dig_port->tc_lock_wakeref));
656 	if (dig_port->tc_mode != TC_PORT_DISCONNECTED)
657 		dig_port->tc_lock_wakeref = tc_cold_block(dig_port,
658 							  &dig_port->tc_lock_power_domain);
659 
660 	tc_cold_unblock(dig_port, domain, wref);
661 }
662 
663 static void
intel_tc_port_link_init_refcount(struct intel_digital_port * dig_port,int refcount)664 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
665 				 int refcount)
666 {
667 	dig_port->tc_link_refcount = refcount;
668 }
669 
670 /**
671  * intel_tc_port_init_mode: Read out HW state and init the given port's TypeC mode
672  * @dig_port: digital port
673  *
674  * Read out the HW state and initialize the TypeC mode of @dig_port. The mode
675  * will be locked until intel_tc_port_sanitize_mode() is called.
676  */
intel_tc_port_init_mode(struct intel_digital_port * dig_port)677 void intel_tc_port_init_mode(struct intel_digital_port *dig_port)
678 {
679 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
680 	intel_wakeref_t tc_cold_wref;
681 	enum intel_display_power_domain domain;
682 
683 	mutex_lock(&dig_port->tc_lock);
684 
685 	drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED);
686 	drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
687 	drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
688 
689 	tc_cold_wref = tc_cold_block(dig_port, &domain);
690 
691 	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
692 	/* Prevent changing dig_port->tc_mode until intel_tc_port_sanitize_mode() is called. */
693 	intel_tc_port_link_init_refcount(dig_port, 1);
694 	dig_port->tc_lock_wakeref = tc_cold_block(dig_port, &dig_port->tc_lock_power_domain);
695 
696 	tc_cold_unblock(dig_port, domain, tc_cold_wref);
697 
698 	drm_dbg_kms(&i915->drm, "Port %s: init mode (%s)\n",
699 		    dig_port->tc_port_name,
700 		    tc_port_mode_name(dig_port->tc_mode));
701 
702 	mutex_unlock(&dig_port->tc_lock);
703 }
704 
705 /**
706  * intel_tc_port_sanitize_mode: Sanitize the given port's TypeC mode
707  * @dig_port: digital port
708  *
709  * Sanitize @dig_port's TypeC mode wrt. the encoder's state right after driver
710  * loading and system resume:
711  * If the encoder is enabled keep the TypeC mode/PHY connected state locked until
712  * the encoder is disabled.
713  * If the encoder is disabled make sure the PHY is disconnected.
714  */
intel_tc_port_sanitize_mode(struct intel_digital_port * dig_port)715 void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port)
716 {
717 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
718 	struct intel_encoder *encoder = &dig_port->base;
719 	int active_links = 0;
720 
721 	mutex_lock(&dig_port->tc_lock);
722 
723 	if (dig_port->dp.is_mst)
724 		active_links = intel_dp_mst_encoder_active_links(dig_port);
725 	else if (encoder->base.crtc)
726 		active_links = to_intel_crtc(encoder->base.crtc)->active;
727 
728 	drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount != 1);
729 	intel_tc_port_link_init_refcount(dig_port, active_links);
730 
731 	if (active_links) {
732 		if (!icl_tc_phy_is_connected(dig_port))
733 			drm_dbg_kms(&i915->drm,
734 				    "Port %s: PHY disconnected with %d active link(s)\n",
735 				    dig_port->tc_port_name, active_links);
736 	} else {
737 		/*
738 		 * TBT-alt is the default mode in any case the PHY ownership is not
739 		 * held (regardless of the sink's connected live state), so
740 		 * we'll just switch to disconnected mode from it here without
741 		 * a note.
742 		 */
743 		if (dig_port->tc_mode != TC_PORT_TBT_ALT)
744 			drm_dbg_kms(&i915->drm,
745 				    "Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
746 				    dig_port->tc_port_name,
747 				    tc_port_mode_name(dig_port->tc_mode));
748 		icl_tc_phy_disconnect(dig_port);
749 
750 		tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain,
751 				fetch_and_zero(&dig_port->tc_lock_wakeref));
752 	}
753 
754 	drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
755 		    dig_port->tc_port_name,
756 		    tc_port_mode_name(dig_port->tc_mode));
757 
758 	mutex_unlock(&dig_port->tc_lock);
759 }
760 
761 /*
762  * The type-C ports are different because even when they are connected, they may
763  * not be available/usable by the graphics driver: see the comment on
764  * icl_tc_phy_connect(). So in our driver instead of adding the additional
765  * concept of "usable" and make everything check for "connected and usable" we
766  * define a port as "connected" when it is not only connected, but also when it
767  * is usable by the rest of the driver. That maintains the old assumption that
768  * connected ports are usable, and avoids exposing to the users objects they
769  * can't really use.
770  */
intel_tc_port_connected(struct intel_encoder * encoder)771 bool intel_tc_port_connected(struct intel_encoder *encoder)
772 {
773 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
774 	bool is_connected;
775 
776 	intel_tc_port_lock(dig_port);
777 
778 	is_connected = tc_port_live_status_mask(dig_port) &
779 		       BIT(dig_port->tc_mode);
780 
781 	intel_tc_port_unlock(dig_port);
782 
783 	return is_connected;
784 }
785 
__intel_tc_port_lock(struct intel_digital_port * dig_port,int required_lanes)786 static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
787 				 int required_lanes)
788 {
789 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
790 
791 	mutex_lock(&dig_port->tc_lock);
792 
793 	cancel_delayed_work(&dig_port->tc_disconnect_phy_work);
794 
795 	if (!dig_port->tc_link_refcount)
796 		intel_tc_port_update_mode(dig_port, required_lanes,
797 					  false);
798 
799 	drm_WARN_ON(&i915->drm, dig_port->tc_mode == TC_PORT_DISCONNECTED);
800 	drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_TBT_ALT &&
801 				!tc_phy_is_owned(dig_port));
802 }
803 
intel_tc_port_lock(struct intel_digital_port * dig_port)804 void intel_tc_port_lock(struct intel_digital_port *dig_port)
805 {
806 	__intel_tc_port_lock(dig_port, 1);
807 }
808 
809 /**
810  * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port
811  * @dig_port: digital port
812  *
813  * Disconnect the given digital port from its TypeC PHY (handing back the
814  * control of the PHY to the TypeC subsystem). This will happen in a delayed
815  * manner after each aux transactions and modeset disables.
816  */
intel_tc_port_disconnect_phy_work(struct work_struct * work)817 static void intel_tc_port_disconnect_phy_work(struct work_struct *work)
818 {
819 	struct intel_digital_port *dig_port =
820 		container_of(work, struct intel_digital_port, tc_disconnect_phy_work.work);
821 
822 	mutex_lock(&dig_port->tc_lock);
823 
824 	if (!dig_port->tc_link_refcount)
825 		intel_tc_port_update_mode(dig_port, 1, true);
826 
827 	mutex_unlock(&dig_port->tc_lock);
828 }
829 
830 /**
831  * intel_tc_port_flush_work: flush the work disconnecting the PHY
832  * @dig_port: digital port
833  *
834  * Flush the delayed work disconnecting an idle PHY.
835  */
intel_tc_port_flush_work(struct intel_digital_port * dig_port)836 void intel_tc_port_flush_work(struct intel_digital_port *dig_port)
837 {
838 	flush_delayed_work(&dig_port->tc_disconnect_phy_work);
839 }
840 
intel_tc_port_unlock(struct intel_digital_port * dig_port)841 void intel_tc_port_unlock(struct intel_digital_port *dig_port)
842 {
843 	if (!dig_port->tc_link_refcount && dig_port->tc_mode != TC_PORT_DISCONNECTED)
844 		queue_delayed_work(system_unbound_wq, &dig_port->tc_disconnect_phy_work,
845 				   msecs_to_jiffies(1000));
846 
847 	mutex_unlock(&dig_port->tc_lock);
848 }
849 
intel_tc_port_ref_held(struct intel_digital_port * dig_port)850 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
851 {
852 	return mutex_is_locked(&dig_port->tc_lock) ||
853 	       dig_port->tc_link_refcount;
854 }
855 
intel_tc_port_get_link(struct intel_digital_port * dig_port,int required_lanes)856 void intel_tc_port_get_link(struct intel_digital_port *dig_port,
857 			    int required_lanes)
858 {
859 	__intel_tc_port_lock(dig_port, required_lanes);
860 	dig_port->tc_link_refcount++;
861 	intel_tc_port_unlock(dig_port);
862 }
863 
intel_tc_port_put_link(struct intel_digital_port * dig_port)864 void intel_tc_port_put_link(struct intel_digital_port *dig_port)
865 {
866 	intel_tc_port_lock(dig_port);
867 	--dig_port->tc_link_refcount;
868 	intel_tc_port_unlock(dig_port);
869 
870 	/*
871 	 * Disconnecting the PHY after the PHY's PLL gets disabled may
872 	 * hang the system on ADL-P, so disconnect the PHY here synchronously.
873 	 * TODO: remove this once the root cause of the ordering requirement
874 	 * is found/fixed.
875 	 */
876 	intel_tc_port_flush_work(dig_port);
877 }
878 
879 static bool
tc_has_modular_fia(struct drm_i915_private * i915,struct intel_digital_port * dig_port)880 tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
881 {
882 	enum intel_display_power_domain domain;
883 	intel_wakeref_t wakeref;
884 	u32 val;
885 
886 	if (!INTEL_INFO(i915)->display.has_modular_fia)
887 		return false;
888 
889 	mutex_lock(&dig_port->tc_lock);
890 	wakeref = tc_cold_block(dig_port, &domain);
891 	val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1));
892 	tc_cold_unblock(dig_port, domain, wakeref);
893 	mutex_unlock(&dig_port->tc_lock);
894 
895 	drm_WARN_ON(&i915->drm, val == 0xffffffff);
896 
897 	return val & MODULAR_FIA_MASK;
898 }
899 
900 static void
tc_port_load_fia_params(struct drm_i915_private * i915,struct intel_digital_port * dig_port)901 tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
902 {
903 	enum port port = dig_port->base.port;
904 	enum tc_port tc_port = intel_port_to_tc(i915, port);
905 
906 	/*
907 	 * Each Modular FIA instance houses 2 TC ports. In SOC that has more
908 	 * than two TC ports, there are multiple instances of Modular FIA.
909 	 */
910 	if (tc_has_modular_fia(i915, dig_port)) {
911 		dig_port->tc_phy_fia = tc_port / 2;
912 		dig_port->tc_phy_fia_idx = tc_port % 2;
913 	} else {
914 		dig_port->tc_phy_fia = FIA1;
915 		dig_port->tc_phy_fia_idx = tc_port;
916 	}
917 }
918 
intel_tc_port_init(struct intel_digital_port * dig_port,bool is_legacy)919 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
920 {
921 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
922 	enum port port = dig_port->base.port;
923 	enum tc_port tc_port = intel_port_to_tc(i915, port);
924 
925 	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
926 		return;
927 
928 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
929 		 "%c/TC#%d", port_name(port), tc_port + 1);
930 
931 	mutex_init(&dig_port->tc_lock);
932 	INIT_DELAYED_WORK(&dig_port->tc_disconnect_phy_work, intel_tc_port_disconnect_phy_work);
933 	dig_port->tc_legacy_port = is_legacy;
934 	dig_port->tc_mode = TC_PORT_DISCONNECTED;
935 	dig_port->tc_link_refcount = 0;
936 	tc_port_load_fia_params(i915, dig_port);
937 
938 	intel_tc_port_init_mode(dig_port);
939 }
940