1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11
12 #include "i915_drv.h"
13 #include "i915_reg.h"
14 #include "intel_crtc.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_dsi.h"
18 #include "intel_qp_tables.h"
19 #include "intel_vdsc.h"
20
21 enum ROW_INDEX_BPP {
22 ROW_INDEX_6BPP = 0,
23 ROW_INDEX_8BPP,
24 ROW_INDEX_10BPP,
25 ROW_INDEX_12BPP,
26 ROW_INDEX_15BPP,
27 MAX_ROW_INDEX
28 };
29
30 enum COLUMN_INDEX_BPC {
31 COLUMN_INDEX_8BPC = 0,
32 COLUMN_INDEX_10BPC,
33 COLUMN_INDEX_12BPC,
34 COLUMN_INDEX_14BPC,
35 COLUMN_INDEX_16BPC,
36 MAX_COLUMN_INDEX
37 };
38
39 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
40 static const u16 rc_buf_thresh[] = {
41 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
42 7744, 7872, 8000, 8064
43 };
44
45 struct rc_parameters {
46 u16 initial_xmit_delay;
47 u8 first_line_bpg_offset;
48 u16 initial_offset;
49 u8 flatness_min_qp;
50 u8 flatness_max_qp;
51 u8 rc_quant_incr_limit0;
52 u8 rc_quant_incr_limit1;
53 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
54 };
55
56 /*
57 * Selected Rate Control Related Parameter Recommended Values
58 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
59 */
60 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
61 {
62 /* 6BPP/8BPC */
63 { 768, 15, 6144, 3, 13, 11, 11, {
64 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
65 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
66 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
67 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
68 }
69 },
70 /* 6BPP/10BPC */
71 { 768, 15, 6144, 7, 17, 15, 15, {
72 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
73 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
74 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
75 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
76 { 17, 18, -12 }
77 }
78 },
79 /* 6BPP/12BPC */
80 { 768, 15, 6144, 11, 21, 19, 19, {
81 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
82 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
83 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
84 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
85 { 21, 22, -12 }
86 }
87 },
88 /* 6BPP/14BPC */
89 { 768, 15, 6144, 15, 25, 23, 27, {
90 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
91 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
92 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
93 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
94 { 25, 26, -12 }
95 }
96 },
97 /* 6BPP/16BPC */
98 { 768, 15, 6144, 19, 29, 27, 27, {
99 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
100 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
101 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
102 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
103 { 29, 30, -12 }
104 }
105 },
106 },
107 {
108 /* 8BPP/8BPC */
109 { 512, 12, 6144, 3, 12, 11, 11, {
110 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
111 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
112 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
113 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
114 }
115 },
116 /* 8BPP/10BPC */
117 { 512, 12, 6144, 7, 16, 15, 15, {
118 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
119 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
120 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
121 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
122 }
123 },
124 /* 8BPP/12BPC */
125 { 512, 12, 6144, 11, 20, 19, 19, {
126 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
127 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
128 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
129 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
130 { 21, 23, -12 }
131 }
132 },
133 /* 8BPP/14BPC */
134 { 512, 12, 6144, 15, 24, 23, 23, {
135 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
136 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
137 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
138 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
139 { 24, 25, -12 }
140 }
141 },
142 /* 8BPP/16BPC */
143 { 512, 12, 6144, 19, 28, 27, 27, {
144 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
145 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
146 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
147 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
148 { 28, 29, -12 }
149 }
150 },
151 },
152 {
153 /* 10BPP/8BPC */
154 { 410, 15, 5632, 3, 12, 11, 11, {
155 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
156 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
157 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
158 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
159 }
160 },
161 /* 10BPP/10BPC */
162 { 410, 15, 5632, 7, 16, 15, 15, {
163 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
164 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
165 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
166 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
167 }
168 },
169 /* 10BPP/12BPC */
170 { 410, 15, 5632, 11, 20, 19, 19, {
171 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
172 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
173 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
174 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
175 { 19, 20, -12 }
176 }
177 },
178 /* 10BPP/14BPC */
179 { 410, 15, 5632, 15, 24, 23, 23, {
180 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
181 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
182 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
183 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
184 { 23, 24, -12 }
185 }
186 },
187 /* 10BPP/16BPC */
188 { 410, 15, 5632, 19, 28, 27, 27, {
189 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
190 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
191 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
192 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
193 { 27, 28, -12 }
194 }
195 },
196 },
197 {
198 /* 12BPP/8BPC */
199 { 341, 15, 2048, 3, 12, 11, 11, {
200 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
201 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
202 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
203 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
204 }
205 },
206 /* 12BPP/10BPC */
207 { 341, 15, 2048, 7, 16, 15, 15, {
208 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
209 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
210 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
211 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
212 }
213 },
214 /* 12BPP/12BPC */
215 { 341, 15, 2048, 11, 20, 19, 19, {
216 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
217 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
218 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
219 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
220 { 21, 23, -12 }
221 }
222 },
223 /* 12BPP/14BPC */
224 { 341, 15, 2048, 15, 24, 23, 23, {
225 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
226 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
227 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
228 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
229 { 22, 23, -12 }
230 }
231 },
232 /* 12BPP/16BPC */
233 { 341, 15, 2048, 19, 28, 27, 27, {
234 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
235 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
236 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
237 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
238 { 26, 27, -12 }
239 }
240 },
241 },
242 {
243 /* 15BPP/8BPC */
244 { 273, 15, 2048, 3, 12, 11, 11, {
245 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
246 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
247 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
248 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
249 }
250 },
251 /* 15BPP/10BPC */
252 { 273, 15, 2048, 7, 16, 15, 15, {
253 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
254 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
255 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
256 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
257 }
258 },
259 /* 15BPP/12BPC */
260 { 273, 15, 2048, 11, 20, 19, 19, {
261 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
262 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
263 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
264 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
265 { 16, 17, -12 }
266 }
267 },
268 /* 15BPP/14BPC */
269 { 273, 15, 2048, 15, 24, 23, 23, {
270 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
271 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
272 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
273 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
274 { 20, 21, -12 }
275 }
276 },
277 /* 15BPP/16BPC */
278 { 273, 15, 2048, 19, 28, 27, 27, {
279 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
280 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
281 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
282 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
283 { 24, 25, -12 }
284 }
285 }
286 }
287
288 };
289
get_row_index_for_rc_params(u16 compressed_bpp)290 static int get_row_index_for_rc_params(u16 compressed_bpp)
291 {
292 switch (compressed_bpp) {
293 case 6:
294 return ROW_INDEX_6BPP;
295 case 8:
296 return ROW_INDEX_8BPP;
297 case 10:
298 return ROW_INDEX_10BPP;
299 case 12:
300 return ROW_INDEX_12BPP;
301 case 15:
302 return ROW_INDEX_15BPP;
303 default:
304 return -EINVAL;
305 }
306 }
307
get_column_index_for_rc_params(u8 bits_per_component)308 static int get_column_index_for_rc_params(u8 bits_per_component)
309 {
310 switch (bits_per_component) {
311 case 8:
312 return COLUMN_INDEX_8BPC;
313 case 10:
314 return COLUMN_INDEX_10BPC;
315 case 12:
316 return COLUMN_INDEX_12BPC;
317 case 14:
318 return COLUMN_INDEX_14BPC;
319 case 16:
320 return COLUMN_INDEX_16BPC;
321 default:
322 return -EINVAL;
323 }
324 }
325
get_rc_params(u16 compressed_bpp,u8 bits_per_component)326 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
327 u8 bits_per_component)
328 {
329 int row_index, column_index;
330
331 row_index = get_row_index_for_rc_params(compressed_bpp);
332 if (row_index < 0)
333 return NULL;
334
335 column_index = get_column_index_for_rc_params(bits_per_component);
336 if (column_index < 0)
337 return NULL;
338
339 return &rc_parameters[row_index][column_index];
340 }
341
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)342 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
343 {
344 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
345 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
346 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
347
348 if (!HAS_DSC(i915))
349 return false;
350
351 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
352 return false;
353
354 return true;
355 }
356
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)357 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
358 {
359 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
360
361 if (DISPLAY_VER(i915) >= 12)
362 return true;
363
364 if (cpu_transcoder == TRANSCODER_EDP ||
365 cpu_transcoder == TRANSCODER_DSI_0 ||
366 cpu_transcoder == TRANSCODER_DSI_1)
367 return false;
368
369 /* There's no pipe A DSC engine on ICL */
370 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
371
372 return true;
373 }
374
375 static void
calculate_rc_params(struct rc_parameters * rc,struct drm_dsc_config * vdsc_cfg)376 calculate_rc_params(struct rc_parameters *rc,
377 struct drm_dsc_config *vdsc_cfg)
378 {
379 int bpc = vdsc_cfg->bits_per_component;
380 int bpp = vdsc_cfg->bits_per_pixel >> 4;
381 static const s8 ofs_und6[] = {
382 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
383 };
384 static const s8 ofs_und8[] = {
385 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
386 };
387 static const s8 ofs_und12[] = {
388 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
389 };
390 static const s8 ofs_und15[] = {
391 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
392 };
393 int qp_bpc_modifier = (bpc - 8) * 2;
394 u32 res, buf_i, bpp_i;
395
396 if (vdsc_cfg->slice_height >= 8)
397 rc->first_line_bpg_offset =
398 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
399 else
400 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
401
402 /* Our hw supports only 444 modes as of today */
403 if (bpp >= 12)
404 rc->initial_offset = 2048;
405 else if (bpp >= 10)
406 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
407 else if (bpp >= 8)
408 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
409 else
410 rc->initial_offset = 6144;
411
412 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
413 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
414
415 rc->flatness_min_qp = 3 + qp_bpc_modifier;
416 rc->flatness_max_qp = 12 + qp_bpc_modifier;
417
418 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
419 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
420
421 bpp_i = (2 * (bpp - 6));
422 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
423 /* Read range_minqp and range_max_qp from qp tables */
424 rc->rc_range_params[buf_i].range_min_qp =
425 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
426 rc->rc_range_params[buf_i].range_max_qp =
427 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
428
429 /* Calculate range_bgp_offset */
430 if (bpp <= 6) {
431 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
432 } else if (bpp <= 8) {
433 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
434 rc->rc_range_params[buf_i].range_bpg_offset =
435 ofs_und6[buf_i] + res;
436 } else if (bpp <= 12) {
437 rc->rc_range_params[buf_i].range_bpg_offset =
438 ofs_und8[buf_i];
439 } else if (bpp <= 15) {
440 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
441 rc->rc_range_params[buf_i].range_bpg_offset =
442 ofs_und12[buf_i] + res;
443 } else {
444 rc->rc_range_params[buf_i].range_bpg_offset =
445 ofs_und15[buf_i];
446 }
447 }
448 }
449
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)450 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
451 {
452 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
454 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
455 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
456 const struct rc_parameters *rc_params;
457 struct rc_parameters *rc = NULL;
458 u8 i = 0;
459
460 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
461 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
462 pipe_config->dsc.slice_count);
463
464 /* Gen 11 does not support YCbCr */
465 vdsc_cfg->simple_422 = false;
466 /* Gen 11 does not support VBR */
467 vdsc_cfg->vbr_enable = false;
468
469 /* Gen 11 only supports integral values of bpp */
470 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
471 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
472
473 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
474 /*
475 * six 0s are appended to the lsb of each threshold value
476 * internally in h/w.
477 * Only 8 bits are allowed for programming RcBufThreshold
478 */
479 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
480 }
481
482 /*
483 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
484 * as per C Model
485 */
486 if (compressed_bpp == 6) {
487 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
488 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
489 }
490
491 /*
492 * From XE_LPD onwards we supports compression bpps in steps of 1
493 * upto uncompressed bpp-1, hence add calculations for all the rc
494 * parameters
495 */
496 if (DISPLAY_VER(dev_priv) >= 13) {
497 rc = kmalloc(sizeof(*rc), GFP_KERNEL);
498 if (!rc)
499 return -ENOMEM;
500
501 calculate_rc_params(rc, vdsc_cfg);
502 rc_params = rc;
503 } else {
504 rc_params = get_rc_params(compressed_bpp,
505 vdsc_cfg->bits_per_component);
506 if (!rc_params)
507 return -EINVAL;
508 }
509
510 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
511 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
512 vdsc_cfg->initial_offset = rc_params->initial_offset;
513 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
514 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
515 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
516 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
517
518 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
519 vdsc_cfg->rc_range_params[i].range_min_qp =
520 rc_params->rc_range_params[i].range_min_qp;
521 vdsc_cfg->rc_range_params[i].range_max_qp =
522 rc_params->rc_range_params[i].range_max_qp;
523 /*
524 * Range BPG Offset uses 2's complement and is only a 6 bits. So
525 * mask it to get only 6 bits.
526 */
527 vdsc_cfg->rc_range_params[i].range_bpg_offset =
528 rc_params->rc_range_params[i].range_bpg_offset &
529 DSC_RANGE_BPG_OFFSET_MASK;
530 }
531
532 /*
533 * BitsPerComponent value determines mux_word_size:
534 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
535 * 48 bits otherwise 64
536 */
537 if (vdsc_cfg->bits_per_component <= 10)
538 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
539 else
540 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
541
542 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
543 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
544 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
545
546 kfree(rc);
547
548 return 0;
549 }
550
551 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)552 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
553 {
554 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
555 enum pipe pipe = crtc->pipe;
556
557 /*
558 * VDSC/joining uses a separate power well, PW2, and requires
559 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
560 *
561 * - ICL eDP/DSI transcoder
562 * - Display version 12 (except RKL) pipe A
563 *
564 * For any other pipe, VDSC/joining uses the power well associated with
565 * the pipe in use. Hence another reference on the pipe power domain
566 * will suffice. (Except no VDSC/joining on ICL pipe A.)
567 */
568 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
569 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
570 else if (is_pipe_dsc(crtc, cpu_transcoder))
571 return POWER_DOMAIN_PIPE(pipe);
572 else
573 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
574 }
575
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)576 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
577 {
578 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
580 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
581 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
582 enum pipe pipe = crtc->pipe;
583 u32 pps_val = 0;
584 u32 rc_buf_thresh_dword[4];
585 u32 rc_range_params_dword[8];
586 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
587 int i = 0;
588
589 if (crtc_state->bigjoiner_pipes)
590 num_vdsc_instances *= 2;
591
592 /* Populate PICTURE_PARAMETER_SET_0 registers */
593 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
594 DSC_VER_MIN_SHIFT |
595 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
596 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
597 if (vdsc_cfg->dsc_version_minor == 2)
598 pps_val |= DSC_ALT_ICH_SEL;
599 if (vdsc_cfg->block_pred_enable)
600 pps_val |= DSC_BLOCK_PREDICTION;
601 if (vdsc_cfg->convert_rgb)
602 pps_val |= DSC_COLOR_SPACE_CONVERSION;
603 if (vdsc_cfg->simple_422)
604 pps_val |= DSC_422_ENABLE;
605 if (vdsc_cfg->vbr_enable)
606 pps_val |= DSC_VBR_ENABLE;
607 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
608 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
609 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
610 pps_val);
611 /*
612 * If 2 VDSC instances are needed, configure PPS for second
613 * VDSC
614 */
615 if (crtc_state->dsc.dsc_split)
616 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
617 pps_val);
618 } else {
619 intel_de_write(dev_priv,
620 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
621 pps_val);
622 if (crtc_state->dsc.dsc_split)
623 intel_de_write(dev_priv,
624 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
625 pps_val);
626 }
627
628 /* Populate PICTURE_PARAMETER_SET_1 registers */
629 pps_val = 0;
630 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
631 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
632 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
633 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
634 pps_val);
635 /*
636 * If 2 VDSC instances are needed, configure PPS for second
637 * VDSC
638 */
639 if (crtc_state->dsc.dsc_split)
640 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
641 pps_val);
642 } else {
643 intel_de_write(dev_priv,
644 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
645 pps_val);
646 if (crtc_state->dsc.dsc_split)
647 intel_de_write(dev_priv,
648 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
649 pps_val);
650 }
651
652 /* Populate PICTURE_PARAMETER_SET_2 registers */
653 pps_val = 0;
654 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
655 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
656 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
657 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
658 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
659 pps_val);
660 /*
661 * If 2 VDSC instances are needed, configure PPS for second
662 * VDSC
663 */
664 if (crtc_state->dsc.dsc_split)
665 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
666 pps_val);
667 } else {
668 intel_de_write(dev_priv,
669 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
670 pps_val);
671 if (crtc_state->dsc.dsc_split)
672 intel_de_write(dev_priv,
673 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
674 pps_val);
675 }
676
677 /* Populate PICTURE_PARAMETER_SET_3 registers */
678 pps_val = 0;
679 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
680 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
681 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
682 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
683 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
684 pps_val);
685 /*
686 * If 2 VDSC instances are needed, configure PPS for second
687 * VDSC
688 */
689 if (crtc_state->dsc.dsc_split)
690 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
691 pps_val);
692 } else {
693 intel_de_write(dev_priv,
694 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
695 pps_val);
696 if (crtc_state->dsc.dsc_split)
697 intel_de_write(dev_priv,
698 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
699 pps_val);
700 }
701
702 /* Populate PICTURE_PARAMETER_SET_4 registers */
703 pps_val = 0;
704 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
705 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
706 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
707 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
708 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
709 pps_val);
710 /*
711 * If 2 VDSC instances are needed, configure PPS for second
712 * VDSC
713 */
714 if (crtc_state->dsc.dsc_split)
715 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
716 pps_val);
717 } else {
718 intel_de_write(dev_priv,
719 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
720 pps_val);
721 if (crtc_state->dsc.dsc_split)
722 intel_de_write(dev_priv,
723 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
724 pps_val);
725 }
726
727 /* Populate PICTURE_PARAMETER_SET_5 registers */
728 pps_val = 0;
729 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
730 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
731 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
732 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
733 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
734 pps_val);
735 /*
736 * If 2 VDSC instances are needed, configure PPS for second
737 * VDSC
738 */
739 if (crtc_state->dsc.dsc_split)
740 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
741 pps_val);
742 } else {
743 intel_de_write(dev_priv,
744 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
745 pps_val);
746 if (crtc_state->dsc.dsc_split)
747 intel_de_write(dev_priv,
748 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
749 pps_val);
750 }
751
752 /* Populate PICTURE_PARAMETER_SET_6 registers */
753 pps_val = 0;
754 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
755 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
756 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
757 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
758 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
759 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
760 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
761 pps_val);
762 /*
763 * If 2 VDSC instances are needed, configure PPS for second
764 * VDSC
765 */
766 if (crtc_state->dsc.dsc_split)
767 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
768 pps_val);
769 } else {
770 intel_de_write(dev_priv,
771 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
772 pps_val);
773 if (crtc_state->dsc.dsc_split)
774 intel_de_write(dev_priv,
775 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
776 pps_val);
777 }
778
779 /* Populate PICTURE_PARAMETER_SET_7 registers */
780 pps_val = 0;
781 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
782 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
783 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
784 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
785 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
786 pps_val);
787 /*
788 * If 2 VDSC instances are needed, configure PPS for second
789 * VDSC
790 */
791 if (crtc_state->dsc.dsc_split)
792 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
793 pps_val);
794 } else {
795 intel_de_write(dev_priv,
796 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
797 pps_val);
798 if (crtc_state->dsc.dsc_split)
799 intel_de_write(dev_priv,
800 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
801 pps_val);
802 }
803
804 /* Populate PICTURE_PARAMETER_SET_8 registers */
805 pps_val = 0;
806 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
807 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
808 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
809 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
810 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
811 pps_val);
812 /*
813 * If 2 VDSC instances are needed, configure PPS for second
814 * VDSC
815 */
816 if (crtc_state->dsc.dsc_split)
817 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
818 pps_val);
819 } else {
820 intel_de_write(dev_priv,
821 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
822 pps_val);
823 if (crtc_state->dsc.dsc_split)
824 intel_de_write(dev_priv,
825 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
826 pps_val);
827 }
828
829 /* Populate PICTURE_PARAMETER_SET_9 registers */
830 pps_val = 0;
831 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
832 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
833 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
834 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
835 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
836 pps_val);
837 /*
838 * If 2 VDSC instances are needed, configure PPS for second
839 * VDSC
840 */
841 if (crtc_state->dsc.dsc_split)
842 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
843 pps_val);
844 } else {
845 intel_de_write(dev_priv,
846 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
847 pps_val);
848 if (crtc_state->dsc.dsc_split)
849 intel_de_write(dev_priv,
850 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
851 pps_val);
852 }
853
854 /* Populate PICTURE_PARAMETER_SET_10 registers */
855 pps_val = 0;
856 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
857 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
858 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
859 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
860 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
861 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
862 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
863 pps_val);
864 /*
865 * If 2 VDSC instances are needed, configure PPS for second
866 * VDSC
867 */
868 if (crtc_state->dsc.dsc_split)
869 intel_de_write(dev_priv,
870 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
871 } else {
872 intel_de_write(dev_priv,
873 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
874 pps_val);
875 if (crtc_state->dsc.dsc_split)
876 intel_de_write(dev_priv,
877 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
878 pps_val);
879 }
880
881 /* Populate Picture parameter set 16 */
882 pps_val = 0;
883 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
884 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
885 vdsc_cfg->slice_width) |
886 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
887 vdsc_cfg->slice_height);
888 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
889 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
890 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
891 pps_val);
892 /*
893 * If 2 VDSC instances are needed, configure PPS for second
894 * VDSC
895 */
896 if (crtc_state->dsc.dsc_split)
897 intel_de_write(dev_priv,
898 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
899 } else {
900 intel_de_write(dev_priv,
901 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
902 pps_val);
903 if (crtc_state->dsc.dsc_split)
904 intel_de_write(dev_priv,
905 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
906 pps_val);
907 }
908
909 /* Populate the RC_BUF_THRESH registers */
910 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
911 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
912 rc_buf_thresh_dword[i / 4] |=
913 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
914 BITS_PER_BYTE * (i % 4));
915 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
916 rc_buf_thresh_dword[i / 4]);
917 }
918 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
919 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
920 rc_buf_thresh_dword[0]);
921 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
922 rc_buf_thresh_dword[1]);
923 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
924 rc_buf_thresh_dword[2]);
925 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
926 rc_buf_thresh_dword[3]);
927 if (crtc_state->dsc.dsc_split) {
928 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
929 rc_buf_thresh_dword[0]);
930 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
931 rc_buf_thresh_dword[1]);
932 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
933 rc_buf_thresh_dword[2]);
934 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
935 rc_buf_thresh_dword[3]);
936 }
937 } else {
938 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
939 rc_buf_thresh_dword[0]);
940 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
941 rc_buf_thresh_dword[1]);
942 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
943 rc_buf_thresh_dword[2]);
944 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
945 rc_buf_thresh_dword[3]);
946 if (crtc_state->dsc.dsc_split) {
947 intel_de_write(dev_priv,
948 ICL_DSC1_RC_BUF_THRESH_0(pipe),
949 rc_buf_thresh_dword[0]);
950 intel_de_write(dev_priv,
951 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
952 rc_buf_thresh_dword[1]);
953 intel_de_write(dev_priv,
954 ICL_DSC1_RC_BUF_THRESH_1(pipe),
955 rc_buf_thresh_dword[2]);
956 intel_de_write(dev_priv,
957 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
958 rc_buf_thresh_dword[3]);
959 }
960 }
961
962 /* Populate the RC_RANGE_PARAMETERS registers */
963 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
964 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
965 rc_range_params_dword[i / 2] |=
966 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
967 RC_BPG_OFFSET_SHIFT) |
968 (vdsc_cfg->rc_range_params[i].range_max_qp <<
969 RC_MAX_QP_SHIFT) |
970 (vdsc_cfg->rc_range_params[i].range_min_qp <<
971 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
972 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
973 rc_range_params_dword[i / 2]);
974 }
975 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
976 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
977 rc_range_params_dword[0]);
978 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
979 rc_range_params_dword[1]);
980 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
981 rc_range_params_dword[2]);
982 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
983 rc_range_params_dword[3]);
984 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
985 rc_range_params_dword[4]);
986 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
987 rc_range_params_dword[5]);
988 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
989 rc_range_params_dword[6]);
990 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
991 rc_range_params_dword[7]);
992 if (crtc_state->dsc.dsc_split) {
993 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
994 rc_range_params_dword[0]);
995 intel_de_write(dev_priv,
996 DSCC_RC_RANGE_PARAMETERS_0_UDW,
997 rc_range_params_dword[1]);
998 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
999 rc_range_params_dword[2]);
1000 intel_de_write(dev_priv,
1001 DSCC_RC_RANGE_PARAMETERS_1_UDW,
1002 rc_range_params_dword[3]);
1003 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
1004 rc_range_params_dword[4]);
1005 intel_de_write(dev_priv,
1006 DSCC_RC_RANGE_PARAMETERS_2_UDW,
1007 rc_range_params_dword[5]);
1008 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
1009 rc_range_params_dword[6]);
1010 intel_de_write(dev_priv,
1011 DSCC_RC_RANGE_PARAMETERS_3_UDW,
1012 rc_range_params_dword[7]);
1013 }
1014 } else {
1015 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
1016 rc_range_params_dword[0]);
1017 intel_de_write(dev_priv,
1018 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
1019 rc_range_params_dword[1]);
1020 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
1021 rc_range_params_dword[2]);
1022 intel_de_write(dev_priv,
1023 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
1024 rc_range_params_dword[3]);
1025 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
1026 rc_range_params_dword[4]);
1027 intel_de_write(dev_priv,
1028 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
1029 rc_range_params_dword[5]);
1030 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
1031 rc_range_params_dword[6]);
1032 intel_de_write(dev_priv,
1033 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
1034 rc_range_params_dword[7]);
1035 if (crtc_state->dsc.dsc_split) {
1036 intel_de_write(dev_priv,
1037 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
1038 rc_range_params_dword[0]);
1039 intel_de_write(dev_priv,
1040 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
1041 rc_range_params_dword[1]);
1042 intel_de_write(dev_priv,
1043 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
1044 rc_range_params_dword[2]);
1045 intel_de_write(dev_priv,
1046 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
1047 rc_range_params_dword[3]);
1048 intel_de_write(dev_priv,
1049 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
1050 rc_range_params_dword[4]);
1051 intel_de_write(dev_priv,
1052 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
1053 rc_range_params_dword[5]);
1054 intel_de_write(dev_priv,
1055 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
1056 rc_range_params_dword[6]);
1057 intel_de_write(dev_priv,
1058 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
1059 rc_range_params_dword[7]);
1060 }
1061 }
1062 }
1063
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1064 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
1065 const struct intel_crtc_state *crtc_state)
1066 {
1067 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1068 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1069 struct mipi_dsi_device *dsi;
1070 struct drm_dsc_picture_parameter_set pps;
1071 enum port port;
1072
1073 if (!crtc_state->dsc.compression_enable)
1074 return;
1075
1076 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
1077
1078 for_each_dsi_port(port, intel_dsi->ports) {
1079 dsi = intel_dsi->dsi_hosts[port]->device;
1080
1081 mipi_dsi_picture_parameter_set(dsi, &pps);
1082 mipi_dsi_compression_mode(dsi, true);
1083 }
1084 }
1085
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1086 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
1087 const struct intel_crtc_state *crtc_state)
1088 {
1089 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1090 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1091 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1092
1093 if (!crtc_state->dsc.compression_enable)
1094 return;
1095
1096 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1097 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1098
1099 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1100 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1101
1102 dig_port->write_infoframe(encoder, crtc_state,
1103 DP_SDP_PPS, &dp_dsc_pps_sdp,
1104 sizeof(dp_dsc_pps_sdp));
1105 }
1106
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1107 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1108 {
1109 return is_pipe_dsc(crtc, cpu_transcoder) ?
1110 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
1111 }
1112
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)1113 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1114 {
1115 return is_pipe_dsc(crtc, cpu_transcoder) ?
1116 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
1117 }
1118
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)1119 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
1120 {
1121 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1122 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1123 u32 dss_ctl1_val = 0;
1124
1125 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) {
1126 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1127 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
1128 else
1129 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
1130
1131 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1132 }
1133 }
1134
intel_dsc_enable(const struct intel_crtc_state * crtc_state)1135 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
1136 {
1137 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1138 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1139 u32 dss_ctl1_val = 0;
1140 u32 dss_ctl2_val = 0;
1141
1142 if (!crtc_state->dsc.compression_enable)
1143 return;
1144
1145 intel_dsc_pps_configure(crtc_state);
1146
1147 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1148 if (crtc_state->dsc.dsc_split) {
1149 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1150 dss_ctl1_val |= JOINER_ENABLE;
1151 }
1152 if (crtc_state->bigjoiner_pipes) {
1153 dss_ctl1_val |= BIG_JOINER_ENABLE;
1154 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
1155 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1156 }
1157 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1158 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
1159 }
1160
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)1161 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1162 {
1163 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1164 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1165
1166 /* Disable only if either of them is enabled */
1167 if (old_crtc_state->dsc.compression_enable ||
1168 old_crtc_state->bigjoiner_pipes) {
1169 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1170 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1171 }
1172 }
1173
intel_dsc_get_config(struct intel_crtc_state * crtc_state)1174 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1175 {
1176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1177 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1178 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1179 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1180 enum pipe pipe = crtc->pipe;
1181 enum intel_display_power_domain power_domain;
1182 intel_wakeref_t wakeref;
1183 u32 dss_ctl1, dss_ctl2, val;
1184
1185 if (!intel_dsc_source_support(crtc_state))
1186 return;
1187
1188 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1189
1190 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1191 if (!wakeref)
1192 return;
1193
1194 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
1195 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
1196
1197 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1198 if (!crtc_state->dsc.compression_enable)
1199 goto out;
1200
1201 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1202 (dss_ctl1 & JOINER_ENABLE);
1203
1204 /* FIXME: add more state readout as needed */
1205
1206 /* PPS1 */
1207 if (!is_pipe_dsc(crtc, cpu_transcoder))
1208 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1209 else
1210 val = intel_de_read(dev_priv,
1211 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1212 vdsc_cfg->bits_per_pixel = val;
1213 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1214 out:
1215 intel_display_power_put(dev_priv, power_domain, wakeref);
1216 }
1217