1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2017-2019 Intel Corporation
4  */
5 
6 #include "intel_wopcm.h"
7 #include "i915_drv.h"
8 
9 /**
10  * DOC: WOPCM Layout
11  *
12  * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
13  * offset registers whose values are calculated and determined by HuC/GuC
14  * firmware size and set of hardware requirements/restrictions as shown below:
15  *
16  * ::
17  *
18  *    +=========> +====================+ <== WOPCM Top
19  *    ^           |  HW contexts RSVD  |
20  *    |     +===> +====================+ <== GuC WOPCM Top
21  *    |     ^     |                    |
22  *    |     |     |                    |
23  *    |     |     |                    |
24  *    |    GuC    |                    |
25  *    |   WOPCM   |                    |
26  *    |    Size   +--------------------+
27  *  WOPCM   |     |    GuC FW RSVD     |
28  *    |     |     +--------------------+
29  *    |     |     |   GuC Stack RSVD   |
30  *    |     |     +------------------- +
31  *    |     v     |   GuC WOPCM RSVD   |
32  *    |     +===> +====================+ <== GuC WOPCM base
33  *    |           |     WOPCM RSVD     |
34  *    |           +------------------- + <== HuC Firmware Top
35  *    v           |      HuC FW        |
36  *    +=========> +====================+ <== WOPCM Base
37  *
38  * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
39  * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
40  * context).
41  */
42 
43 /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
44 #define GEN11_WOPCM_SIZE		SZ_2M
45 #define GEN9_WOPCM_SIZE			SZ_1M
46 #define MAX_WOPCM_SIZE			SZ_8M
47 /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
48 #define WOPCM_RESERVED_SIZE		SZ_16K
49 
50 /* 16KB reserved at the beginning of GuC WOPCM. */
51 #define GUC_WOPCM_RESERVED		SZ_16K
52 /* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
53 #define GUC_WOPCM_STACK_RESERVED	SZ_8K
54 
55 /* GuC WOPCM Offset value needs to be aligned to 16KB. */
56 #define GUC_WOPCM_OFFSET_ALIGNMENT	(1UL << GUC_WOPCM_OFFSET_SHIFT)
57 
58 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
59 #define BXT_WOPCM_RC6_CTX_RESERVED	(SZ_16K + SZ_8K)
60 /* 36KB WOPCM reserved at the end of WOPCM on ICL. */
61 #define ICL_WOPCM_HW_CTX_RESERVED	(SZ_32K + SZ_4K)
62 
63 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
64 #define GEN9_GUC_FW_RESERVED	SZ_128K
65 #define GEN9_GUC_WOPCM_OFFSET	(GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
66 
wopcm_to_gt(struct intel_wopcm * wopcm)67 static inline struct intel_gt *wopcm_to_gt(struct intel_wopcm *wopcm)
68 {
69 	return container_of(wopcm, struct intel_gt, wopcm);
70 }
71 
72 /**
73  * intel_wopcm_init_early() - Early initialization of the WOPCM.
74  * @wopcm: pointer to intel_wopcm.
75  *
76  * Setup the size of WOPCM which will be used by later on WOPCM partitioning.
77  */
intel_wopcm_init_early(struct intel_wopcm * wopcm)78 void intel_wopcm_init_early(struct intel_wopcm *wopcm)
79 {
80 	struct intel_gt *gt = wopcm_to_gt(wopcm);
81 	struct drm_i915_private *i915 = gt->i915;
82 
83 	if (!HAS_GT_UC(i915))
84 		return;
85 
86 	if (GRAPHICS_VER(i915) >= 11)
87 		wopcm->size = GEN11_WOPCM_SIZE;
88 	else
89 		wopcm->size = GEN9_WOPCM_SIZE;
90 
91 	drm_dbg(&i915->drm, "WOPCM: %uK\n", wopcm->size / 1024);
92 }
93 
context_reserved_size(struct drm_i915_private * i915)94 static u32 context_reserved_size(struct drm_i915_private *i915)
95 {
96 	if (IS_GEN9_LP(i915))
97 		return BXT_WOPCM_RC6_CTX_RESERVED;
98 	else if (GRAPHICS_VER(i915) >= 11)
99 		return ICL_WOPCM_HW_CTX_RESERVED;
100 	else
101 		return 0;
102 }
103 
gen9_check_dword_gap(struct drm_i915_private * i915,u32 guc_wopcm_base,u32 guc_wopcm_size)104 static bool gen9_check_dword_gap(struct drm_i915_private *i915,
105 				 u32 guc_wopcm_base, u32 guc_wopcm_size)
106 {
107 	u32 offset;
108 
109 	/*
110 	 * GuC WOPCM size shall be at least a dword larger than the offset from
111 	 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
112 	 * due to hardware limitation on Gen9.
113 	 */
114 	offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
115 	if (offset > guc_wopcm_size ||
116 	    (guc_wopcm_size - offset) < sizeof(u32)) {
117 		drm_err(&i915->drm,
118 			"WOPCM: invalid GuC region size: %uK < %uK\n",
119 			guc_wopcm_size / SZ_1K,
120 			(u32)(offset + sizeof(u32)) / SZ_1K);
121 		return false;
122 	}
123 
124 	return true;
125 }
126 
gen9_check_huc_fw_fits(struct drm_i915_private * i915,u32 guc_wopcm_size,u32 huc_fw_size)127 static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
128 				   u32 guc_wopcm_size, u32 huc_fw_size)
129 {
130 	/*
131 	 * On Gen9, hardware requires the total available GuC WOPCM
132 	 * size to be larger than or equal to HuC firmware size. Otherwise,
133 	 * firmware uploading would fail.
134 	 */
135 	if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
136 		drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
137 			intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
138 			(guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K,
139 			huc_fw_size / 1024);
140 		return false;
141 	}
142 
143 	return true;
144 }
145 
check_hw_restrictions(struct drm_i915_private * i915,u32 guc_wopcm_base,u32 guc_wopcm_size,u32 huc_fw_size)146 static bool check_hw_restrictions(struct drm_i915_private *i915,
147 				  u32 guc_wopcm_base, u32 guc_wopcm_size,
148 				  u32 huc_fw_size)
149 {
150 	if (GRAPHICS_VER(i915) == 9 && !gen9_check_dword_gap(i915, guc_wopcm_base,
151 							     guc_wopcm_size))
152 		return false;
153 
154 	if (GRAPHICS_VER(i915) == 9 &&
155 	    !gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size))
156 		return false;
157 
158 	return true;
159 }
160 
__check_layout(struct intel_gt * gt,u32 wopcm_size,u32 guc_wopcm_base,u32 guc_wopcm_size,u32 guc_fw_size,u32 huc_fw_size)161 static bool __check_layout(struct intel_gt *gt, u32 wopcm_size,
162 			   u32 guc_wopcm_base, u32 guc_wopcm_size,
163 			   u32 guc_fw_size, u32 huc_fw_size)
164 {
165 	struct drm_i915_private *i915 = gt->i915;
166 	const u32 ctx_rsvd = context_reserved_size(i915);
167 	u32 size;
168 
169 	size = wopcm_size - ctx_rsvd;
170 	if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {
171 		drm_err(&i915->drm,
172 			"WOPCM: invalid GuC region layout: %uK + %uK > %uK\n",
173 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
174 			size / SZ_1K);
175 		return false;
176 	}
177 
178 	size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
179 	if (unlikely(guc_wopcm_size < size)) {
180 		drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
181 			intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC),
182 			guc_wopcm_size / SZ_1K, size / SZ_1K);
183 		return false;
184 	}
185 
186 	if (intel_uc_supports_huc(&gt->uc)) {
187 		size = huc_fw_size + WOPCM_RESERVED_SIZE;
188 		if (unlikely(guc_wopcm_base < size)) {
189 			drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
190 				intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
191 				guc_wopcm_base / SZ_1K, size / SZ_1K);
192 			return false;
193 		}
194 	}
195 
196 	return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,
197 				     huc_fw_size);
198 }
199 
__wopcm_regs_locked(struct intel_uncore * uncore,u32 * guc_wopcm_base,u32 * guc_wopcm_size)200 static bool __wopcm_regs_locked(struct intel_uncore *uncore,
201 				u32 *guc_wopcm_base, u32 *guc_wopcm_size)
202 {
203 	u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET);
204 	u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE);
205 
206 	if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
207 	    !(reg_base & GUC_WOPCM_OFFSET_VALID))
208 		return false;
209 
210 	*guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
211 	*guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK;
212 	return true;
213 }
214 
__wopcm_regs_writable(struct intel_uncore * uncore)215 static bool __wopcm_regs_writable(struct intel_uncore *uncore)
216 {
217 	if (!HAS_GUC_DEPRIVILEGE(uncore->i915))
218 		return true;
219 
220 	return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED;
221 }
222 
223 /**
224  * intel_wopcm_init() - Initialize the WOPCM structure.
225  * @wopcm: pointer to intel_wopcm.
226  *
227  * This function will partition WOPCM space based on GuC and HuC firmware sizes
228  * and will allocate max remaining for use by GuC. This function will also
229  * enforce platform dependent hardware restrictions on GuC WOPCM offset and
230  * size. It will fail the WOPCM init if any of these checks fail, so that the
231  * following WOPCM registers setup and GuC firmware uploading would be aborted.
232  */
intel_wopcm_init(struct intel_wopcm * wopcm)233 void intel_wopcm_init(struct intel_wopcm *wopcm)
234 {
235 	struct intel_gt *gt = wopcm_to_gt(wopcm);
236 	struct drm_i915_private *i915 = gt->i915;
237 	u32 guc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.guc.fw);
238 	u32 huc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.huc.fw);
239 	u32 ctx_rsvd = context_reserved_size(i915);
240 	u32 wopcm_size = wopcm->size;
241 	u32 guc_wopcm_base;
242 	u32 guc_wopcm_size;
243 
244 	if (!guc_fw_size)
245 		return;
246 
247 	GEM_BUG_ON(!wopcm_size);
248 	GEM_BUG_ON(wopcm->guc.base);
249 	GEM_BUG_ON(wopcm->guc.size);
250 	GEM_BUG_ON(guc_fw_size >= wopcm_size);
251 	GEM_BUG_ON(huc_fw_size >= wopcm_size);
252 	GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm_size);
253 
254 	if (i915_inject_probe_failure(i915))
255 		return;
256 
257 	if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {
258 		drm_dbg(&i915->drm, "GuC WOPCM is already locked [%uK, %uK)\n",
259 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
260 		/*
261 		 * Note that to keep things simple (i.e. avoid different
262 		 * defines per platform) our WOPCM math doesn't always use the
263 		 * actual WOPCM size, but a value that is less or equal to it.
264 		 * This is perfectly fine when i915 programs the registers, but
265 		 * on platforms with GuC deprivilege the registers are not
266 		 * writable from i915 and are instead pre-programmed by the
267 		 * bios/IFWI, so there might be a mismatch of sizes.
268 		 * Instead of handling the size difference, we trust that the
269 		 * programmed values make sense and disable the relevant check
270 		 * by using the maximum possible WOPCM size in the verification
271 		 * math. In the extremely unlikely case that the registers
272 		 * were pre-programmed with an invalid value, we will still
273 		 * gracefully fail later during the GuC/HuC dma.
274 		 */
275 		if (!__wopcm_regs_writable(gt->uncore))
276 			wopcm_size = MAX_WOPCM_SIZE;
277 
278 		goto check;
279 	}
280 
281 	/*
282 	 * On platforms with a media GT, the WOPCM is partitioned between the
283 	 * two GTs, so we would have to take that into account when doing the
284 	 * math below. There is also a new section reserved for the GSC context
285 	 * that would have to be factored in. However, all platforms with a
286 	 * media GT also have GuC depriv enabled, so the WOPCM regs are
287 	 * pre-locked and therefore we don't have to do the math ourselves.
288 	 */
289 	if (unlikely(i915->media_gt)) {
290 		drm_err(&i915->drm, "Unlocked WOPCM regs with media GT\n");
291 		return;
292 	}
293 
294 	/*
295 	 * Aligned value of guc_wopcm_base will determine available WOPCM space
296 	 * for HuC firmware and mandatory reserved area.
297 	 */
298 	guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;
299 	guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);
300 
301 	/*
302 	 * Need to clamp guc_wopcm_base now to make sure the following math is
303 	 * correct. Formal check of whole WOPCM layout will be done below.
304 	 */
305 	guc_wopcm_base = min(guc_wopcm_base, wopcm_size - ctx_rsvd);
306 
307 	/* Aligned remainings of usable WOPCM space can be assigned to GuC. */
308 	guc_wopcm_size = wopcm_size - ctx_rsvd - guc_wopcm_base;
309 	guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
310 
311 	drm_dbg(&i915->drm, "Calculated GuC WOPCM [%uK, %uK)\n",
312 		guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
313 
314 check:
315 	if (__check_layout(gt, wopcm_size, guc_wopcm_base, guc_wopcm_size,
316 			   guc_fw_size, huc_fw_size)) {
317 		wopcm->guc.base = guc_wopcm_base;
318 		wopcm->guc.size = guc_wopcm_size;
319 		GEM_BUG_ON(!wopcm->guc.base);
320 		GEM_BUG_ON(!wopcm->guc.size);
321 	}
322 }
323