1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2023 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 #include "reg.h" 14 15 struct ipa; 16 17 /** 18 * DOC: IPA Registers 19 * 20 * IPA registers are located within the "ipa-reg" address space defined by 21 * Device Tree. Each register has a specified offset within that space, 22 * which is mapped into virtual memory space in ipa_mem_init(). Each 23 * has a unique identifer, taken from the ipa_reg_id enumerated type. 24 * All IPA registers are 32 bits wide. 25 * 26 * Certain "parameterized" register types are duplicated for a number of 27 * instances of something. For example, each IPA endpoint has an set of 28 * registers defining its configuration. The offset to an endpoint's set 29 * of registers is computed based on an "base" offset, plus an endpoint's 30 * ID multiplied and a "stride" value for the register. Similarly, some 31 * registers have an offset that depends on execution environment. In 32 * this case, the stride is multiplied by a member of the gsi_ee_id 33 * enumerated type. 34 * 35 * Each version of IPA implements an array of ipa_reg structures indexed 36 * by register ID. Each entry in the array specifies the base offset and 37 * (for parameterized registers) a non-zero stride value. Not all versions 38 * of IPA define all registers. The offset for a register is returned by 39 * reg_offset() when the register's ipa_reg structure is supplied; 40 * zero is returned for an undefined register (this should never happen). 41 * 42 * Some registers encode multiple fields within them. Each field in 43 * such a register has a unique identifier (from an enumerated type). 44 * The position and width of the fields in a register are defined by 45 * an array of field masks, indexed by field ID. Two functions are 46 * used to access register fields; both take an ipa_reg structure as 47 * argument. To encode a value to be represented in a register field, 48 * the value and field ID are passed to reg_encode(). To extract 49 * a value encoded in a register field, the field ID is passed to 50 * reg_decode(). In addition, for single-bit fields, reg_bit() 51 * can be used to either encode the bit value, or to generate a mask 52 * used to extract the bit value. 53 */ 54 55 /* enum ipa_reg_id - IPA register IDs */ 56 enum ipa_reg_id { 57 COMP_CFG, 58 CLKON_CFG, 59 ROUTE, 60 SHARED_MEM_SIZE, 61 QSB_MAX_WRITES, 62 QSB_MAX_READS, 63 FILT_ROUT_HASH_EN, /* Not IPA v5.0+ */ 64 FILT_ROUT_CACHE_CFG, /* IPA v5.0+ */ 65 FILT_ROUT_HASH_FLUSH, /* Not IPA v5.0+ */ 66 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ 67 STATE_AGGR_ACTIVE, 68 IPA_BCR, /* Not IPA v4.5+ */ 69 LOCAL_PKT_PROC_CNTXT, 70 AGGR_FORCE_CLOSE, 71 COUNTER_CFG, /* Not IPA v4.5+ */ 72 IPA_TX_CFG, /* IPA v3.5+ */ 73 FLAVOR_0, /* IPA v3.5+ */ 74 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 75 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 76 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 77 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 78 SRC_RSRC_GRP_01_RSRC_TYPE, 79 SRC_RSRC_GRP_23_RSRC_TYPE, 80 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 81 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 82 DST_RSRC_GRP_01_RSRC_TYPE, 83 DST_RSRC_GRP_23_RSRC_TYPE, 84 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 85 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 86 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 87 ENDP_INIT_CFG, 88 ENDP_INIT_NAT, /* TX only */ 89 ENDP_INIT_HDR, 90 ENDP_INIT_HDR_EXT, 91 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 92 ENDP_INIT_MODE, /* TX only */ 93 ENDP_INIT_AGGR, 94 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 95 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 96 ENDP_INIT_DEAGGR, /* TX only */ 97 ENDP_INIT_RSRC_GRP, 98 ENDP_INIT_SEQ, /* TX only */ 99 ENDP_STATUS, 100 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 101 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ 102 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ 103 /* The IRQ registers that follow are only used for GSI_EE_AP */ 104 IPA_IRQ_STTS, 105 IPA_IRQ_EN, 106 IPA_IRQ_CLR, 107 IPA_IRQ_UC, 108 IRQ_SUSPEND_INFO, 109 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 110 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 111 IPA_REG_ID_COUNT, /* Last; not an ID */ 112 }; 113 114 /* COMP_CFG register */ 115 enum ipa_reg_comp_cfg_field_id { 116 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 117 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 118 GSI_SNOC_BYPASS_DIS, 119 GEN_QMB_0_SNOC_BYPASS_DIS, 120 GEN_QMB_1_SNOC_BYPASS_DIS, 121 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 122 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 123 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 124 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 125 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 126 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 127 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 128 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 129 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 130 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 131 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 132 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 133 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 134 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 135 GENQMB_AOOOWR, /* IPA v4.9+ */ 136 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 137 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 138 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 139 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 140 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 141 }; 142 143 /* CLKON_CFG register */ 144 enum ipa_reg_clkon_cfg_field_id { 145 CLKON_RX, 146 CLKON_PROC, 147 TX_WRAPPER, 148 CLKON_MISC, 149 RAM_ARB, 150 FTCH_HPS, 151 FTCH_DPS, 152 CLKON_HPS, 153 CLKON_DPS, 154 RX_HPS_CMDQS, 155 HPS_DPS_CMDQS, 156 DPS_TX_CMDQS, 157 RSRC_MNGR, 158 CTX_HANDLER, 159 ACK_MNGR, 160 D_DCPH, 161 H_DCPH, 162 CLKON_DCMP, /* IPA v4.5+ */ 163 NTF_TX_CMDQS, /* IPA v3.5+ */ 164 CLKON_TX_0, /* IPA v3.5+ */ 165 CLKON_TX_1, /* IPA v3.5+ */ 166 CLKON_FNR, /* IPA v3.5.1+ */ 167 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 168 AGGR_WRAPPER, /* IPA v4.0+ */ 169 RAM_SLAVEWAY, /* IPA v4.0+ */ 170 CLKON_QMB, /* IPA v4.0+ */ 171 WEIGHT_ARB, /* IPA v4.0+ */ 172 GSI_IF, /* IPA v4.0+ */ 173 CLKON_GLOBAL, /* IPA v4.0+ */ 174 GLOBAL_2X_CLK, /* IPA v4.0+ */ 175 DPL_FIFO, /* IPA v4.5+ */ 176 DRBIP, /* IPA v4.7+ */ 177 }; 178 179 /* ROUTE register */ 180 enum ipa_reg_route_field_id { 181 ROUTE_DIS, 182 ROUTE_DEF_PIPE, 183 ROUTE_DEF_HDR_TABLE, 184 ROUTE_DEF_HDR_OFST, 185 ROUTE_FRAG_DEF_PIPE, 186 ROUTE_DEF_RETAIN_HDR, 187 }; 188 189 /* SHARED_MEM_SIZE register */ 190 enum ipa_reg_shared_mem_size_field_id { 191 MEM_SIZE, 192 MEM_BADDR, 193 }; 194 195 /* QSB_MAX_WRITES register */ 196 enum ipa_reg_qsb_max_writes_field_id { 197 GEN_QMB_0_MAX_WRITES, 198 GEN_QMB_1_MAX_WRITES, 199 }; 200 201 /* QSB_MAX_READS register */ 202 enum ipa_reg_qsb_max_reads_field_id { 203 GEN_QMB_0_MAX_READS, 204 GEN_QMB_1_MAX_READS, 205 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 206 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 207 }; 208 209 /* FILT_ROUT_CACHE_CFG register */ 210 enum ipa_reg_filt_rout_cache_cfg_field_id { 211 ROUTER_CACHE_EN, 212 FILTER_CACHE_EN, 213 LOW_PRI_HASH_HIT_DISABLE, 214 LRU_EVICTION_THRESHOLD, 215 }; 216 217 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 218 enum ipa_reg_filt_rout_hash_field_id { 219 IPV6_ROUTER_HASH, 220 IPV6_FILTER_HASH, 221 IPV4_ROUTER_HASH, 222 IPV4_FILTER_HASH, 223 }; 224 225 /* FILT_ROUT_CACHE_FLUSH register */ 226 enum ipa_reg_filt_rout_cache_field_id { 227 ROUTER_CACHE, 228 FILTER_CACHE, 229 }; 230 231 /* BCR register */ 232 enum ipa_bcr_compat { 233 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 234 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 235 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 236 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 237 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 238 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 239 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 240 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 241 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 242 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 243 }; 244 245 /* LOCAL_PKT_PROC_CNTXT register */ 246 enum ipa_reg_local_pkt_proc_cntxt_field_id { 247 IPA_BASE_ADDR, 248 }; 249 250 /* COUNTER_CFG register */ 251 enum ipa_reg_counter_cfg_field_id { 252 EOT_COAL_GRANULARITY, /* Not v3.5+ */ 253 AGGR_GRANULARITY, 254 }; 255 256 /* IPA_TX_CFG register */ 257 enum ipa_reg_ipa_tx_cfg_field_id { 258 TX0_PREFETCH_DISABLE, /* Not v4.0+ */ 259 TX1_PREFETCH_DISABLE, /* Not v4.0+ */ 260 PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ 261 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ 262 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ 263 DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ 264 DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ 265 PA_MASK_EN, /* v4.0+ */ 266 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ 267 DUAL_TX_ENABLE, /* v4.5+ */ 268 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ 269 SSPND_PA_NO_BQ_STATE, /* v4.2 only */ 270 HOLB_STICKY_DROP_EN, /* v5.0+ */ 271 }; 272 273 /* FLAVOR_0 register */ 274 enum ipa_reg_flavor_0_field_id { 275 MAX_PIPES, 276 MAX_CONS_PIPES, 277 MAX_PROD_PIPES, 278 PROD_LOWEST, 279 }; 280 281 /* IDLE_INDICATION_CFG register */ 282 enum ipa_reg_idle_indication_cfg_field_id { 283 ENTER_IDLE_DEBOUNCE_THRESH, 284 CONST_NON_IDLE_ENABLE, 285 }; 286 287 /* QTIME_TIMESTAMP_CFG register */ 288 enum ipa_reg_qtime_timestamp_cfg_field_id { 289 DPL_TIMESTAMP_LSB, 290 DPL_TIMESTAMP_SEL, 291 TAG_TIMESTAMP_LSB, 292 NAT_TIMESTAMP_LSB, 293 }; 294 295 /* TIMERS_XO_CLK_DIV_CFG register */ 296 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 297 DIV_VALUE, 298 DIV_ENABLE, 299 }; 300 301 /* TIMERS_PULSE_GRAN_CFG register */ 302 enum ipa_reg_timers_pulse_gran_cfg_field_id { 303 PULSE_GRAN_0, 304 PULSE_GRAN_1, 305 PULSE_GRAN_2, 306 PULSE_GRAN_3, 307 }; 308 309 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 310 enum ipa_pulse_gran { 311 IPA_GRAN_10_US = 0x0, 312 IPA_GRAN_20_US = 0x1, 313 IPA_GRAN_50_US = 0x2, 314 IPA_GRAN_100_US = 0x3, 315 IPA_GRAN_1_MS = 0x4, 316 IPA_GRAN_10_MS = 0x5, 317 IPA_GRAN_100_MS = 0x6, 318 IPA_GRAN_655350_US = 0x7, 319 }; 320 321 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 322 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 323 X_MIN_LIM, 324 X_MAX_LIM, 325 Y_MIN_LIM, 326 Y_MAX_LIM, 327 }; 328 329 /* ENDP_INIT_CTRL register */ 330 enum ipa_reg_endp_init_ctrl_field_id { 331 ENDP_SUSPEND, /* Not v4.0+ */ 332 ENDP_DELAY, /* Not v4.2+ */ 333 }; 334 335 /* ENDP_INIT_CFG register */ 336 enum ipa_reg_endp_init_cfg_field_id { 337 FRAG_OFFLOAD_EN, 338 CS_OFFLOAD_EN, 339 CS_METADATA_HDR_OFFSET, 340 CS_GEN_QMB_MASTER_SEL, 341 }; 342 343 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 344 enum ipa_cs_offload_en { 345 IPA_CS_OFFLOAD_NONE = 0x0, 346 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 347 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 348 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 349 }; 350 351 /* ENDP_INIT_NAT register */ 352 enum ipa_reg_endp_init_nat_field_id { 353 NAT_EN, 354 }; 355 356 /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ 357 enum ipa_nat_type { 358 IPA_NAT_TYPE_BYPASS = 0, 359 IPA_NAT_TYPE_SRC = 1, 360 IPA_NAT_TYPE_DST = 2, 361 }; 362 363 /* ENDP_INIT_HDR register */ 364 enum ipa_reg_endp_init_hdr_field_id { 365 HDR_LEN, 366 HDR_OFST_METADATA_VALID, 367 HDR_OFST_METADATA, 368 HDR_ADDITIONAL_CONST_LEN, 369 HDR_OFST_PKT_SIZE_VALID, 370 HDR_OFST_PKT_SIZE, 371 HDR_A5_MUX, /* Not v4.9+ */ 372 HDR_LEN_INC_DEAGG_HDR, 373 HDR_METADATA_REG_VALID, /* Not v4.5+ */ 374 HDR_LEN_MSB, /* v4.5+ */ 375 HDR_OFST_METADATA_MSB, /* v4.5+ */ 376 }; 377 378 /* ENDP_INIT_HDR_EXT register */ 379 enum ipa_reg_endp_init_hdr_ext_field_id { 380 HDR_ENDIANNESS, 381 HDR_TOTAL_LEN_OR_PAD_VALID, 382 HDR_TOTAL_LEN_OR_PAD, 383 HDR_PAYLOAD_LEN_INC_PADDING, 384 HDR_TOTAL_LEN_OR_PAD_OFFSET, 385 HDR_PAD_TO_ALIGNMENT, 386 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ 387 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ 388 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ 389 HDR_BYTES_TO_REMOVE_VALID, /* v5.0+ */ 390 HDR_BYTES_TO_REMOVE, /* v5.0+ */ 391 }; 392 393 /* ENDP_INIT_MODE register */ 394 enum ipa_reg_endp_init_mode_field_id { 395 ENDP_MODE, 396 DCPH_ENABLE, /* v4.5+ */ 397 DEST_PIPE_INDEX, 398 BYTE_THRESHOLD, 399 PIPE_REPLICATION_EN, 400 PAD_EN, 401 HDR_FTCH_DISABLE, /* v4.5+ */ 402 DRBIP_ACL_ENABLE, /* v4.9+ */ 403 }; 404 405 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 406 enum ipa_mode { 407 IPA_BASIC = 0x0, 408 IPA_ENABLE_FRAMING_HDLC = 0x1, 409 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 410 IPA_DMA = 0x3, 411 }; 412 413 /* ENDP_INIT_AGGR register */ 414 enum ipa_reg_endp_init_aggr_field_id { 415 AGGR_EN, 416 AGGR_TYPE, 417 BYTE_LIMIT, 418 TIME_LIMIT, 419 PKT_LIMIT, 420 SW_EOF_ACTIVE, 421 FORCE_CLOSE, 422 HARD_BYTE_LIMIT_EN, 423 AGGR_GRAN_SEL, 424 }; 425 426 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 427 enum ipa_aggr_en { 428 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 429 IPA_ENABLE_AGGR /* RX */ = 0x1, 430 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 431 }; 432 433 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 434 enum ipa_aggr_type { 435 IPA_MBIM_16 = 0x0, 436 IPA_HDLC = 0x1, 437 IPA_TLP = 0x2, 438 IPA_RNDIS = 0x3, 439 IPA_GENERIC = 0x4, 440 IPA_COALESCE = 0x5, 441 IPA_QCMAP = 0x6, 442 }; 443 444 /* ENDP_INIT_HOL_BLOCK_EN register */ 445 enum ipa_reg_endp_init_hol_block_en_field_id { 446 HOL_BLOCK_EN, 447 }; 448 449 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 450 enum ipa_reg_endp_init_hol_block_timer_field_id { 451 TIMER_BASE_VALUE, /* Not v4.5+ */ 452 TIMER_SCALE, /* v4.2 only */ 453 TIMER_LIMIT, /* v4.5+ */ 454 TIMER_GRAN_SEL, /* v4.5+ */ 455 }; 456 457 /* ENDP_INIT_DEAGGR register */ 458 enum ipa_reg_endp_deaggr_field_id { 459 DEAGGR_HDR_LEN, 460 SYSPIPE_ERR_DETECTION, 461 PACKET_OFFSET_VALID, 462 PACKET_OFFSET_LOCATION, 463 IGNORE_MIN_PKT_ERR, 464 MAX_PACKET_LEN, 465 }; 466 467 /* ENDP_INIT_RSRC_GRP register */ 468 enum ipa_reg_endp_init_rsrc_grp_field_id { 469 ENDP_RSRC_GRP, 470 }; 471 472 /* ENDP_INIT_SEQ register */ 473 enum ipa_reg_endp_init_seq_field_id { 474 SEQ_TYPE, 475 SEQ_REP_TYPE, /* Not v4.5+ */ 476 }; 477 478 /** 479 * enum ipa_seq_type - HPS and DPS sequencer type 480 * @IPA_SEQ_DMA: Perform DMA only 481 * @IPA_SEQ_1_PASS: One pass through the pipeline 482 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 483 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 484 * @IPA_SEQ_2_PASS: Two passes through the pipeline 485 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 486 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 487 * 488 * The low-order byte of the sequencer type register defines the number of 489 * passes a packet takes through the IPA pipeline. The last pass through can 490 * optionally skip the microprocessor. Deciphering is optional for all types; 491 * if enabled, an additional mask (two bits) is added to the type value. 492 * 493 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 494 * supported (or meaningful). 495 */ 496 enum ipa_seq_type { 497 IPA_SEQ_DMA = 0x00, 498 IPA_SEQ_1_PASS = 0x02, 499 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 500 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 501 IPA_SEQ_2_PASS = 0x0a, 502 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 503 /* The next value can be ORed with the above */ 504 IPA_SEQ_DECIPHER = 0x11, 505 }; 506 507 /** 508 * enum ipa_seq_rep_type - replicated packet sequencer type 509 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 510 * 511 * This goes in the second byte of the endpoint sequencer type register. 512 * 513 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 514 * supported (or meaningful). 515 */ 516 enum ipa_seq_rep_type { 517 IPA_SEQ_REP_DMA_PARSER = 0x08, 518 }; 519 520 /* ENDP_STATUS register */ 521 enum ipa_reg_endp_status_field_id { 522 STATUS_EN, 523 STATUS_ENDP, 524 STATUS_LOCATION, /* Not v4.5+ */ 525 STATUS_PKT_SUPPRESS, /* v4.0+ */ 526 }; 527 528 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 529 enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 530 FILTER_HASH_MSK_SRC_ID, 531 FILTER_HASH_MSK_SRC_IP, 532 FILTER_HASH_MSK_DST_IP, 533 FILTER_HASH_MSK_SRC_PORT, 534 FILTER_HASH_MSK_DST_PORT, 535 FILTER_HASH_MSK_PROTOCOL, 536 FILTER_HASH_MSK_METADATA, 537 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 538 539 ROUTER_HASH_MSK_SRC_ID, 540 ROUTER_HASH_MSK_SRC_IP, 541 ROUTER_HASH_MSK_DST_IP, 542 ROUTER_HASH_MSK_SRC_PORT, 543 ROUTER_HASH_MSK_DST_PORT, 544 ROUTER_HASH_MSK_PROTOCOL, 545 ROUTER_HASH_MSK_METADATA, 546 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 547 }; 548 549 /* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ 550 enum ipa_reg_endp_cache_cfg_field_id { 551 CACHE_MSK_SRC_ID, 552 CACHE_MSK_SRC_IP, 553 CACHE_MSK_DST_IP, 554 CACHE_MSK_SRC_PORT, 555 CACHE_MSK_DST_PORT, 556 CACHE_MSK_PROTOCOL, 557 CACHE_MSK_METADATA, 558 }; 559 560 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 561 /** 562 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 563 * @IPA_IRQ_UC_0: Microcontroller event interrupt 564 * @IPA_IRQ_UC_1: Microcontroller response interrupt 565 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 566 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 567 * 568 * IRQ types not described above are not currently used. 569 * 570 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 571 * @IPA_IRQ_EOT_COAL: (Not currently used) 572 * @IPA_IRQ_UC_2: (Not currently used) 573 * @IPA_IRQ_UC_3: (Not currently used) 574 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 575 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 576 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 577 * @IPA_IRQ_RX_ERR: (Not currently used) 578 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 579 * @IPA_IRQ_TX_ERR: (Not currently used) 580 * @IPA_IRQ_STEP_MODE: (Not currently used) 581 * @IPA_IRQ_PROC_ERR: (Not currently used) 582 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 583 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 584 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 585 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 586 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 587 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 588 * @IPA_IRQ_UCP: (Not currently used) 589 * @IPA_IRQ_DCMP: (Not currently used) 590 * @IPA_IRQ_GSI_EE: (Not currently used) 591 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 592 * @IPA_IRQ_GSI_UC: (Not currently used) 593 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 594 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 595 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 596 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 597 */ 598 enum ipa_irq_id { 599 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 600 /* The next bit is not present for IPA v3.5+ */ 601 IPA_IRQ_EOT_COAL = 0x1, 602 IPA_IRQ_UC_0 = 0x2, 603 IPA_IRQ_UC_1 = 0x3, 604 IPA_IRQ_UC_2 = 0x4, 605 IPA_IRQ_UC_3 = 0x5, 606 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 607 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 608 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 609 IPA_IRQ_RX_ERR = 0x9, 610 IPA_IRQ_DEAGGR_ERR = 0xa, 611 IPA_IRQ_TX_ERR = 0xb, 612 IPA_IRQ_STEP_MODE = 0xc, 613 IPA_IRQ_PROC_ERR = 0xd, 614 IPA_IRQ_TX_SUSPEND = 0xe, 615 IPA_IRQ_TX_HOLB_DROP = 0xf, 616 IPA_IRQ_BAM_GSI_IDLE = 0x10, 617 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 618 IPA_IRQ_PIPE_RED_BELOW = 0x12, 619 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 620 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 621 IPA_IRQ_UCP = 0x15, 622 /* The next bit is not present for IPA v4.5+ */ 623 IPA_IRQ_DCMP = 0x16, 624 IPA_IRQ_GSI_EE = 0x17, 625 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 626 IPA_IRQ_GSI_UC = 0x19, 627 /* The next bit is present for IPA v4.5+ */ 628 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 629 /* The next three bits are present for IPA v4.9+ */ 630 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 631 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 632 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 633 IPA_IRQ_COUNT, /* Last; not an id */ 634 }; 635 636 /* IPA_IRQ_UC register */ 637 enum ipa_reg_ipa_irq_uc_field_id { 638 UC_INTR, 639 }; 640 641 extern const struct regs ipa_regs_v3_1; 642 extern const struct regs ipa_regs_v3_5_1; 643 extern const struct regs ipa_regs_v4_2; 644 extern const struct regs ipa_regs_v4_5; 645 extern const struct regs ipa_regs_v4_7; 646 extern const struct regs ipa_regs_v4_9; 647 extern const struct regs ipa_regs_v4_11; 648 649 const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 650 651 int ipa_reg_init(struct ipa *ipa); 652 void ipa_reg_exit(struct ipa *ipa); 653 654 #endif /* _IPA_REG_H_ */ 655