1 /*
2  * Copyright (c) 2022 Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier:    BSD-3-Clause
5  *
6  * DRTM service
7  *
8  * Authors:
9  *	Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
10  *	Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01
11  *
12  */
13 
14 #ifndef ARM_DRTM_SVC_H
15 #define ARM_DRTM_SVC_H
16 
17 /*
18  * SMC function IDs for DRTM Service
19  * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4)
20  */
21 #define DRTM_FID(func_num)				\
22 	((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) |		\
23 	(SMC_64 << FUNCID_CC_SHIFT) |			\
24 	(OEN_STD_START << FUNCID_OEN_SHIFT) |		\
25 	((func_num) << FUNCID_NUM_SHIFT))
26 
27 #define DRTM_FNUM_SVC_VERSION		U(0x110)
28 #define DRTM_FNUM_SVC_FEATURES		U(0x111)
29 #define DRTM_FNUM_SVC_UNPROTECT_MEM	U(0x113)
30 #define DRTM_FNUM_SVC_DYNAMIC_LAUNCH	U(0x114)
31 #define DRTM_FNUM_SVC_CLOSE_LOCALITY	U(0x115)
32 #define DRTM_FNUM_SVC_GET_ERROR		U(0x116)
33 #define DRTM_FNUM_SVC_SET_ERROR		U(0x117)
34 #define DRTM_FNUM_SVC_SET_TCB_HASH	U(0x118)
35 #define DRTM_FNUM_SVC_LOCK_TCB_HASH	U(0x119)
36 
37 #define ARM_DRTM_SVC_VERSION		DRTM_FID(DRTM_FNUM_SVC_VERSION)
38 #define ARM_DRTM_SVC_FEATURES		DRTM_FID(DRTM_FNUM_SVC_FEATURES)
39 #define ARM_DRTM_SVC_UNPROTECT_MEM	DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM)
40 #define ARM_DRTM_SVC_DYNAMIC_LAUNCH	DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH)
41 #define ARM_DRTM_SVC_CLOSE_LOCALITY	DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY)
42 #define ARM_DRTM_SVC_GET_ERROR		DRTM_FID(DRTM_FNUM_SVC_GET_ERROR)
43 #define ARM_DRTM_SVC_SET_ERROR		DRTM_FID(DRTM_FNUM_SVC_SET_ERROR)
44 #define ARM_DRTM_SVC_SET_TCB_HASH	DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH)
45 #define ARM_DRTM_SVC_LOCK_TCB_HASH	DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH)
46 
47 #define ARM_DRTM_FEATURES_TPM		U(0x1)
48 #define ARM_DRTM_FEATURES_MEM_REQ	U(0x2)
49 #define ARM_DRTM_FEATURES_DMA_PROT	U(0x3)
50 #define ARM_DRTM_FEATURES_BOOT_PE_ID	U(0x4)
51 #define ARM_DRTM_FEATURES_TCB_HASHES	U(0x5)
52 
53 #define is_drtm_fid(_fid) \
54 	(((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH))
55 
56 /* ARM DRTM Service Calls version numbers */
57 #define ARM_DRTM_VERSION_MAJOR		U(0)
58 #define ARM_DRTM_VERSION_MAJOR_SHIFT	16
59 #define ARM_DRTM_VERSION_MAJOR_MASK	U(0x7FFF)
60 #define ARM_DRTM_VERSION_MINOR		U(1)
61 #define ARM_DRTM_VERSION_MINOR_SHIFT	0
62 #define ARM_DRTM_VERSION_MINOR_MASK	U(0xFFFF)
63 
64 #define ARM_DRTM_VERSION						\
65 	((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) <<	\
66 	ARM_DRTM_VERSION_MAJOR_SHIFT)					\
67 	| (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) <<	\
68 	ARM_DRTM_VERSION_MINOR_SHIFT))
69 
70 #define ARM_DRTM_FUNC_SHIFT	U(63)
71 #define ARM_DRTM_FUNC_MASK	ULL(0x1)
72 #define ARM_DRTM_FUNC_ID	U(0x0)
73 #define ARM_DRTM_FEAT_ID	U(0x1)
74 #define ARM_DRTM_FEAT_ID_MASK	ULL(0xff)
75 
76 /*
77  * Definitions for DRTM features as per DRTM beta0 section 3.3,
78  * Table 6 DRTM_FEATURES
79  */
80 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT		U(33)
81 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK		ULL(0xF)
82 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT	ULL(0x1)
83 
84 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT		U(32)
85 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK		ULL(0x1)
86 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED	ULL(0x0)
87 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED	ULL(0x1)
88 
89 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT		U(0)
90 #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK		ULL(0xFFFFFFFF)
91 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256		ULL(0xB)
92 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384		ULL(0xC)
93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512		ULL(0xD)
94 
95 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT		U(32)
96 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK		ULL(0xFFFFFFFF)
97 
98 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT	U(0)
99 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK	ULL(0xFFFFFFFF)
100 
101 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT	U(8)
102 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xF)
103 
104 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT	U(0)
105 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK	ULL(0xFF)
106 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE	ULL(0x1)
107 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION	ULL(0x2)
108 
109 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT	U(0)
110 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK	ULL(0xFF)
111 
112 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val)			\
113 	do {								\
114 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
115 		<< ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
116 		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) <<		\
117 		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT));		\
118 	} while (false)
119 
120 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val)			\
121 	do {								\
122 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK	\
123 		<< ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) &	\
124 		ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) <<			\
125 		ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT));			\
126 	} while (false)
127 
128 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val)			\
129 	do {								\
130 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK	\
131 		<< ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) &	\
132 		ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) <<			\
133 		ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT));			\
134 	} while (false)
135 
136 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val)			\
137 	do {								\
138 		reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK	\
139 		<< ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) &	\
140 		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) <<			\
141 		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT));			\
142 	} while (false)
143 
144 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val)		\
145 	do {								\
146 		reg = (((reg) &						\
147 		~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK <<	\
148 		ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) |	\
149 		(((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
150 		<< ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT));	\
151 	} while (false)
152 
153 #define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val)		\
154 	do {								\
155 		reg = (((reg) &						\
156 		~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK <<	\
157 		ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) |	\
158 		(((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK)	\
159 		<< ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT));	\
160 	} while (false)
161 
162 #define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
163 	do {								\
164 		reg = (((reg) &						\
165 		~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK <<	\
166 		ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) |	\
167 		(((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK)	\
168 		<< ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT));	\
169 	} while (false)
170 
171 #define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val)		\
172 	do {								\
173 		reg = (((reg) &						\
174 		~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK <<	\
175 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) |	\
176 		(((val) &						\
177 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) <<	\
178 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT));	\
179 	} while (false)
180 
181 /* Definitions for DRTM address map */
182 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT	U(55)
183 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK	ULL(0x3)
184 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC	ULL(0)
185 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC	ULL(1)
186 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT	ULL(2)
187 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB	ULL(3)
188 
189 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT	U(52)
190 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK	ULL(0x7)
191 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL	ULL(0)
192 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR	ULL(1)
193 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE	ULL(2)
194 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV	ULL(3)
195 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD	ULL(4)
196 
197 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT	U(0)
198 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK	ULL(0xFFFFFFFFFFFFF)
199 
200 #define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val)		\
201 	do {								\
202 		reg = (((reg) &						\
203 		~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << 	\
204 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) |	\
205 		(((val) &						\
206 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) <<		\
207 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT));		\
208 	} while (false)
209 
210 #define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val)		\
211 	do {								\
212 		reg = (((reg) &						\
213 		~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK <<		\
214 		ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) |		\
215 		(((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK)	\
216 		<< ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT));	\
217 	} while (false)
218 
219 #define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val)		\
220 	do {								\
221 		reg = (((reg) &						\
222 		~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK <<		\
223 		ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) |		\
224 		(((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK)	\
225 		<< ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT));	\
226 	} while (false)
227 
228 /* Initialization routine for the DRTM service */
229 int drtm_setup(void);
230 
231 /* Handler to be called to handle DRTM SMC calls */
232 uint64_t drtm_smc_handler(uint32_t smc_fid,
233 			  uint64_t x1,
234 			  uint64_t x2,
235 			  uint64_t x3,
236 			  uint64_t x4,
237 			  void *cookie,
238 			  void *handle,
239 			  uint64_t flags);
240 
241 #endif /* ARM_DRTM_SVC_H */
242