1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8
9 #include <drm/drm_device.h>
10 #include <drm/drm_managed.h>
11 #include <drm/drm_mm.h>
12 #include <drm/drm_print.h>
13
14 #include <linux/pci.h>
15 #include <linux/xarray.h>
16 #include <uapi/drm/ivpu_accel.h>
17
18 #include "ivpu_mmu_context.h"
19
20 #define DRIVER_NAME "intel_vpu"
21 #define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
22 #define DRIVER_DATE "20230117"
23
24 #define PCI_DEVICE_ID_MTL 0x7d1d
25
26 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
27 #define IVPU_CONTEXT_LIMIT 64
28 #define IVPU_NUM_ENGINES 2
29
30 #define IVPU_PLATFORM_SILICON 0
31 #define IVPU_PLATFORM_SIMICS 2
32 #define IVPU_PLATFORM_FPGA 3
33 #define IVPU_PLATFORM_INVALID 8
34
35 #define IVPU_DBG_REG BIT(0)
36 #define IVPU_DBG_IRQ BIT(1)
37 #define IVPU_DBG_MMU BIT(2)
38 #define IVPU_DBG_FILE BIT(3)
39 #define IVPU_DBG_MISC BIT(4)
40 #define IVPU_DBG_FW_BOOT BIT(5)
41 #define IVPU_DBG_PM BIT(6)
42 #define IVPU_DBG_IPC BIT(7)
43 #define IVPU_DBG_BO BIT(8)
44 #define IVPU_DBG_JOB BIT(9)
45 #define IVPU_DBG_JSM BIT(10)
46 #define IVPU_DBG_KREF BIT(11)
47 #define IVPU_DBG_RPM BIT(12)
48
49 #define ivpu_err(vdev, fmt, ...) \
50 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
51
52 #define ivpu_err_ratelimited(vdev, fmt, ...) \
53 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
54
55 #define ivpu_warn(vdev, fmt, ...) \
56 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
57
58 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
59 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
60
61 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
62
63 #define ivpu_dbg(vdev, type, fmt, args...) do { \
64 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
65 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
66 } while (0)
67
68 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
69
70 struct ivpu_wa_table {
71 bool punit_disabled;
72 bool clear_runtime_mem;
73 };
74
75 struct ivpu_hw_info;
76 struct ivpu_mmu_info;
77 struct ivpu_fw_info;
78 struct ivpu_ipc_info;
79 struct ivpu_pm_info;
80
81 struct ivpu_device {
82 struct drm_device drm;
83 void __iomem *regb;
84 void __iomem *regv;
85 u32 platform;
86 u32 irq;
87
88 struct ivpu_wa_table wa;
89 struct ivpu_hw_info *hw;
90 struct ivpu_mmu_info *mmu;
91 struct ivpu_fw_info *fw;
92 struct ivpu_ipc_info *ipc;
93 struct ivpu_pm_info *pm;
94
95 struct ivpu_mmu_context gctx;
96 struct xarray context_xa;
97 struct xa_limit context_xa_limit;
98
99 struct xarray submitted_jobs_xa;
100 struct task_struct *job_done_thread;
101
102 atomic64_t unique_id_counter;
103
104 struct {
105 int boot;
106 int jsm;
107 int tdr;
108 int reschedule_suspend;
109 } timeout;
110 };
111
112 /*
113 * file_priv has its own refcount (ref) that allows user space to close the fd
114 * without blocking even if VPU is still processing some jobs.
115 */
116 struct ivpu_file_priv {
117 struct kref ref;
118 struct ivpu_device *vdev;
119 struct mutex lock; /* Protects cmdq */
120 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
121 struct ivpu_mmu_context ctx;
122 u32 priority;
123 bool has_mmu_faults;
124 };
125
126 extern int ivpu_dbg_mask;
127 extern u8 ivpu_pll_min_ratio;
128 extern u8 ivpu_pll_max_ratio;
129
130 #define IVPU_TEST_MODE_DISABLED 0
131 #define IVPU_TEST_MODE_FW_TEST 1
132 #define IVPU_TEST_MODE_NULL_HW 2
133 extern int ivpu_test_mode;
134
135 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
136 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
137 void ivpu_file_priv_put(struct ivpu_file_priv **link);
138
139 int ivpu_boot(struct ivpu_device *vdev);
140 int ivpu_shutdown(struct ivpu_device *vdev);
141
ivpu_is_mtl(struct ivpu_device * vdev)142 static inline bool ivpu_is_mtl(struct ivpu_device *vdev)
143 {
144 return to_pci_dev(vdev->drm.dev)->device == PCI_DEVICE_ID_MTL;
145 }
146
ivpu_revision(struct ivpu_device * vdev)147 static inline u8 ivpu_revision(struct ivpu_device *vdev)
148 {
149 return to_pci_dev(vdev->drm.dev)->revision;
150 }
151
ivpu_device_id(struct ivpu_device * vdev)152 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
153 {
154 return to_pci_dev(vdev->drm.dev)->device;
155 }
156
to_ivpu_device(struct drm_device * dev)157 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
158 {
159 return container_of(dev, struct ivpu_device, drm);
160 }
161
ivpu_get_context_count(struct ivpu_device * vdev)162 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
163 {
164 struct xa_limit ctx_limit = vdev->context_xa_limit;
165
166 return (ctx_limit.max - ctx_limit.min + 1);
167 }
168
ivpu_get_platform(struct ivpu_device * vdev)169 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
170 {
171 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
172 return vdev->platform;
173 }
174
ivpu_is_silicon(struct ivpu_device * vdev)175 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
176 {
177 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
178 }
179
ivpu_is_simics(struct ivpu_device * vdev)180 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
181 {
182 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
183 }
184
ivpu_is_fpga(struct ivpu_device * vdev)185 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
186 {
187 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
188 }
189
190 #endif /* __IVPU_DRV_H__ */
191