1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 74 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-" 60 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 61 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-" 62 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 63 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 64 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 65 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 66 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 67 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 68 #define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-" 69 70 71 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 72 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 73 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 74 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 75 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 76 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 77 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 78 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 79 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 80 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 81 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 82 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 83 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 84 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 85 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 86 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 87 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 88 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 89 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 90 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 91 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 92 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 93 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 94 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 95 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 96 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 97 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 98 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 99 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 100 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 101 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 102 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 103 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 104 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 105 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 106 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 107 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 108 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 109 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 110 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 111 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 112 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 113 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 114 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 115 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 116 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 117 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 118 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 119 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 120 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 121 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 122 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 123 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 124 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 125 #define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \ 126 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 127 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 128 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 129 #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 130 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode" 131 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 132 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 133 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 134 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 135 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 136 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 137 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 138 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 139 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 140 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 141 #define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \ 142 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode" 143 144 static const struct iwl_base_params iwl_22000_base_params = { 145 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 146 .num_of_queues = 512, 147 .max_tfd_queue_size = 256, 148 .shadow_ram_support = true, 149 .led_compensation = 57, 150 .wd_timeout = IWL_LONG_WD_TIMEOUT, 151 .max_event_log_size = 512, 152 .shadow_reg_enable = true, 153 .pcie_l1_allowed = true, 154 }; 155 156 static const struct iwl_base_params iwl_ax210_base_params = { 157 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 158 .num_of_queues = 512, 159 .max_tfd_queue_size = 65536, 160 .shadow_ram_support = true, 161 .led_compensation = 57, 162 .wd_timeout = IWL_LONG_WD_TIMEOUT, 163 .max_event_log_size = 512, 164 .shadow_reg_enable = true, 165 .pcie_l1_allowed = true, 166 }; 167 168 static const struct iwl_ht_params iwl_22000_ht_params = { 169 .stbc = true, 170 .ldpc = true, 171 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 172 BIT(NL80211_BAND_6GHZ), 173 }; 174 175 static const struct iwl_ht_params iwl_gl_a_ht_params = { 176 .stbc = false, /* we explicitly disable STBC for GL step A */ 177 .ldpc = true, 178 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 179 BIT(NL80211_BAND_6GHZ), 180 }; 181 182 #define IWL_DEVICE_22000_COMMON \ 183 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 184 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 185 .led_mode = IWL_LED_RF_STATE, \ 186 .nvm_hw_section_num = 10, \ 187 .non_shared_ant = ANT_B, \ 188 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 189 .dccm_len = IWL_22000_DCCM_LEN, \ 190 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 191 .dccm2_len = IWL_22000_DCCM2_LEN, \ 192 .smem_offset = IWL_22000_SMEM_OFFSET, \ 193 .smem_len = IWL_22000_SMEM_LEN, \ 194 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 195 .apmg_not_supported = true, \ 196 .trans.mq_rx_supported = true, \ 197 .vht_mu_mimo_supported = true, \ 198 .mac_addr_from_csr = 0x380, \ 199 .ht_params = &iwl_22000_ht_params, \ 200 .nvm_ver = IWL_22000_NVM_VERSION, \ 201 .trans.use_tfh = true, \ 202 .trans.rf_id = true, \ 203 .trans.gen2 = true, \ 204 .nvm_type = IWL_NVM_EXT, \ 205 .dbgc_supported = true, \ 206 .min_umac_error_event_table = 0x400000, \ 207 .d3_debug_data_base_addr = 0x401000, \ 208 .d3_debug_data_length = 60 * 1024, \ 209 .mon_smem_regs = { \ 210 .write_ptr = { \ 211 .addr = LDBG_M2S_BUF_WPTR, \ 212 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 213 }, \ 214 .cycle_cnt = { \ 215 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 216 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 217 }, \ 218 } 219 220 #define IWL_DEVICE_22500 \ 221 IWL_DEVICE_22000_COMMON, \ 222 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 223 .trans.base_params = &iwl_22000_base_params, \ 224 .gp2_reg_addr = 0xa02c68, \ 225 .mon_dram_regs = { \ 226 .write_ptr = { \ 227 .addr = MON_BUFF_WRPTR_VER2, \ 228 .mask = 0xffffffff, \ 229 }, \ 230 .cycle_cnt = { \ 231 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 232 .mask = 0xffffffff, \ 233 }, \ 234 } 235 236 #define IWL_DEVICE_AX210 \ 237 IWL_DEVICE_22000_COMMON, \ 238 .trans.umac_prph_offset = 0x300000, \ 239 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 240 .trans.base_params = &iwl_ax210_base_params, \ 241 .min_txq_size = 128, \ 242 .gp2_reg_addr = 0xd02c68, \ 243 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 244 .mon_dram_regs = { \ 245 .write_ptr = { \ 246 .addr = DBGC_CUR_DBGBUF_STATUS, \ 247 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 248 }, \ 249 .cycle_cnt = { \ 250 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 251 .mask = 0xffffffff, \ 252 }, \ 253 .cur_frag = { \ 254 .addr = DBGC_CUR_DBGBUF_STATUS, \ 255 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 256 }, \ 257 } 258 259 #define IWL_DEVICE_BZ_COMMON \ 260 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 261 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 262 .led_mode = IWL_LED_RF_STATE, \ 263 .nvm_hw_section_num = 10, \ 264 .non_shared_ant = ANT_B, \ 265 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 266 .dccm_len = IWL_22000_DCCM_LEN, \ 267 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 268 .dccm2_len = IWL_22000_DCCM2_LEN, \ 269 .smem_offset = IWL_22000_SMEM_OFFSET, \ 270 .smem_len = IWL_22000_SMEM_LEN, \ 271 .apmg_not_supported = true, \ 272 .trans.mq_rx_supported = true, \ 273 .vht_mu_mimo_supported = true, \ 274 .mac_addr_from_csr = 0x30, \ 275 .nvm_ver = IWL_22000_NVM_VERSION, \ 276 .trans.use_tfh = true, \ 277 .trans.rf_id = true, \ 278 .trans.gen2 = true, \ 279 .nvm_type = IWL_NVM_EXT, \ 280 .dbgc_supported = true, \ 281 .min_umac_error_event_table = 0x400000, \ 282 .d3_debug_data_base_addr = 0x401000, \ 283 .d3_debug_data_length = 60 * 1024, \ 284 .mon_smem_regs = { \ 285 .write_ptr = { \ 286 .addr = LDBG_M2S_BUF_WPTR, \ 287 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 288 }, \ 289 .cycle_cnt = { \ 290 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 291 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 292 }, \ 293 }, \ 294 .trans.umac_prph_offset = 0x300000, \ 295 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 296 .trans.base_params = &iwl_ax210_base_params, \ 297 .min_txq_size = 128, \ 298 .gp2_reg_addr = 0xd02c68, \ 299 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 300 .mon_dram_regs = { \ 301 .write_ptr = { \ 302 .addr = DBGC_CUR_DBGBUF_STATUS, \ 303 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 304 }, \ 305 .cycle_cnt = { \ 306 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 307 .mask = 0xffffffff, \ 308 }, \ 309 .cur_frag = { \ 310 .addr = DBGC_CUR_DBGBUF_STATUS, \ 311 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 312 }, \ 313 }, \ 314 .mon_dbgi_regs = { \ 315 .write_ptr = { \ 316 .addr = DBGI_SRAM_FIFO_POINTERS, \ 317 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 318 }, \ 319 } 320 321 #define IWL_DEVICE_BZ \ 322 IWL_DEVICE_BZ_COMMON, \ 323 .ht_params = &iwl_22000_ht_params 324 325 #define IWL_DEVICE_GL_A \ 326 IWL_DEVICE_BZ_COMMON, \ 327 .ht_params = &iwl_gl_a_ht_params 328 329 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 330 .mq_rx_supported = true, 331 .use_tfh = true, 332 .rf_id = true, 333 .gen2 = true, 334 .device_family = IWL_DEVICE_FAMILY_22000, 335 .base_params = &iwl_22000_base_params, 336 }; 337 338 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 339 .mq_rx_supported = true, 340 .use_tfh = true, 341 .rf_id = true, 342 .gen2 = true, 343 .device_family = IWL_DEVICE_FAMILY_22000, 344 .base_params = &iwl_22000_base_params, 345 .integrated = true, 346 .xtal_latency = 500, 347 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 348 }; 349 350 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 351 .mq_rx_supported = true, 352 .use_tfh = true, 353 .rf_id = true, 354 .gen2 = true, 355 .device_family = IWL_DEVICE_FAMILY_22000, 356 .base_params = &iwl_22000_base_params, 357 .integrated = true, 358 .xtal_latency = 1820, 359 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 360 }; 361 362 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 363 .mq_rx_supported = true, 364 .use_tfh = true, 365 .rf_id = true, 366 .gen2 = true, 367 .device_family = IWL_DEVICE_FAMILY_22000, 368 .base_params = &iwl_22000_base_params, 369 .integrated = true, 370 .xtal_latency = 12000, 371 .low_latency_xtal = true, 372 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 373 }; 374 375 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 376 .mq_rx_supported = true, 377 .use_tfh = true, 378 .rf_id = true, 379 .gen2 = true, 380 .device_family = IWL_DEVICE_FAMILY_AX210, 381 .base_params = &iwl_ax210_base_params, 382 .umac_prph_offset = 0x300000, 383 }; 384 385 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 386 .mq_rx_supported = true, 387 .use_tfh = true, 388 .rf_id = true, 389 .gen2 = true, 390 .device_family = IWL_DEVICE_FAMILY_AX210, 391 .base_params = &iwl_ax210_base_params, 392 .umac_prph_offset = 0x300000, 393 .integrated = true, 394 /* TODO: the following values need to be checked */ 395 .xtal_latency = 500, 396 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 397 }; 398 399 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 400 .mq_rx_supported = true, 401 .use_tfh = true, 402 .rf_id = true, 403 .gen2 = true, 404 .device_family = IWL_DEVICE_FAMILY_AX210, 405 .base_params = &iwl_ax210_base_params, 406 .umac_prph_offset = 0x300000, 407 .integrated = true, 408 .low_latency_xtal = true, 409 .xtal_latency = 12000, 410 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 411 }; 412 413 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 414 .mq_rx_supported = true, 415 .use_tfh = true, 416 .rf_id = true, 417 .gen2 = true, 418 .device_family = IWL_DEVICE_FAMILY_AX210, 419 .base_params = &iwl_ax210_base_params, 420 .umac_prph_offset = 0x300000, 421 .integrated = true, 422 .low_latency_xtal = true, 423 .xtal_latency = 12000, 424 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 425 .imr_enabled = true, 426 }; 427 428 /* 429 * If the device doesn't support HE, no need to have that many buffers. 430 * 22000 devices can split multiple frames into a single RB, so fewer are 431 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 432 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 433 * additional overhead to account for processing time. 434 */ 435 #define IWL_NUM_RBDS_NON_HE 512 436 #define IWL_NUM_RBDS_22000_HE 2048 437 #define IWL_NUM_RBDS_AX210_HE 4096 438 439 /* 440 * All JF radio modules are part of the 9000 series, but the MAC part 441 * looks more like 22000. That's why this device is here, but called 442 * 9560 nevertheless. 443 */ 444 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 445 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 446 IWL_DEVICE_22500, 447 .num_rbds = IWL_NUM_RBDS_NON_HE, 448 }; 449 450 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 451 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 452 IWL_DEVICE_22500, 453 .num_rbds = IWL_NUM_RBDS_NON_HE, 454 }; 455 456 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 457 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 458 IWL_DEVICE_22500, 459 /* 460 * This device doesn't support receiving BlockAck with a large bitmap 461 * so we need to restrict the size of transmitted aggregation to the 462 * HT size; mac80211 would otherwise pick the HE max (256) by default. 463 */ 464 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 465 .num_rbds = IWL_NUM_RBDS_NON_HE, 466 }; 467 468 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 469 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 470 IWL_DEVICE_22500, 471 /* 472 * This device doesn't support receiving BlockAck with a large bitmap 473 * so we need to restrict the size of transmitted aggregation to the 474 * HT size; mac80211 would otherwise pick the HE max (256) by default. 475 */ 476 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 477 .num_rbds = IWL_NUM_RBDS_NON_HE, 478 }; 479 480 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 481 .device_family = IWL_DEVICE_FAMILY_22000, 482 .base_params = &iwl_22000_base_params, 483 .mq_rx_supported = true, 484 .use_tfh = true, 485 .rf_id = true, 486 .gen2 = true, 487 .bisr_workaround = 1, 488 }; 489 490 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 491 .device_family = IWL_DEVICE_FAMILY_AX210, 492 .base_params = &iwl_ax210_base_params, 493 .mq_rx_supported = true, 494 .use_tfh = true, 495 .rf_id = true, 496 .gen2 = true, 497 .integrated = true, 498 .umac_prph_offset = 0x300000 499 }; 500 501 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 502 .device_family = IWL_DEVICE_FAMILY_BZ, 503 .base_params = &iwl_ax210_base_params, 504 .mq_rx_supported = true, 505 .use_tfh = true, 506 .rf_id = true, 507 .gen2 = true, 508 .integrated = true, 509 .umac_prph_offset = 0x300000, 510 .xtal_latency = 12000, 511 .low_latency_xtal = true, 512 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 513 }; 514 515 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 516 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 517 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 518 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 519 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 520 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 521 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 522 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 523 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 524 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 525 526 const char iwl_ax200_killer_1650w_name[] = 527 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 528 const char iwl_ax200_killer_1650x_name[] = 529 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 530 const char iwl_ax201_killer_1650s_name[] = 531 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 532 const char iwl_ax201_killer_1650i_name[] = 533 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 534 const char iwl_ax210_killer_1675w_name[] = 535 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 536 const char iwl_ax210_killer_1675x_name[] = 537 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 538 const char iwl_ax211_killer_1675s_name[] = 539 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 540 const char iwl_ax211_killer_1675i_name[] = 541 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 542 const char iwl_ax411_killer_1690s_name[] = 543 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 544 const char iwl_ax411_killer_1690i_name[] = 545 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 546 547 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 548 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 549 IWL_DEVICE_22500, 550 /* 551 * This device doesn't support receiving BlockAck with a large bitmap 552 * so we need to restrict the size of transmitted aggregation to the 553 * HT size; mac80211 would otherwise pick the HE max (256) by default. 554 */ 555 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 556 .tx_with_siso_diversity = true, 557 .num_rbds = IWL_NUM_RBDS_22000_HE, 558 }; 559 560 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 561 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 562 IWL_DEVICE_22500, 563 /* 564 * This device doesn't support receiving BlockAck with a large bitmap 565 * so we need to restrict the size of transmitted aggregation to the 566 * HT size; mac80211 would otherwise pick the HE max (256) by default. 567 */ 568 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 569 .num_rbds = IWL_NUM_RBDS_22000_HE, 570 }; 571 572 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 573 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 574 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 575 IWL_DEVICE_22500, 576 /* 577 * This device doesn't support receiving BlockAck with a large bitmap 578 * so we need to restrict the size of transmitted aggregation to the 579 * HT size; mac80211 would otherwise pick the HE max (256) by default. 580 */ 581 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 582 .num_rbds = IWL_NUM_RBDS_22000_HE, 583 }; 584 585 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 586 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 587 IWL_DEVICE_22500, 588 /* 589 * This device doesn't support receiving BlockAck with a large bitmap 590 * so we need to restrict the size of transmitted aggregation to the 591 * HT size; mac80211 would otherwise pick the HE max (256) by default. 592 */ 593 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 594 .tx_with_siso_diversity = true, 595 .num_rbds = IWL_NUM_RBDS_22000_HE, 596 }; 597 598 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 599 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 600 IWL_DEVICE_22500, 601 /* 602 * This device doesn't support receiving BlockAck with a large bitmap 603 * so we need to restrict the size of transmitted aggregation to the 604 * HT size; mac80211 would otherwise pick the HE max (256) by default. 605 */ 606 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 607 .num_rbds = IWL_NUM_RBDS_22000_HE, 608 }; 609 610 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 611 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 612 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 613 IWL_DEVICE_22500, 614 /* 615 * This device doesn't support receiving BlockAck with a large bitmap 616 * so we need to restrict the size of transmitted aggregation to the 617 * HT size; mac80211 would otherwise pick the HE max (256) by default. 618 */ 619 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 620 .num_rbds = IWL_NUM_RBDS_22000_HE, 621 }; 622 623 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 624 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 625 IWL_DEVICE_22500, 626 /* 627 * This device doesn't support receiving BlockAck with a large bitmap 628 * so we need to restrict the size of transmitted aggregation to the 629 * HT size; mac80211 would otherwise pick the HE max (256) by default. 630 */ 631 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 632 .tx_with_siso_diversity = true, 633 .num_rbds = IWL_NUM_RBDS_22000_HE, 634 }; 635 636 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 637 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 638 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 639 IWL_DEVICE_22500, 640 /* 641 * This device doesn't support receiving BlockAck with a large bitmap 642 * so we need to restrict the size of transmitted aggregation to the 643 * HT size; mac80211 would otherwise pick the HE max (256) by default. 644 */ 645 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 646 .num_rbds = IWL_NUM_RBDS_22000_HE, 647 }; 648 649 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 650 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 651 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 652 IWL_DEVICE_22500, 653 /* 654 * This device doesn't support receiving BlockAck with a large bitmap 655 * so we need to restrict the size of transmitted aggregation to the 656 * HT size; mac80211 would otherwise pick the HE max (256) by default. 657 */ 658 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 659 .num_rbds = IWL_NUM_RBDS_22000_HE, 660 }; 661 662 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 663 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 664 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 665 IWL_DEVICE_22500, 666 /* 667 * This device doesn't support receiving BlockAck with a large bitmap 668 * so we need to restrict the size of transmitted aggregation to the 669 * HT size; mac80211 would otherwise pick the HE max (256) by default. 670 */ 671 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 672 .num_rbds = IWL_NUM_RBDS_22000_HE, 673 }; 674 675 const struct iwl_cfg iwl_ax200_cfg_cc = { 676 .fw_name_pre = IWL_CC_A_FW_PRE, 677 IWL_DEVICE_22500, 678 /* 679 * This device doesn't support receiving BlockAck with a large bitmap 680 * so we need to restrict the size of transmitted aggregation to the 681 * HT size; mac80211 would otherwise pick the HE max (256) by default. 682 */ 683 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 684 .num_rbds = IWL_NUM_RBDS_22000_HE, 685 }; 686 687 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 688 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 689 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 690 IWL_DEVICE_22500, 691 /* 692 * This device doesn't support receiving BlockAck with a large bitmap 693 * so we need to restrict the size of transmitted aggregation to the 694 * HT size; mac80211 would otherwise pick the HE max (256) by default. 695 */ 696 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 697 .num_rbds = IWL_NUM_RBDS_22000_HE, 698 }; 699 700 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 701 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 702 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 703 IWL_DEVICE_22500, 704 /* 705 * This device doesn't support receiving BlockAck with a large bitmap 706 * so we need to restrict the size of transmitted aggregation to the 707 * HT size; mac80211 would otherwise pick the HE max (256) by default. 708 */ 709 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 710 .num_rbds = IWL_NUM_RBDS_22000_HE, 711 }; 712 713 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 714 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 715 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 716 IWL_DEVICE_22500, 717 /* 718 * This device doesn't support receiving BlockAck with a large bitmap 719 * so we need to restrict the size of transmitted aggregation to the 720 * HT size; mac80211 would otherwise pick the HE max (256) by default. 721 */ 722 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 723 .num_rbds = IWL_NUM_RBDS_22000_HE, 724 }; 725 726 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 727 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 728 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 729 IWL_DEVICE_22500, 730 /* 731 * This device doesn't support receiving BlockAck with a large bitmap 732 * so we need to restrict the size of transmitted aggregation to the 733 * HT size; mac80211 would otherwise pick the HE max (256) by default. 734 */ 735 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 736 .num_rbds = IWL_NUM_RBDS_22000_HE, 737 }; 738 739 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 740 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 741 IWL_DEVICE_22500, 742 /* 743 * This device doesn't support receiving BlockAck with a large bitmap 744 * so we need to restrict the size of transmitted aggregation to the 745 * HT size; mac80211 would otherwise pick the HE max (256) by default. 746 */ 747 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 748 .num_rbds = IWL_NUM_RBDS_22000_HE, 749 }; 750 751 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 752 .name = "Intel(R) Wireless-AC 9560 160MHz", 753 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 754 IWL_DEVICE_AX210, 755 .num_rbds = IWL_NUM_RBDS_NON_HE, 756 }; 757 758 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 759 .name = iwl_ax211_name, 760 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 761 .uhb_supported = true, 762 IWL_DEVICE_AX210, 763 .num_rbds = IWL_NUM_RBDS_AX210_HE, 764 }; 765 766 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 767 .name = iwl_ax211_name, 768 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 769 .uhb_supported = true, 770 IWL_DEVICE_AX210, 771 .num_rbds = IWL_NUM_RBDS_AX210_HE, 772 .trans.xtal_latency = 12000, 773 .trans.low_latency_xtal = true, 774 }; 775 776 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 777 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 778 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 779 .uhb_supported = true, 780 IWL_DEVICE_AX210, 781 .num_rbds = IWL_NUM_RBDS_AX210_HE, 782 }; 783 784 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 785 .name = iwl_ax411_name, 786 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 787 .uhb_supported = true, 788 IWL_DEVICE_AX210, 789 .num_rbds = IWL_NUM_RBDS_AX210_HE, 790 }; 791 792 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 793 .name = iwl_ax411_name, 794 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 795 .uhb_supported = true, 796 IWL_DEVICE_AX210, 797 .num_rbds = IWL_NUM_RBDS_AX210_HE, 798 .trans.xtal_latency = 12000, 799 .trans.low_latency_xtal = true, 800 }; 801 802 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 803 .name = iwl_ax411_name, 804 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 805 .uhb_supported = true, 806 IWL_DEVICE_AX210, 807 .num_rbds = IWL_NUM_RBDS_AX210_HE, 808 }; 809 810 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 811 .name = iwl_ax211_name, 812 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 813 .uhb_supported = true, 814 IWL_DEVICE_AX210, 815 .num_rbds = IWL_NUM_RBDS_AX210_HE, 816 }; 817 818 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 819 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 820 .uhb_supported = true, 821 IWL_DEVICE_AX210, 822 .num_rbds = IWL_NUM_RBDS_AX210_HE, 823 }; 824 825 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 826 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 827 .uhb_supported = true, 828 IWL_DEVICE_AX210, 829 .num_rbds = IWL_NUM_RBDS_AX210_HE, 830 }; 831 832 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 833 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 834 .uhb_supported = true, 835 IWL_DEVICE_AX210, 836 .num_rbds = IWL_NUM_RBDS_AX210_HE, 837 }; 838 839 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 840 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 841 .uhb_supported = true, 842 IWL_DEVICE_AX210, 843 .num_rbds = IWL_NUM_RBDS_AX210_HE, 844 }; 845 846 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 847 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 848 .uhb_supported = true, 849 IWL_DEVICE_AX210, 850 .num_rbds = IWL_NUM_RBDS_AX210_HE, 851 }; 852 853 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 854 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 855 .uhb_supported = true, 856 IWL_DEVICE_AX210, 857 .num_rbds = IWL_NUM_RBDS_AX210_HE, 858 }; 859 860 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 861 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 862 .uhb_supported = false, 863 IWL_DEVICE_AX210, 864 .num_rbds = IWL_NUM_RBDS_AX210_HE, 865 }; 866 867 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 868 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 869 .uhb_supported = false, 870 IWL_DEVICE_AX210, 871 .num_rbds = IWL_NUM_RBDS_AX210_HE, 872 }; 873 874 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 875 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 876 .uhb_supported = true, 877 IWL_DEVICE_AX210, 878 .num_rbds = IWL_NUM_RBDS_AX210_HE, 879 }; 880 881 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 882 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 883 .uhb_supported = true, 884 IWL_DEVICE_AX210, 885 .num_rbds = IWL_NUM_RBDS_AX210_HE, 886 }; 887 888 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 889 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 890 .uhb_supported = false, 891 IWL_DEVICE_AX210, 892 .num_rbds = IWL_NUM_RBDS_AX210_HE, 893 }; 894 895 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 896 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 897 IWL_DEVICE_AX210, 898 .num_rbds = IWL_NUM_RBDS_AX210_HE, 899 }; 900 901 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 902 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 903 IWL_DEVICE_22500, 904 /* 905 * This device doesn't support receiving BlockAck with a large bitmap 906 * so we need to restrict the size of transmitted aggregation to the 907 * HT size; mac80211 would otherwise pick the HE max (256) by default. 908 */ 909 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 910 .num_rbds = IWL_NUM_RBDS_22000_HE, 911 }; 912 913 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 914 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 915 .uhb_supported = true, 916 IWL_DEVICE_BZ, 917 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 918 .num_rbds = IWL_NUM_RBDS_AX210_HE, 919 }; 920 921 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 922 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 923 .uhb_supported = true, 924 IWL_DEVICE_BZ, 925 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 926 .num_rbds = IWL_NUM_RBDS_AX210_HE, 927 }; 928 929 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 930 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 931 .uhb_supported = true, 932 IWL_DEVICE_BZ, 933 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 934 .num_rbds = IWL_NUM_RBDS_AX210_HE, 935 }; 936 937 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 938 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 939 .uhb_supported = true, 940 IWL_DEVICE_BZ, 941 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 942 .num_rbds = IWL_NUM_RBDS_AX210_HE, 943 }; 944 945 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 946 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 947 .uhb_supported = true, 948 IWL_DEVICE_BZ, 949 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 950 .num_rbds = IWL_NUM_RBDS_AX210_HE, 951 }; 952 953 const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = { 954 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE, 955 .uhb_supported = true, 956 IWL_DEVICE_BZ, 957 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 958 .num_rbds = IWL_NUM_RBDS_AX210_HE, 959 }; 960 961 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 962 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 963 .uhb_supported = true, 964 IWL_DEVICE_GL_A, 965 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 966 .num_rbds = IWL_NUM_RBDS_AX210_HE, 967 }; 968 969 const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = { 970 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE, 971 .uhb_supported = true, 972 IWL_DEVICE_BZ, 973 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 974 .num_rbds = IWL_NUM_RBDS_AX210_HE, 975 }; 976 977 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 978 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 979 .uhb_supported = true, 980 IWL_DEVICE_BZ, 981 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 982 .num_rbds = IWL_NUM_RBDS_AX210_HE, 983 }; 984 985 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 986 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 987 .uhb_supported = true, 988 IWL_DEVICE_BZ, 989 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 990 .num_rbds = IWL_NUM_RBDS_AX210_HE, 991 }; 992 993 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 994 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 995 .uhb_supported = true, 996 IWL_DEVICE_BZ, 997 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 998 .num_rbds = IWL_NUM_RBDS_AX210_HE, 999 }; 1000 1001 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 1002 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 1003 .uhb_supported = true, 1004 IWL_DEVICE_BZ, 1005 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1006 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1007 }; 1008 1009 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 1010 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 1011 .uhb_supported = true, 1012 IWL_DEVICE_BZ, 1013 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1014 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1015 }; 1016 1017 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 1018 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 1019 .uhb_supported = true, 1020 IWL_DEVICE_BZ, 1021 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1022 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1023 }; 1024 1025 const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = { 1026 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE, 1027 .uhb_supported = true, 1028 IWL_DEVICE_BZ, 1029 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, 1030 .num_rbds = IWL_NUM_RBDS_AX210_HE, 1031 }; 1032 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1033 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1034 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1035 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1036 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1037 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1038 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1039 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1040 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1041 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1042 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1043 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1044 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1045 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1046 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1047 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1048 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1049 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1050 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1051 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1052 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1053 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1054 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1055 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1056 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1057 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1058 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1059 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1060 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1061 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1062 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1063 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1064 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1065 MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1066 MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1067 MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1068