1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file manages link detection states and receiver states by using various
28 * link protocols. It also provides helper functions to interpret certain
29 * capabilities or status based on the states it manages or retrieve them
30 * directly from connected receivers.
31 */
32
33 #include "link_dpms.h"
34 #include "link_detection.h"
35 #include "link_hwss.h"
36 #include "protocols/link_edp_panel_control.h"
37 #include "protocols/link_ddc.h"
38 #include "protocols/link_hpd.h"
39 #include "protocols/link_dpcd.h"
40 #include "protocols/link_dp_capability.h"
41 #include "protocols/link_dp_dpia.h"
42 #include "protocols/link_dp_phy.h"
43 #include "protocols/link_dp_training.h"
44 #include "accessories/link_dp_trace.h"
45
46 #include "link_enc_cfg.h"
47 #include "dm_helpers.h"
48 #include "clk_mgr.h"
49
50 #define DC_LOGGER_INIT(logger)
51
52 #define LINK_INFO(...) \
53 DC_LOG_HW_HOTPLUG( \
54 __VA_ARGS__)
55 /*
56 * Some receivers fail to train on first try and are good
57 * on subsequent tries. 2 retries should be plenty. If we
58 * don't have a successful training then we don't expect to
59 * ever get one.
60 */
61 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
62
get_ddc_transaction_type(enum signal_type sink_signal)63 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
64 {
65 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
66
67 switch (sink_signal) {
68 case SIGNAL_TYPE_DVI_SINGLE_LINK:
69 case SIGNAL_TYPE_DVI_DUAL_LINK:
70 case SIGNAL_TYPE_HDMI_TYPE_A:
71 case SIGNAL_TYPE_LVDS:
72 case SIGNAL_TYPE_RGB:
73 transaction_type = DDC_TRANSACTION_TYPE_I2C;
74 break;
75
76 case SIGNAL_TYPE_DISPLAY_PORT:
77 case SIGNAL_TYPE_EDP:
78 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
79 break;
80
81 case SIGNAL_TYPE_DISPLAY_PORT_MST:
82 /* MST does not use I2COverAux, but there is the
83 * SPECIAL use case for "immediate dwnstrm device
84 * access" (EPR#370830).
85 */
86 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
87 break;
88
89 default:
90 break;
91 }
92
93 return transaction_type;
94 }
95
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)96 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
97 struct graphics_object_id downstream)
98 {
99 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
100 switch (downstream.id) {
101 case CONNECTOR_ID_SINGLE_LINK_DVII:
102 switch (encoder.id) {
103 case ENCODER_ID_INTERNAL_DAC1:
104 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
105 case ENCODER_ID_INTERNAL_DAC2:
106 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
107 return SIGNAL_TYPE_RGB;
108 default:
109 return SIGNAL_TYPE_DVI_SINGLE_LINK;
110 }
111 break;
112 case CONNECTOR_ID_DUAL_LINK_DVII:
113 {
114 switch (encoder.id) {
115 case ENCODER_ID_INTERNAL_DAC1:
116 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
117 case ENCODER_ID_INTERNAL_DAC2:
118 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
119 return SIGNAL_TYPE_RGB;
120 default:
121 return SIGNAL_TYPE_DVI_DUAL_LINK;
122 }
123 }
124 break;
125 case CONNECTOR_ID_SINGLE_LINK_DVID:
126 return SIGNAL_TYPE_DVI_SINGLE_LINK;
127 case CONNECTOR_ID_DUAL_LINK_DVID:
128 return SIGNAL_TYPE_DVI_DUAL_LINK;
129 case CONNECTOR_ID_VGA:
130 return SIGNAL_TYPE_RGB;
131 case CONNECTOR_ID_HDMI_TYPE_A:
132 return SIGNAL_TYPE_HDMI_TYPE_A;
133 case CONNECTOR_ID_LVDS:
134 return SIGNAL_TYPE_LVDS;
135 case CONNECTOR_ID_DISPLAY_PORT:
136 case CONNECTOR_ID_USBC:
137 return SIGNAL_TYPE_DISPLAY_PORT;
138 case CONNECTOR_ID_EDP:
139 return SIGNAL_TYPE_EDP;
140 default:
141 return SIGNAL_TYPE_NONE;
142 }
143 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
144 switch (downstream.id) {
145 case ENCODER_ID_EXTERNAL_NUTMEG:
146 case ENCODER_ID_EXTERNAL_TRAVIS:
147 return SIGNAL_TYPE_DISPLAY_PORT;
148 default:
149 return SIGNAL_TYPE_NONE;
150 }
151 }
152
153 return SIGNAL_TYPE_NONE;
154 }
155
156 /*
157 * @brief
158 * Detect output sink type
159 */
link_detect_sink_signal_type(struct dc_link * link,enum dc_detect_reason reason)160 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
161 enum dc_detect_reason reason)
162 {
163 enum signal_type result;
164 struct graphics_object_id enc_id;
165
166 if (link->is_dig_mapping_flexible)
167 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
168 else
169 enc_id = link->link_enc->id;
170 result = get_basic_signal_type(enc_id, link->link_id);
171
172 /* Use basic signal type for link without physical connector. */
173 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
174 return result;
175
176 /* Internal digital encoder will detect only dongles
177 * that require digital signal
178 */
179
180 /* Detection mechanism is different
181 * for different native connectors.
182 * LVDS connector supports only LVDS signal;
183 * PCIE is a bus slot, the actual connector needs to be detected first;
184 * eDP connector supports only eDP signal;
185 * HDMI should check straps for audio
186 */
187
188 /* PCIE detects the actual connector on add-on board */
189 if (link->link_id.id == CONNECTOR_ID_PCIE) {
190 /* ZAZTODO implement PCIE add-on card detection */
191 }
192
193 switch (link->link_id.id) {
194 case CONNECTOR_ID_HDMI_TYPE_A: {
195 /* check audio support:
196 * if native HDMI is not supported, switch to DVI
197 */
198 struct audio_support *aud_support =
199 &link->dc->res_pool->audio_support;
200
201 if (!aud_support->hdmi_audio_native)
202 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
203 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
204 }
205 break;
206 case CONNECTOR_ID_DISPLAY_PORT:
207 case CONNECTOR_ID_USBC: {
208 /* DP HPD short pulse. Passive DP dongle will not
209 * have short pulse
210 */
211 if (reason != DETECT_REASON_HPDRX) {
212 /* Check whether DP signal detected: if not -
213 * we assume signal is DVI; it could be corrected
214 * to HDMI after dongle detection
215 */
216 if (!dm_helpers_is_dp_sink_present(link))
217 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
218 }
219 }
220 break;
221 default:
222 break;
223 }
224
225 return result;
226 }
227
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)228 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
229 struct audio_support *audio_support)
230 {
231 enum signal_type signal = SIGNAL_TYPE_NONE;
232
233 switch (dongle_type) {
234 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
235 if (audio_support->hdmi_audio_on_dongle)
236 signal = SIGNAL_TYPE_HDMI_TYPE_A;
237 else
238 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
239 break;
240 case DISPLAY_DONGLE_DP_DVI_DONGLE:
241 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
242 break;
243 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
244 if (audio_support->hdmi_audio_native)
245 signal = SIGNAL_TYPE_HDMI_TYPE_A;
246 else
247 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
248 break;
249 default:
250 signal = SIGNAL_TYPE_NONE;
251 break;
252 }
253
254 return signal;
255 }
256
read_scdc_caps(struct ddc_service * ddc_service,struct dc_sink * sink)257 static void read_scdc_caps(struct ddc_service *ddc_service,
258 struct dc_sink *sink)
259 {
260 uint8_t slave_address = HDMI_SCDC_ADDRESS;
261 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
262
263 link_query_ddc_data(ddc_service, slave_address, &offset,
264 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
265 sizeof(sink->scdc_caps.manufacturer_OUI.byte));
266
267 offset = HDMI_SCDC_DEVICE_ID;
268
269 link_query_ddc_data(ddc_service, slave_address, &offset,
270 sizeof(offset), &(sink->scdc_caps.device_id.byte),
271 sizeof(sink->scdc_caps.device_id.byte));
272 }
273
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)274 static bool i2c_read(
275 struct ddc_service *ddc,
276 uint32_t address,
277 uint8_t *buffer,
278 uint32_t len)
279 {
280 uint8_t offs_data = 0;
281 struct i2c_payload payloads[2] = {
282 {
283 .write = true,
284 .address = address,
285 .length = 1,
286 .data = &offs_data },
287 {
288 .write = false,
289 .address = address,
290 .length = len,
291 .data = buffer } };
292
293 struct i2c_command command = {
294 .payloads = payloads,
295 .number_of_payloads = 2,
296 .engine = DDC_I2C_COMMAND_ENGINE,
297 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
298
299 return dm_helpers_submit_i2c(
300 ddc->ctx,
301 ddc->link,
302 &command);
303 }
304
305 enum {
306 DP_SINK_CAP_SIZE =
307 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
308 };
309
query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)310 static void query_dp_dual_mode_adaptor(
311 struct ddc_service *ddc,
312 struct display_sink_capability *sink_cap)
313 {
314 uint8_t i;
315 bool is_valid_hdmi_signature;
316 enum display_dongle_type *dongle = &sink_cap->dongle_type;
317 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
318 bool is_type2_dongle = false;
319 int retry_count = 2;
320 struct dp_hdmi_dongle_signature_data *dongle_signature;
321
322 /* Assume we have no valid DP passive dongle connected */
323 *dongle = DISPLAY_DONGLE_NONE;
324 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
325
326 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
327 if (!i2c_read(
328 ddc,
329 DP_HDMI_DONGLE_ADDRESS,
330 type2_dongle_buf,
331 sizeof(type2_dongle_buf))) {
332 /* Passive HDMI dongles can sometimes fail here without retrying*/
333 while (retry_count > 0) {
334 if (i2c_read(ddc,
335 DP_HDMI_DONGLE_ADDRESS,
336 type2_dongle_buf,
337 sizeof(type2_dongle_buf)))
338 break;
339 retry_count--;
340 }
341 if (retry_count == 0) {
342 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
343 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
344
345 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
346 "DP-DVI passive dongle %dMhz: ",
347 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
348 return;
349 }
350 }
351
352 /* Check if Type 2 dongle.*/
353 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
354 is_type2_dongle = true;
355
356 dongle_signature =
357 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
358
359 is_valid_hdmi_signature = true;
360
361 /* Check EOT */
362 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
363 is_valid_hdmi_signature = false;
364 }
365
366 /* Check signature */
367 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
368 /* If its not the right signature,
369 * skip mismatch in subversion byte.*/
370 if (dongle_signature->id[i] !=
371 dp_hdmi_dongle_signature_str[i] && i != 3) {
372
373 if (is_type2_dongle) {
374 is_valid_hdmi_signature = false;
375 break;
376 }
377
378 }
379 }
380
381 if (is_type2_dongle) {
382 uint32_t max_tmds_clk =
383 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
384
385 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
386
387 if (0 == max_tmds_clk ||
388 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
389 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
390 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
391
392 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
393 sizeof(type2_dongle_buf),
394 "DP-DVI passive dongle %dMhz: ",
395 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
396 } else {
397 if (is_valid_hdmi_signature == true) {
398 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
399
400 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
401 sizeof(type2_dongle_buf),
402 "Type 2 DP-HDMI passive dongle %dMhz: ",
403 max_tmds_clk);
404 } else {
405 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
406
407 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
408 sizeof(type2_dongle_buf),
409 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
410 max_tmds_clk);
411
412 }
413
414 /* Multiply by 1000 to convert to kHz. */
415 sink_cap->max_hdmi_pixel_clock =
416 max_tmds_clk * 1000;
417 }
418 sink_cap->is_dongle_type_one = false;
419
420 } else {
421 if (is_valid_hdmi_signature == true) {
422 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
423
424 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
425 sizeof(type2_dongle_buf),
426 "Type 1 DP-HDMI passive dongle %dMhz: ",
427 sink_cap->max_hdmi_pixel_clock / 1000);
428 } else {
429 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
430
431 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
432 sizeof(type2_dongle_buf),
433 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
434 sink_cap->max_hdmi_pixel_clock / 1000);
435 }
436 sink_cap->is_dongle_type_one = true;
437 }
438
439 return;
440 }
441
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)442 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
443 struct display_sink_capability *sink_cap,
444 struct audio_support *audio_support)
445 {
446 query_dp_dual_mode_adaptor(ddc, sink_cap);
447
448 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
449 audio_support);
450 }
451
link_disconnect_sink(struct dc_link * link)452 static void link_disconnect_sink(struct dc_link *link)
453 {
454 if (link->local_sink) {
455 dc_sink_release(link->local_sink);
456 link->local_sink = NULL;
457 }
458
459 link->dpcd_sink_count = 0;
460 //link->dpcd_caps.dpcd_rev.raw = 0;
461 }
462
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)463 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
464 {
465 dc_sink_release(link->local_sink);
466 link->local_sink = prev_sink;
467 }
468
469 #if defined(CONFIG_DRM_AMD_DC_HDCP)
query_hdcp_capability(enum signal_type signal,struct dc_link * link)470 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
471 {
472 struct hdcp_protection_message msg22;
473 struct hdcp_protection_message msg14;
474
475 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
476 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
477 memset(link->hdcp_caps.rx_caps.raw, 0,
478 sizeof(link->hdcp_caps.rx_caps.raw));
479
480 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
481 link->ddc->transaction_type ==
482 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
483 link->connector_signal == SIGNAL_TYPE_EDP) {
484 msg22.data = link->hdcp_caps.rx_caps.raw;
485 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
486 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
487 } else {
488 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
489 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
490 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
491 }
492 msg22.version = HDCP_VERSION_22;
493 msg22.link = HDCP_LINK_PRIMARY;
494 msg22.max_retries = 5;
495 dc_process_hdcp_msg(signal, link, &msg22);
496
497 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
498 enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
499
500 msg14.data = &link->hdcp_caps.bcaps.raw;
501 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
502 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
503 msg14.version = HDCP_VERSION_14;
504 msg14.link = HDCP_LINK_PRIMARY;
505 msg14.max_retries = 5;
506
507 status = dc_process_hdcp_msg(signal, link, &msg14);
508 }
509
510 }
511 #endif // CONFIG_DRM_AMD_DC_HDCP
read_current_link_settings_on_detect(struct dc_link * link)512 static void read_current_link_settings_on_detect(struct dc_link *link)
513 {
514 union lane_count_set lane_count_set = {0};
515 uint8_t link_bw_set;
516 uint8_t link_rate_set;
517 uint32_t read_dpcd_retry_cnt = 10;
518 enum dc_status status = DC_ERROR_UNEXPECTED;
519 int i;
520 union max_down_spread max_down_spread = {0};
521
522 // Read DPCD 00101h to find out the number of lanes currently set
523 for (i = 0; i < read_dpcd_retry_cnt; i++) {
524 status = core_link_read_dpcd(link,
525 DP_LANE_COUNT_SET,
526 &lane_count_set.raw,
527 sizeof(lane_count_set));
528 /* First DPCD read after VDD ON can fail if the particular board
529 * does not have HPD pin wired correctly. So if DPCD read fails,
530 * which it should never happen, retry a few times. Target worst
531 * case scenario of 80 ms.
532 */
533 if (status == DC_OK) {
534 link->cur_link_settings.lane_count =
535 lane_count_set.bits.LANE_COUNT_SET;
536 break;
537 }
538
539 msleep(8);
540 }
541
542 // Read DPCD 00100h to find if standard link rates are set
543 core_link_read_dpcd(link, DP_LINK_BW_SET,
544 &link_bw_set, sizeof(link_bw_set));
545
546 if (link_bw_set == 0) {
547 if (link->connector_signal == SIGNAL_TYPE_EDP) {
548 /* If standard link rates are not being used,
549 * Read DPCD 00115h to find the edp link rate set used
550 */
551 core_link_read_dpcd(link, DP_LINK_RATE_SET,
552 &link_rate_set, sizeof(link_rate_set));
553
554 // edp_supported_link_rates_count = 0 for DP
555 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
556 link->cur_link_settings.link_rate =
557 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
558 link->cur_link_settings.link_rate_set = link_rate_set;
559 link->cur_link_settings.use_link_rate_set = true;
560 }
561 } else {
562 // Link Rate not found. Seamless boot may not work.
563 ASSERT(false);
564 }
565 } else {
566 link->cur_link_settings.link_rate = link_bw_set;
567 link->cur_link_settings.use_link_rate_set = false;
568 }
569 // Read DPCD 00003h to find the max down spread.
570 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
571 &max_down_spread.raw, sizeof(max_down_spread));
572 link->cur_link_settings.link_spread =
573 max_down_spread.bits.MAX_DOWN_SPREAD ?
574 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
575 }
576
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)577 static bool detect_dp(struct dc_link *link,
578 struct display_sink_capability *sink_caps,
579 enum dc_detect_reason reason)
580 {
581 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
582
583 sink_caps->signal = link_detect_sink_signal_type(link, reason);
584 sink_caps->transaction_type =
585 get_ddc_transaction_type(sink_caps->signal);
586
587 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
588 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
589 if (!detect_dp_sink_caps(link))
590 return false;
591
592 if (is_dp_branch_device(link))
593 /* DP SST branch */
594 link->type = dc_connection_sst_branch;
595 } else {
596 /* DP passive dongles */
597 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
598 sink_caps,
599 audio_support);
600 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
601 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
602 link->dpcd_caps.dpcd_rev.raw = 0;
603 }
604
605 return true;
606 }
607
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)608 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
609 {
610 if (old_edid->length != new_edid->length)
611 return false;
612
613 if (new_edid->length == 0)
614 return false;
615
616 return (memcmp(old_edid->raw_edid,
617 new_edid->raw_edid, new_edid->length) == 0);
618 }
619
wait_for_entering_dp_alt_mode(struct dc_link * link)620 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
621 {
622
623 /**
624 * something is terribly wrong if time out is > 200ms. (5Hz)
625 * 500 microseconds * 400 tries us 200 ms
626 **/
627 unsigned int sleep_time_in_microseconds = 500;
628 unsigned int tries_allowed = 400;
629 bool is_in_alt_mode;
630 unsigned long long enter_timestamp;
631 unsigned long long finish_timestamp;
632 unsigned long long time_taken_in_ns;
633 int tries_taken;
634
635 DC_LOGGER_INIT(link->ctx->logger);
636
637 /**
638 * this function will only exist if we are on dcn21 (is_in_alt_mode is a
639 * function pointer, so checking to see if it is equal to 0 is the same
640 * as checking to see if it is null
641 **/
642 if (!link->link_enc->funcs->is_in_alt_mode)
643 return true;
644
645 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
646 DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
647
648 if (is_in_alt_mode)
649 return true;
650
651 enter_timestamp = dm_get_timestamp(link->ctx);
652
653 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
654 udelay(sleep_time_in_microseconds);
655 /* ask the link if alt mode is enabled, if so return ok */
656 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
657 finish_timestamp = dm_get_timestamp(link->ctx);
658 time_taken_in_ns =
659 dm_get_elapse_time_in_ns(link->ctx,
660 finish_timestamp,
661 enter_timestamp);
662 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
663 div_u64(time_taken_in_ns, 1000000));
664 return true;
665 }
666 }
667 finish_timestamp = dm_get_timestamp(link->ctx);
668 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
669 enter_timestamp);
670 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
671 div_u64(time_taken_in_ns, 1000000));
672 return false;
673 }
674
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)675 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
676 {
677 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
678 * reports DSC support.
679 */
680 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
681 link->type == dc_connection_mst_branch &&
682 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
683 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
684 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
685 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
686 link->wa_flags.dpia_mst_dsc_always_on = true;
687 }
688
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)689 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
690 {
691 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
692 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
693 link->wa_flags.dpia_mst_dsc_always_on = false;
694 }
695
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)696 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
697 {
698 DC_LOGGER_INIT(link->ctx->logger);
699
700 LINK_INFO("link=%d, mst branch is now Connected\n",
701 link->link_index);
702
703 link->type = dc_connection_mst_branch;
704 apply_dpia_mst_dsc_always_on_wa(link);
705
706 dm_helpers_dp_update_branch_info(link->ctx, link);
707 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
708 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
709 link_disconnect_sink(link);
710 } else {
711 link->type = dc_connection_sst_branch;
712 }
713
714 return link->type == dc_connection_mst_branch;
715 }
716
link_reset_cur_dp_mst_topology(struct dc_link * link)717 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
718 {
719 DC_LOGGER_INIT(link->ctx->logger);
720
721 LINK_INFO("link=%d, mst branch is now Disconnected\n",
722 link->link_index);
723
724 revert_dpia_mst_dsc_always_on_wa(link);
725 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
726 }
727
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)728 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
729 enum dc_detect_reason reason)
730 {
731 int i;
732 bool can_apply_seamless_boot = false;
733
734 for (i = 0; i < dc->current_state->stream_count; i++) {
735 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
736 can_apply_seamless_boot = true;
737 break;
738 }
739 }
740
741 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
742 }
743
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)744 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
745 {
746 dc_z10_restore(dc);
747 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
748 }
749
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)750 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
751 {
752 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
753 }
754
verify_link_capability_destructive(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)755 static void verify_link_capability_destructive(struct dc_link *link,
756 struct dc_sink *sink,
757 enum dc_detect_reason reason)
758 {
759 bool should_prepare_phy_clocks =
760 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
761
762 if (should_prepare_phy_clocks)
763 prepare_phy_clocks_for_destructive_link_verification(link->dc);
764
765 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
766 struct dc_link_settings known_limit_link_setting =
767 dp_get_max_link_cap(link);
768 link_set_all_streams_dpms_off_for_link(link);
769 dp_verify_link_cap_with_retries(
770 link, &known_limit_link_setting,
771 LINK_TRAINING_MAX_VERIFY_RETRY);
772 } else {
773 ASSERT(0);
774 }
775
776 if (should_prepare_phy_clocks)
777 restore_phy_clocks_for_destructive_link_verification(link->dc);
778 }
779
verify_link_capability_non_destructive(struct dc_link * link)780 static void verify_link_capability_non_destructive(struct dc_link *link)
781 {
782 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
783 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
784 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
785 /* TODO - should we check link encoder's max link caps here?
786 * How do we know which link encoder to check from?
787 */
788 link->verified_link_cap = link->reported_link_cap;
789 else
790 link->verified_link_cap = dp_get_max_link_cap(link);
791 }
792 }
793
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)794 static bool should_verify_link_capability_destructively(struct dc_link *link,
795 enum dc_detect_reason reason)
796 {
797 bool destrictive = false;
798 struct dc_link_settings max_link_cap;
799 bool is_link_enc_unavailable = link->link_enc &&
800 link->dc->res_pool->funcs->link_encs_assign &&
801 !link_enc_cfg_is_link_enc_avail(
802 link->ctx->dc,
803 link->link_enc->preferred_engine,
804 link);
805
806 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
807 max_link_cap = dp_get_max_link_cap(link);
808 destrictive = true;
809
810 if (link->dc->debug.skip_detection_link_training ||
811 dc_is_embedded_signal(link->local_sink->sink_signal) ||
812 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
813 destrictive = false;
814 } else if (link_dp_get_encoding_format(&max_link_cap) ==
815 DP_8b_10b_ENCODING) {
816 if (link->dpcd_caps.is_mst_capable ||
817 is_link_enc_unavailable) {
818 destrictive = false;
819 }
820 }
821 }
822
823 return destrictive;
824 }
825
verify_link_capability(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)826 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
827 enum dc_detect_reason reason)
828 {
829 if (should_verify_link_capability_destructively(link, reason))
830 verify_link_capability_destructive(link, sink, reason);
831 else
832 verify_link_capability_non_destructive(link);
833 }
834
835 /**
836 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
837 *
838 * link->local_sink is created or destroyed as needed.
839 *
840 * This does not create remote sinks.
841 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)842 static bool detect_link_and_local_sink(struct dc_link *link,
843 enum dc_detect_reason reason)
844 {
845 struct dc_sink_init_data sink_init_data = { 0 };
846 struct display_sink_capability sink_caps = { 0 };
847 uint32_t i;
848 bool converter_disable_audio = false;
849 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
850 bool same_edid = false;
851 enum dc_edid_status edid_status;
852 struct dc_context *dc_ctx = link->ctx;
853 struct dc *dc = dc_ctx->dc;
854 struct dc_sink *sink = NULL;
855 struct dc_sink *prev_sink = NULL;
856 struct dpcd_caps prev_dpcd_caps;
857 enum dc_connection_type new_connection_type = dc_connection_none;
858 const uint32_t post_oui_delay = 30; // 30ms
859
860 DC_LOGGER_INIT(link->ctx->logger);
861
862 if (dc_is_virtual_signal(link->connector_signal))
863 return false;
864
865 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
866 link->connector_signal == SIGNAL_TYPE_EDP) &&
867 (!link->dc->config.allow_edp_hotplug_detection)) &&
868 link->local_sink) {
869 // need to re-write OUI and brightness in resume case
870 if (link->connector_signal == SIGNAL_TYPE_EDP &&
871 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
872 dpcd_set_source_specific_data(link);
873 msleep(post_oui_delay);
874 set_default_brightness_aux(link);
875 //TODO: use cached
876 }
877
878 return true;
879 }
880
881 if (!dc_link_detect_connection_type(link, &new_connection_type)) {
882 BREAK_TO_DEBUGGER();
883 return false;
884 }
885
886 prev_sink = link->local_sink;
887 if (prev_sink) {
888 dc_sink_retain(prev_sink);
889 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
890 }
891
892 link_disconnect_sink(link);
893 if (new_connection_type != dc_connection_none) {
894 link->type = new_connection_type;
895 link->link_state_valid = false;
896
897 /* From Disconnected-to-Connected. */
898 switch (link->connector_signal) {
899 case SIGNAL_TYPE_HDMI_TYPE_A: {
900 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
901 if (aud_support->hdmi_audio_native)
902 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
903 else
904 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
905 break;
906 }
907
908 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
909 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
910 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
911 break;
912 }
913
914 case SIGNAL_TYPE_DVI_DUAL_LINK: {
915 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
916 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
917 break;
918 }
919
920 case SIGNAL_TYPE_LVDS: {
921 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
922 sink_caps.signal = SIGNAL_TYPE_LVDS;
923 break;
924 }
925
926 case SIGNAL_TYPE_EDP: {
927 detect_edp_sink_caps(link);
928 read_current_link_settings_on_detect(link);
929
930 /* Disable power sequence on MIPI panel + converter
931 */
932 if (dc->config.enable_mipi_converter_optimization &&
933 dc_ctx->dce_version == DCN_VERSION_3_01 &&
934 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
935 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
936 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
937 dc->config.edp_no_power_sequencing = true;
938
939 if (!link->dpcd_caps.set_power_state_capable_edp)
940 link->wa_flags.dp_keep_receiver_powered = true;
941 }
942
943 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
944 sink_caps.signal = SIGNAL_TYPE_EDP;
945 break;
946 }
947
948 case SIGNAL_TYPE_DISPLAY_PORT: {
949
950 /* wa HPD high coming too early*/
951 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
952 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
953
954 /* if alt mode times out, return false */
955 if (!wait_for_entering_dp_alt_mode(link))
956 return false;
957 }
958
959 if (!detect_dp(link, &sink_caps, reason)) {
960 if (prev_sink)
961 dc_sink_release(prev_sink);
962 return false;
963 }
964
965 /* Active SST downstream branch device unplug*/
966 if (link->type == dc_connection_sst_branch &&
967 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
968 if (prev_sink)
969 /* Downstream unplug */
970 dc_sink_release(prev_sink);
971 return true;
972 }
973
974 /* disable audio for non DP to HDMI active sst converter */
975 if (link->type == dc_connection_sst_branch &&
976 is_dp_active_dongle(link) &&
977 (link->dpcd_caps.dongle_type !=
978 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
979 converter_disable_audio = true;
980 break;
981 }
982
983 default:
984 DC_ERROR("Invalid connector type! signal:%d\n",
985 link->connector_signal);
986 if (prev_sink)
987 dc_sink_release(prev_sink);
988 return false;
989 } /* switch() */
990
991 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
992 link->dpcd_sink_count =
993 link->dpcd_caps.sink_count.bits.SINK_COUNT;
994 else
995 link->dpcd_sink_count = 1;
996
997 set_ddc_transaction_type(link->ddc,
998 sink_caps.transaction_type);
999
1000 link->aux_mode =
1001 link_is_in_aux_transaction_mode(link->ddc);
1002
1003 sink_init_data.link = link;
1004 sink_init_data.sink_signal = sink_caps.signal;
1005
1006 sink = dc_sink_create(&sink_init_data);
1007 if (!sink) {
1008 DC_ERROR("Failed to create sink!\n");
1009 if (prev_sink)
1010 dc_sink_release(prev_sink);
1011 return false;
1012 }
1013
1014 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1015 sink->converter_disable_audio = converter_disable_audio;
1016
1017 /* dc_sink_create returns a new reference */
1018 link->local_sink = sink;
1019
1020 edid_status = dm_helpers_read_local_edid(link->ctx,
1021 link, sink);
1022
1023 switch (edid_status) {
1024 case EDID_BAD_CHECKSUM:
1025 DC_LOG_ERROR("EDID checksum invalid.\n");
1026 break;
1027 case EDID_PARTIAL_VALID:
1028 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1029 break;
1030 case EDID_NO_RESPONSE:
1031 DC_LOG_ERROR("No EDID read.\n");
1032 /*
1033 * Abort detection for non-DP connectors if we have
1034 * no EDID
1035 *
1036 * DP needs to report as connected if HDP is high
1037 * even if we have no EDID in order to go to
1038 * fail-safe mode
1039 */
1040 if (dc_is_hdmi_signal(link->connector_signal) ||
1041 dc_is_dvi_signal(link->connector_signal)) {
1042 if (prev_sink)
1043 dc_sink_release(prev_sink);
1044
1045 return false;
1046 }
1047
1048 if (link->type == dc_connection_sst_branch &&
1049 link->dpcd_caps.dongle_type ==
1050 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1051 reason == DETECT_REASON_HPDRX) {
1052 /* Abort detection for DP-VGA adapters when EDID
1053 * can't be read and detection reason is VGA-side
1054 * hotplug
1055 */
1056 if (prev_sink)
1057 dc_sink_release(prev_sink);
1058 link_disconnect_sink(link);
1059
1060 return true;
1061 }
1062
1063 break;
1064 default:
1065 break;
1066 }
1067
1068 // Check if edid is the same
1069 if ((prev_sink) &&
1070 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1071 same_edid = is_same_edid(&prev_sink->dc_edid,
1072 &sink->dc_edid);
1073
1074 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1075 link->ctx->dc->debug.hdmi20_disable = true;
1076
1077 if (dc_is_hdmi_signal(link->connector_signal))
1078 read_scdc_caps(link->ddc, link->local_sink);
1079
1080 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1081 sink_caps.transaction_type ==
1082 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1083 /*
1084 * TODO debug why certain monitors don't like
1085 * two link trainings
1086 */
1087 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1088 query_hdcp_capability(sink->sink_signal, link);
1089 #endif
1090 } else {
1091 // If edid is the same, then discard new sink and revert back to original sink
1092 if (same_edid) {
1093 link_disconnect_remap(prev_sink, link);
1094 sink = prev_sink;
1095 prev_sink = NULL;
1096 }
1097 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1098 query_hdcp_capability(sink->sink_signal, link);
1099 #endif
1100 }
1101
1102 /* HDMI-DVI Dongle */
1103 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1104 !sink->edid_caps.edid_hdmi)
1105 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1106
1107 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1108 dp_trace_init(link);
1109
1110 /* Connectivity log: detection */
1111 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1112 CONN_DATA_DETECT(link,
1113 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1114 DC_EDID_BLOCK_SIZE,
1115 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1116 }
1117
1118 DC_LOG_DETECTION_EDID_PARSER("%s: "
1119 "manufacturer_id = %X, "
1120 "product_id = %X, "
1121 "serial_number = %X, "
1122 "manufacture_week = %d, "
1123 "manufacture_year = %d, "
1124 "display_name = %s, "
1125 "speaker_flag = %d, "
1126 "audio_mode_count = %d\n",
1127 __func__,
1128 sink->edid_caps.manufacturer_id,
1129 sink->edid_caps.product_id,
1130 sink->edid_caps.serial_number,
1131 sink->edid_caps.manufacture_week,
1132 sink->edid_caps.manufacture_year,
1133 sink->edid_caps.display_name,
1134 sink->edid_caps.speaker_flags,
1135 sink->edid_caps.audio_mode_count);
1136
1137 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1138 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1139 "format_code = %d, "
1140 "channel_count = %d, "
1141 "sample_rate = %d, "
1142 "sample_size = %d\n",
1143 __func__,
1144 i,
1145 sink->edid_caps.audio_modes[i].format_code,
1146 sink->edid_caps.audio_modes[i].channel_count,
1147 sink->edid_caps.audio_modes[i].sample_rate,
1148 sink->edid_caps.audio_modes[i].sample_size);
1149 }
1150
1151 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1152 // Init dc_panel_config by HW config
1153 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1154 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1155 // Pickup base DM settings
1156 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1157 // Override dc_panel_config if system has specific settings
1158 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1159 }
1160
1161 } else {
1162 /* From Connected-to-Disconnected. */
1163 link->type = dc_connection_none;
1164 sink_caps.signal = SIGNAL_TYPE_NONE;
1165 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1166 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1167 #endif
1168 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1169 * is not cleared. If we emulate a DP signal on this connection, it thinks
1170 * the dongle is still there and limits the number of modes we can emulate.
1171 * Clear dongle_max_pix_clk on disconnect to fix this
1172 */
1173 link->dongle_max_pix_clk = 0;
1174
1175 dc_link_clear_dprx_states(link);
1176 dp_trace_reset(link);
1177 }
1178
1179 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1180 link->link_index, sink,
1181 (sink_caps.signal ==
1182 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1183 prev_sink, same_edid);
1184
1185 if (prev_sink)
1186 dc_sink_release(prev_sink);
1187
1188 return true;
1189 }
1190
1191 /**
1192 * dc_link_detect_connection_type() - Determine if there is a sink connected
1193 *
1194 * @type: Returned connection type
1195 * Does not detect downstream devices, such as MST sinks
1196 * or display connected through active dongles
1197 */
link_detect_connection_type(struct dc_link * link,enum dc_connection_type * type)1198 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1199 {
1200 uint32_t is_hpd_high = 0;
1201
1202 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1203 *type = dc_connection_single;
1204 return true;
1205 }
1206
1207 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1208 /*in case it is not on*/
1209 if (!link->dc->config.edp_no_power_sequencing)
1210 link->dc->hwss.edp_power_control(link, true);
1211 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1212 }
1213
1214 /* Link may not have physical HPD pin. */
1215 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1216 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
1217 *type = dc_connection_none;
1218 else
1219 *type = dc_connection_single;
1220
1221 return true;
1222 }
1223
1224
1225 if (!query_hpd_status(link, &is_hpd_high))
1226 goto hpd_gpio_failure;
1227
1228 if (is_hpd_high) {
1229 *type = dc_connection_single;
1230 /* TODO: need to do the actual detection */
1231 } else {
1232 *type = dc_connection_none;
1233 }
1234
1235 return true;
1236
1237 hpd_gpio_failure:
1238 return false;
1239 }
1240
link_detect(struct dc_link * link,enum dc_detect_reason reason)1241 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1242 {
1243 bool is_local_sink_detect_success;
1244 bool is_delegated_to_mst_top_mgr = false;
1245 enum dc_connection_type pre_link_type = link->type;
1246
1247 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1248
1249 if (is_local_sink_detect_success && link->local_sink)
1250 verify_link_capability(link, link->local_sink, reason);
1251
1252 if (is_local_sink_detect_success && link->local_sink &&
1253 dc_is_dp_signal(link->local_sink->sink_signal) &&
1254 link->dpcd_caps.is_mst_capable)
1255 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1256
1257 if (is_local_sink_detect_success &&
1258 pre_link_type == dc_connection_mst_branch &&
1259 link->type != dc_connection_mst_branch)
1260 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1261
1262 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1263 }
1264
link_clear_dprx_states(struct dc_link * link)1265 void link_clear_dprx_states(struct dc_link *link)
1266 {
1267 memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1268 }
1269 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1270
link_is_hdcp14(struct dc_link * link,enum signal_type signal)1271 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1272 {
1273 bool ret = false;
1274
1275 switch (signal) {
1276 case SIGNAL_TYPE_DISPLAY_PORT:
1277 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1278 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1279 break;
1280 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1281 case SIGNAL_TYPE_DVI_DUAL_LINK:
1282 case SIGNAL_TYPE_HDMI_TYPE_A:
1283 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1284 * we can poll for bksv but some displays have an issue with this. Since its so rare
1285 * for a display to not be 1.4 capable, this assumtion is ok
1286 */
1287 ret = true;
1288 break;
1289 default:
1290 break;
1291 }
1292 return ret;
1293 }
1294
link_is_hdcp22(struct dc_link * link,enum signal_type signal)1295 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1296 {
1297 bool ret = false;
1298
1299 switch (signal) {
1300 case SIGNAL_TYPE_DISPLAY_PORT:
1301 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1302 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1303 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1304 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1305 break;
1306 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1307 case SIGNAL_TYPE_DVI_DUAL_LINK:
1308 case SIGNAL_TYPE_HDMI_TYPE_A:
1309 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1310 break;
1311 default:
1312 break;
1313 }
1314
1315 return ret;
1316 }
1317 #endif // CONFIG_DRM_AMD_DC_HDCP
1318
link_get_status(const struct dc_link * link)1319 const struct dc_link_status *link_get_status(const struct dc_link *link)
1320 {
1321 return &link->link_status;
1322 }
1323
1324