1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements dp specific link capability retrieval sequence. It is
28 * responsible for retrieving, parsing, overriding, deciding capability obtained
29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30 * usb and all other possible backend capabilities. Other components should
31 * include this header file in order to access link capability. Accessing link
32 * capability by dereferencing dc_link outside dp_link_capability is not a
33 * recommended method as it makes the component dependent on the underlying data
34 * structure used to represent link capability instead of function interfaces.
35 */
36
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link_dp_training.h"
46 #include "atomfirmware.h"
47 #include "resource.h"
48 #include "link_enc_cfg.h"
49 #include "dc_dmub_srv.h"
50 #include "gpio_service_interface.h"
51
52 #define DC_LOGGER \
53 link->ctx->logger
54 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
55
56 #ifndef MAX
57 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
58 #endif
59 #ifndef MIN
60 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
61 #endif
62
63 struct dp_lt_fallback_entry {
64 enum dc_lane_count lane_count;
65 enum dc_link_rate link_rate;
66 };
67
68 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
69 /* This link training fallback array is ordered by
70 * link bandwidth from highest to lowest.
71 * DP specs makes it a normative policy to always
72 * choose the next highest link bandwidth during
73 * link training fallback.
74 */
75 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
76 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
77 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
78 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
79 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
80 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
81 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
82 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
83 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
84 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
85 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
86 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
87 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
88 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
89 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
90 {LANE_COUNT_FOUR, LINK_RATE_LOW},
91 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
92 {LANE_COUNT_TWO, LINK_RATE_HIGH},
93 {LANE_COUNT_TWO, LINK_RATE_LOW},
94 {LANE_COUNT_ONE, LINK_RATE_HIGH},
95 {LANE_COUNT_ONE, LINK_RATE_LOW},
96 };
97
98 static const struct dc_link_settings fail_safe_link_settings = {
99 .lane_count = LANE_COUNT_ONE,
100 .link_rate = LINK_RATE_LOW,
101 .link_spread = LINK_SPREAD_DISABLED,
102 };
103
is_dp_active_dongle(const struct dc_link * link)104 bool is_dp_active_dongle(const struct dc_link *link)
105 {
106 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
107 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
108 }
109
is_dp_branch_device(const struct dc_link * link)110 bool is_dp_branch_device(const struct dc_link *link)
111 {
112 return link->dpcd_caps.is_branch_dev;
113 }
114
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)115 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
116 {
117 switch (bpc) {
118 case DOWN_STREAM_MAX_8BPC:
119 return 8;
120 case DOWN_STREAM_MAX_10BPC:
121 return 10;
122 case DOWN_STREAM_MAX_12BPC:
123 return 12;
124 case DOWN_STREAM_MAX_16BPC:
125 return 16;
126 default:
127 break;
128 }
129
130 return -1;
131 }
132
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)133 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
134 {
135 switch (lttpr_repeater_count) {
136 case 0x80: // 1 lttpr repeater
137 return 1;
138 case 0x40: // 2 lttpr repeaters
139 return 2;
140 case 0x20: // 3 lttpr repeaters
141 return 3;
142 case 0x10: // 4 lttpr repeaters
143 return 4;
144 case 0x08: // 5 lttpr repeaters
145 return 5;
146 case 0x04: // 6 lttpr repeaters
147 return 6;
148 case 0x02: // 7 lttpr repeaters
149 return 7;
150 case 0x01: // 8 lttpr repeaters
151 return 8;
152 default:
153 break;
154 }
155 return 0; // invalid value
156 }
157
dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)158 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
159 {
160 switch (bw) {
161 case 0b001:
162 return 9000000;
163 case 0b010:
164 return 18000000;
165 case 0b011:
166 return 24000000;
167 case 0b100:
168 return 32000000;
169 case 0b101:
170 return 40000000;
171 case 0b110:
172 return 48000000;
173 }
174
175 return 0;
176 }
177
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)178 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
179 {
180 enum dc_link_rate link_rate;
181 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
182 switch (link_rate_in_khz) {
183 case 1620000:
184 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
185 break;
186 case 2160000:
187 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
188 break;
189 case 2430000:
190 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
191 break;
192 case 2700000:
193 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
194 break;
195 case 3240000:
196 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane
197 break;
198 case 4320000:
199 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
200 break;
201 case 5400000:
202 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane
203 break;
204 case 8100000:
205 link_rate = LINK_RATE_HIGH3; // Rate_8 (HBR3)- 8.10 Gbps/Lane
206 break;
207 default:
208 link_rate = LINK_RATE_UNKNOWN;
209 break;
210 }
211 return link_rate;
212 }
213
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)214 static union dp_cable_id intersect_cable_id(
215 union dp_cable_id *a, union dp_cable_id *b)
216 {
217 union dp_cable_id out;
218
219 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
220 b->bits.UHBR10_20_CAPABILITY);
221 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
222 b->bits.UHBR13_5_CAPABILITY);
223 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
224
225 return out;
226 }
227
228 /*
229 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
230 */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)231 static uint32_t intersect_frl_link_bw_support(
232 const uint32_t max_supported_frl_bw_in_kbps,
233 const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
234 {
235 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
236
237 // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
238 if (hdmi_encoded_link_bw.bits.FRL_MODE) {
239 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
240 supported_bw_in_kbps = 48000000;
241 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
242 supported_bw_in_kbps = 40000000;
243 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
244 supported_bw_in_kbps = 32000000;
245 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
246 supported_bw_in_kbps = 24000000;
247 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
248 supported_bw_in_kbps = 18000000;
249 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
250 supported_bw_in_kbps = 9000000;
251 }
252
253 return supported_bw_in_kbps;
254 }
255
get_clock_source_id(struct dc_link * link)256 static enum clock_source_id get_clock_source_id(struct dc_link *link)
257 {
258 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
259 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
260
261 if (dp_cs != NULL) {
262 dp_cs_id = dp_cs->id;
263 } else {
264 /*
265 * dp clock source is not initialized for some reason.
266 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
267 */
268 ASSERT(dp_cs);
269 }
270
271 return dp_cs_id;
272 }
273
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)274 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
275 int length)
276 {
277 int retry = 0;
278
279 if (!link->dpcd_caps.dpcd_rev.raw) {
280 do {
281 dc_link_dp_receiver_power_ctrl(link, true);
282 core_link_read_dpcd(link, DP_DPCD_REV,
283 dpcd_data, length);
284 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
285 DP_DPCD_REV -
286 DP_DPCD_REV];
287 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
288 }
289
290 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
291 switch (link->dpcd_caps.branch_dev_id) {
292 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
293 * all internal circuits including AUX communication preventing
294 * reading DPCD table and EDID (spec violation).
295 * Encoder will skip DP RX power down on disable_output to
296 * keep receiver powered all the time.*/
297 case DP_BRANCH_DEVICE_ID_0010FA:
298 case DP_BRANCH_DEVICE_ID_0080E1:
299 case DP_BRANCH_DEVICE_ID_00E04C:
300 link->wa_flags.dp_keep_receiver_powered = true;
301 break;
302
303 /* TODO: May need work around for other dongles. */
304 default:
305 link->wa_flags.dp_keep_receiver_powered = false;
306 break;
307 }
308 } else
309 link->wa_flags.dp_keep_receiver_powered = false;
310 }
311
dc_link_is_fec_supported(const struct dc_link * link)312 bool dc_link_is_fec_supported(const struct dc_link *link)
313 {
314 /* TODO - use asic cap instead of link_enc->features
315 * we no longer know which link enc to use for this link before commit
316 */
317 struct link_encoder *link_enc = NULL;
318
319 link_enc = link_enc_cfg_get_link_enc(link);
320 ASSERT(link_enc);
321
322 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
323 link_enc->features.fec_supported &&
324 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
325 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
326 }
327
dc_link_should_enable_fec(const struct dc_link * link)328 bool dc_link_should_enable_fec(const struct dc_link *link)
329 {
330 bool force_disable = false;
331
332 if (link->fec_state == dc_link_fec_enabled)
333 force_disable = false;
334 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
335 link->local_sink &&
336 link->local_sink->edid_caps.panel_patch.disable_fec)
337 force_disable = true;
338 else if (link->connector_signal == SIGNAL_TYPE_EDP
339 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
340 dsc_support.DSC_SUPPORT == false
341 || link->panel_config.dsc.disable_dsc_edp
342 || !link->dc->caps.edp_dsc_support))
343 force_disable = true;
344
345 return !force_disable && dc_link_is_fec_supported(link);
346 }
347
link_is_dp_128b_132b_signal(struct pipe_ctx * pipe_ctx)348 bool link_is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
349 {
350 /* If this assert is hit then we have a link encoder dynamic management issue */
351 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
352 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
353 pipe_ctx->link_res.hpo_dp_link_enc &&
354 dc_is_dp_signal(pipe_ctx->stream->signal));
355 }
356
dp_is_lttpr_present(struct dc_link * link)357 bool dp_is_lttpr_present(struct dc_link *link)
358 {
359 return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
360 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
361 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
362 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
363 }
364
365 /* in DP compliance test, DPR-120 may have
366 * a random value in its MAX_LINK_BW dpcd field.
367 * We map it to the maximum supported link rate that
368 * is smaller than MAX_LINK_BW in this case.
369 */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)370 static enum dc_link_rate get_link_rate_from_max_link_bw(
371 uint8_t max_link_bw)
372 {
373 enum dc_link_rate link_rate;
374
375 if (max_link_bw >= LINK_RATE_HIGH3) {
376 link_rate = LINK_RATE_HIGH3;
377 } else if (max_link_bw < LINK_RATE_HIGH3
378 && max_link_bw >= LINK_RATE_HIGH2) {
379 link_rate = LINK_RATE_HIGH2;
380 } else if (max_link_bw < LINK_RATE_HIGH2
381 && max_link_bw >= LINK_RATE_HIGH) {
382 link_rate = LINK_RATE_HIGH;
383 } else if (max_link_bw < LINK_RATE_HIGH
384 && max_link_bw >= LINK_RATE_LOW) {
385 link_rate = LINK_RATE_LOW;
386 } else {
387 link_rate = LINK_RATE_UNKNOWN;
388 }
389
390 return link_rate;
391 }
392
get_lttpr_max_link_rate(struct dc_link * link)393 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
394 {
395 enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
396
397 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
398 lttpr_max_link_rate = LINK_RATE_UHBR20;
399 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
400 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
401 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
402 lttpr_max_link_rate = LINK_RATE_UHBR10;
403
404 return lttpr_max_link_rate;
405 }
406
get_cable_max_link_rate(struct dc_link * link)407 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
408 {
409 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
410
411 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
412 cable_max_link_rate = LINK_RATE_UHBR20;
413 else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
414 cable_max_link_rate = LINK_RATE_UHBR13_5;
415 else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
416 cable_max_link_rate = LINK_RATE_UHBR10;
417
418 return cable_max_link_rate;
419 }
420
reached_minimum_lane_count(enum dc_lane_count lane_count)421 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
422 {
423 return lane_count <= LANE_COUNT_ONE;
424 }
425
reached_minimum_link_rate(enum dc_link_rate link_rate)426 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
427 {
428 return link_rate <= LINK_RATE_LOW;
429 }
430
reduce_lane_count(enum dc_lane_count lane_count)431 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
432 {
433 switch (lane_count) {
434 case LANE_COUNT_FOUR:
435 return LANE_COUNT_TWO;
436 case LANE_COUNT_TWO:
437 return LANE_COUNT_ONE;
438 case LANE_COUNT_ONE:
439 return LANE_COUNT_UNKNOWN;
440 default:
441 return LANE_COUNT_UNKNOWN;
442 }
443 }
444
reduce_link_rate(enum dc_link_rate link_rate)445 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
446 {
447 switch (link_rate) {
448 case LINK_RATE_UHBR20:
449 return LINK_RATE_UHBR13_5;
450 case LINK_RATE_UHBR13_5:
451 return LINK_RATE_UHBR10;
452 case LINK_RATE_UHBR10:
453 return LINK_RATE_HIGH3;
454 case LINK_RATE_HIGH3:
455 return LINK_RATE_HIGH2;
456 case LINK_RATE_HIGH2:
457 return LINK_RATE_HIGH;
458 case LINK_RATE_HIGH:
459 return LINK_RATE_LOW;
460 case LINK_RATE_LOW:
461 return LINK_RATE_UNKNOWN;
462 default:
463 return LINK_RATE_UNKNOWN;
464 }
465 }
466
increase_lane_count(enum dc_lane_count lane_count)467 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
468 {
469 switch (lane_count) {
470 case LANE_COUNT_ONE:
471 return LANE_COUNT_TWO;
472 case LANE_COUNT_TWO:
473 return LANE_COUNT_FOUR;
474 default:
475 return LANE_COUNT_UNKNOWN;
476 }
477 }
478
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)479 static enum dc_link_rate increase_link_rate(struct dc_link *link,
480 enum dc_link_rate link_rate)
481 {
482 switch (link_rate) {
483 case LINK_RATE_LOW:
484 return LINK_RATE_HIGH;
485 case LINK_RATE_HIGH:
486 return LINK_RATE_HIGH2;
487 case LINK_RATE_HIGH2:
488 return LINK_RATE_HIGH3;
489 case LINK_RATE_HIGH3:
490 return LINK_RATE_UHBR10;
491 case LINK_RATE_UHBR10:
492 /* upto DP2.x specs UHBR13.5 is the only link rate that could be
493 * not supported by DPRX when higher link rate is supported.
494 * so we treat it as a special case for code simplicity. When we
495 * have new specs with more link rates like this, we should
496 * consider a more generic solution to handle discrete link
497 * rate capabilities.
498 */
499 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
500 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
501 case LINK_RATE_UHBR13_5:
502 return LINK_RATE_UHBR20;
503 default:
504 return LINK_RATE_UNKNOWN;
505 }
506 }
507
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)508 static bool decide_fallback_link_setting_max_bw_policy(
509 struct dc_link *link,
510 const struct dc_link_settings *max,
511 struct dc_link_settings *cur,
512 enum link_training_result training_result)
513 {
514 uint8_t cur_idx = 0, next_idx;
515 bool found = false;
516
517 if (training_result == LINK_TRAINING_ABORT)
518 return false;
519
520 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
521 /* find current index */
522 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
523 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
524 break;
525 else
526 cur_idx++;
527
528 next_idx = cur_idx + 1;
529
530 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
531 /* find next index */
532 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
533 dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
534 next_idx++;
535 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
536 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
537 /* upto DP2.x specs UHBR13.5 is the only link rate that
538 * could be not supported by DPRX when higher link rate
539 * is supported. so we treat it as a special case for
540 * code simplicity. When we have new specs with more
541 * link rates like this, we should consider a more
542 * generic solution to handle discrete link rate
543 * capabilities.
544 */
545 next_idx++;
546 else
547 break;
548
549 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
550 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
551 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
552 found = true;
553 }
554
555 return found;
556 }
557
558 /*
559 * function: set link rate and lane count fallback based
560 * on current link setting and last link training result
561 * return value:
562 * true - link setting could be set
563 * false - has reached minimum setting
564 * and no further fallback could be done
565 */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)566 bool decide_fallback_link_setting(
567 struct dc_link *link,
568 struct dc_link_settings *max,
569 struct dc_link_settings *cur,
570 enum link_training_result training_result)
571 {
572 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
573 link->dc->debug.force_dp2_lt_fallback_method)
574 return decide_fallback_link_setting_max_bw_policy(link, max,
575 cur, training_result);
576
577 switch (training_result) {
578 case LINK_TRAINING_CR_FAIL_LANE0:
579 case LINK_TRAINING_CR_FAIL_LANE1:
580 case LINK_TRAINING_CR_FAIL_LANE23:
581 case LINK_TRAINING_LQA_FAIL:
582 {
583 if (!reached_minimum_link_rate(cur->link_rate)) {
584 cur->link_rate = reduce_link_rate(cur->link_rate);
585 } else if (!reached_minimum_lane_count(cur->lane_count)) {
586 cur->link_rate = max->link_rate;
587 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
588 return false;
589 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
590 cur->lane_count = LANE_COUNT_ONE;
591 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
592 cur->lane_count = LANE_COUNT_TWO;
593 else
594 cur->lane_count = reduce_lane_count(cur->lane_count);
595 } else {
596 return false;
597 }
598 break;
599 }
600 case LINK_TRAINING_EQ_FAIL_EQ:
601 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
602 {
603 if (!reached_minimum_lane_count(cur->lane_count)) {
604 cur->lane_count = reduce_lane_count(cur->lane_count);
605 } else if (!reached_minimum_link_rate(cur->link_rate)) {
606 cur->link_rate = reduce_link_rate(cur->link_rate);
607 /* Reduce max link rate to avoid potential infinite loop.
608 * Needed so that any subsequent CR_FAIL fallback can't
609 * re-set the link rate higher than the link rate from
610 * the latest EQ_FAIL fallback.
611 */
612 max->link_rate = cur->link_rate;
613 cur->lane_count = max->lane_count;
614 } else {
615 return false;
616 }
617 break;
618 }
619 case LINK_TRAINING_EQ_FAIL_CR:
620 {
621 if (!reached_minimum_link_rate(cur->link_rate)) {
622 cur->link_rate = reduce_link_rate(cur->link_rate);
623 /* Reduce max link rate to avoid potential infinite loop.
624 * Needed so that any subsequent CR_FAIL fallback can't
625 * re-set the link rate higher than the link rate from
626 * the latest EQ_FAIL fallback.
627 */
628 max->link_rate = cur->link_rate;
629 cur->lane_count = max->lane_count;
630 } else {
631 return false;
632 }
633 break;
634 }
635 default:
636 return false;
637 }
638 return true;
639 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)640 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
641 {
642 struct dc_link_settings initial_link_setting = {
643 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
644 struct dc_link_settings current_link_setting =
645 initial_link_setting;
646 uint32_t link_bw;
647
648 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
649 return false;
650
651 /* search for the minimum link setting that:
652 * 1. is supported according to the link training result
653 * 2. could support the b/w requested by the timing
654 */
655 while (current_link_setting.link_rate <=
656 link->verified_link_cap.link_rate) {
657 link_bw = dc_link_bandwidth_kbps(
658 link,
659 ¤t_link_setting);
660 if (req_bw <= link_bw) {
661 *link_setting = current_link_setting;
662 return true;
663 }
664
665 if (current_link_setting.lane_count <
666 link->verified_link_cap.lane_count) {
667 current_link_setting.lane_count =
668 increase_lane_count(
669 current_link_setting.lane_count);
670 } else {
671 current_link_setting.link_rate =
672 increase_link_rate(link,
673 current_link_setting.link_rate);
674 current_link_setting.lane_count =
675 initial_link_setting.lane_count;
676 }
677 }
678
679 return false;
680 }
681
dc_link_decide_edp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)682 bool dc_link_decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
683 {
684 struct dc_link_settings initial_link_setting;
685 struct dc_link_settings current_link_setting;
686 uint32_t link_bw;
687
688 /*
689 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
690 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
691 */
692 if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
693 link->dpcd_caps.edp_supported_link_rates_count == 0) {
694 *link_setting = link->verified_link_cap;
695 return true;
696 }
697
698 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
699 initial_link_setting.lane_count = LANE_COUNT_ONE;
700 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
701 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
702 initial_link_setting.use_link_rate_set = true;
703 initial_link_setting.link_rate_set = 0;
704 current_link_setting = initial_link_setting;
705
706 /* search for the minimum link setting that:
707 * 1. is supported according to the link training result
708 * 2. could support the b/w requested by the timing
709 */
710 while (current_link_setting.link_rate <=
711 link->verified_link_cap.link_rate) {
712 link_bw = dc_link_bandwidth_kbps(
713 link,
714 ¤t_link_setting);
715 if (req_bw <= link_bw) {
716 *link_setting = current_link_setting;
717 return true;
718 }
719
720 if (current_link_setting.lane_count <
721 link->verified_link_cap.lane_count) {
722 current_link_setting.lane_count =
723 increase_lane_count(
724 current_link_setting.lane_count);
725 } else {
726 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
727 current_link_setting.link_rate_set++;
728 current_link_setting.link_rate =
729 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
730 current_link_setting.lane_count =
731 initial_link_setting.lane_count;
732 } else
733 break;
734 }
735 }
736 return false;
737 }
738
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)739 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
740 struct dc_link_settings *link_setting,
741 uint32_t req_bw,
742 enum dc_link_rate max_link_rate)
743 {
744 struct dc_link_settings initial_link_setting;
745 struct dc_link_settings current_link_setting;
746 uint32_t link_bw;
747
748 unsigned int policy = 0;
749
750 policy = link->panel_config.dsc.force_dsc_edp_policy;
751 if (max_link_rate == LINK_RATE_UNKNOWN)
752 max_link_rate = link->verified_link_cap.link_rate;
753 /*
754 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
755 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
756 */
757 if ((link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
758 link->dpcd_caps.edp_supported_link_rates_count == 0)) {
759 /* for DSC enabled case, we search for minimum lane count */
760 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
761 initial_link_setting.lane_count = LANE_COUNT_ONE;
762 initial_link_setting.link_rate = LINK_RATE_LOW;
763 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
764 initial_link_setting.use_link_rate_set = false;
765 initial_link_setting.link_rate_set = 0;
766 current_link_setting = initial_link_setting;
767 if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
768 return false;
769
770 /* search for the minimum link setting that:
771 * 1. is supported according to the link training result
772 * 2. could support the b/w requested by the timing
773 */
774 while (current_link_setting.link_rate <=
775 max_link_rate) {
776 link_bw = dc_link_bandwidth_kbps(
777 link,
778 ¤t_link_setting);
779 if (req_bw <= link_bw) {
780 *link_setting = current_link_setting;
781 return true;
782 }
783 if (policy) {
784 /* minimize lane */
785 if (current_link_setting.link_rate < max_link_rate) {
786 current_link_setting.link_rate =
787 increase_link_rate(link,
788 current_link_setting.link_rate);
789 } else {
790 if (current_link_setting.lane_count <
791 link->verified_link_cap.lane_count) {
792 current_link_setting.lane_count =
793 increase_lane_count(
794 current_link_setting.lane_count);
795 current_link_setting.link_rate = initial_link_setting.link_rate;
796 } else
797 break;
798 }
799 } else {
800 /* minimize link rate */
801 if (current_link_setting.lane_count <
802 link->verified_link_cap.lane_count) {
803 current_link_setting.lane_count =
804 increase_lane_count(
805 current_link_setting.lane_count);
806 } else {
807 current_link_setting.link_rate =
808 increase_link_rate(link,
809 current_link_setting.link_rate);
810 current_link_setting.lane_count =
811 initial_link_setting.lane_count;
812 }
813 }
814 }
815 return false;
816 }
817
818 /* if optimize edp link is supported */
819 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
820 initial_link_setting.lane_count = LANE_COUNT_ONE;
821 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
822 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
823 initial_link_setting.use_link_rate_set = true;
824 initial_link_setting.link_rate_set = 0;
825 current_link_setting = initial_link_setting;
826
827 /* search for the minimum link setting that:
828 * 1. is supported according to the link training result
829 * 2. could support the b/w requested by the timing
830 */
831 while (current_link_setting.link_rate <=
832 max_link_rate) {
833 link_bw = dc_link_bandwidth_kbps(
834 link,
835 ¤t_link_setting);
836 if (req_bw <= link_bw) {
837 *link_setting = current_link_setting;
838 return true;
839 }
840 if (policy) {
841 /* minimize lane */
842 if (current_link_setting.link_rate_set <
843 link->dpcd_caps.edp_supported_link_rates_count
844 && current_link_setting.link_rate < max_link_rate) {
845 current_link_setting.link_rate_set++;
846 current_link_setting.link_rate =
847 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
848 } else {
849 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
850 current_link_setting.lane_count =
851 increase_lane_count(
852 current_link_setting.lane_count);
853 current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
854 current_link_setting.link_rate =
855 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
856 } else
857 break;
858 }
859 } else {
860 /* minimize link rate */
861 if (current_link_setting.lane_count <
862 link->verified_link_cap.lane_count) {
863 current_link_setting.lane_count =
864 increase_lane_count(
865 current_link_setting.lane_count);
866 } else {
867 if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
868 current_link_setting.link_rate_set++;
869 current_link_setting.link_rate =
870 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
871 current_link_setting.lane_count =
872 initial_link_setting.lane_count;
873 } else
874 break;
875 }
876 }
877 }
878 return false;
879 }
880
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)881 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
882 {
883 *link_setting = link->verified_link_cap;
884 return true;
885 }
886
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)887 bool link_decide_link_settings(struct dc_stream_state *stream,
888 struct dc_link_settings *link_setting)
889 {
890 struct dc_link *link = stream->link;
891 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
892
893 memset(link_setting, 0, sizeof(*link_setting));
894
895 /* if preferred is specified through AMDDP, use it, if it's enough
896 * to drive the mode
897 */
898 if (link->preferred_link_setting.lane_count !=
899 LANE_COUNT_UNKNOWN &&
900 link->preferred_link_setting.link_rate !=
901 LINK_RATE_UNKNOWN) {
902 *link_setting = link->preferred_link_setting;
903 return true;
904 }
905
906 /* MST doesn't perform link training for now
907 * TODO: add MST specific link training routine
908 */
909 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
910 decide_mst_link_settings(link, link_setting);
911 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
912 /* enable edp link optimization for DSC eDP case */
913 if (stream->timing.flags.DSC) {
914 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
915
916 if (link->panel_config.dsc.force_dsc_edp_policy) {
917 /* calculate link max link rate cap*/
918 struct dc_link_settings tmp_link_setting;
919 struct dc_crtc_timing tmp_timing = stream->timing;
920 uint32_t orig_req_bw;
921
922 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
923 tmp_timing.flags.DSC = 0;
924 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing);
925 dc_link_decide_edp_link_settings(link, &tmp_link_setting, orig_req_bw);
926 max_link_rate = tmp_link_setting.link_rate;
927 }
928 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
929 } else {
930 dc_link_decide_edp_link_settings(link, link_setting, req_bw);
931 }
932 } else {
933 decide_dp_link_settings(link, link_setting, req_bw);
934 }
935
936 return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
937 link_setting->link_rate != LINK_RATE_UNKNOWN;
938 }
939
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)940 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
941 {
942 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
943 (link_settings->link_rate <= LINK_RATE_HIGH3))
944 return DP_8b_10b_ENCODING;
945 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
946 (link_settings->link_rate <= LINK_RATE_UHBR20))
947 return DP_128b_132b_ENCODING;
948 return DP_UNKNOWN_ENCODING;
949 }
950
dc_link_dp_mst_decide_link_encoding_format(const struct dc_link * link)951 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link)
952 {
953 struct dc_link_settings link_settings = {0};
954
955 if (!dc_is_dp_signal(link->connector_signal))
956 return DP_UNKNOWN_ENCODING;
957
958 if (link->preferred_link_setting.lane_count !=
959 LANE_COUNT_UNKNOWN &&
960 link->preferred_link_setting.link_rate !=
961 LINK_RATE_UNKNOWN) {
962 link_settings = link->preferred_link_setting;
963 } else {
964 decide_mst_link_settings(link, &link_settings);
965 }
966
967 return link_dp_get_encoding_format(&link_settings);
968 }
969
read_dp_device_vendor_id(struct dc_link * link)970 static void read_dp_device_vendor_id(struct dc_link *link)
971 {
972 struct dp_device_vendor_id dp_id;
973
974 /* read IEEE branch device id */
975 core_link_read_dpcd(
976 link,
977 DP_BRANCH_OUI,
978 (uint8_t *)&dp_id,
979 sizeof(dp_id));
980
981 link->dpcd_caps.branch_dev_id =
982 (dp_id.ieee_oui[0] << 16) +
983 (dp_id.ieee_oui[1] << 8) +
984 dp_id.ieee_oui[2];
985
986 memmove(
987 link->dpcd_caps.branch_dev_name,
988 dp_id.ieee_device_id,
989 sizeof(dp_id.ieee_device_id));
990 }
991
wake_up_aux_channel(struct dc_link * link)992 static enum dc_status wake_up_aux_channel(struct dc_link *link)
993 {
994 enum dc_status status = DC_ERROR_UNEXPECTED;
995 uint32_t aux_channel_retry_cnt = 0;
996 uint8_t dpcd_power_state = '\0';
997
998 while (status != DC_OK && aux_channel_retry_cnt < 10) {
999 status = core_link_read_dpcd(link, DP_SET_POWER,
1000 &dpcd_power_state, sizeof(dpcd_power_state));
1001
1002 /* Delay 1 ms if AUX CH is in power down state. Based on spec
1003 * section 2.3.1.2, if AUX CH may be powered down due to
1004 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1005 * signal and may need up to 1 ms before being able to reply.
1006 */
1007 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1008 udelay(1000);
1009 aux_channel_retry_cnt++;
1010 }
1011 }
1012
1013 if (status != DC_OK) {
1014 dpcd_power_state = DP_SET_POWER_D0;
1015 status = core_link_write_dpcd(
1016 link,
1017 DP_SET_POWER,
1018 &dpcd_power_state,
1019 sizeof(dpcd_power_state));
1020
1021 dpcd_power_state = DP_SET_POWER_D3;
1022 status = core_link_write_dpcd(
1023 link,
1024 DP_SET_POWER,
1025 &dpcd_power_state,
1026 sizeof(dpcd_power_state));
1027 return DC_ERROR_UNEXPECTED;
1028 }
1029
1030 return DC_OK;
1031 }
1032
get_active_converter_info(uint8_t data,struct dc_link * link)1033 static void get_active_converter_info(
1034 uint8_t data, struct dc_link *link)
1035 {
1036 union dp_downstream_port_present ds_port = { .byte = data };
1037 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1038
1039 /* decode converter info*/
1040 if (!ds_port.fields.PORT_PRESENT) {
1041 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1042 set_dongle_type(link->ddc,
1043 link->dpcd_caps.dongle_type);
1044 link->dpcd_caps.is_branch_dev = false;
1045 return;
1046 }
1047
1048 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1049 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1050
1051 switch (ds_port.fields.PORT_TYPE) {
1052 case DOWNSTREAM_VGA:
1053 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1054 break;
1055 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1056 /* At this point we don't know is it DVI or HDMI or DP++,
1057 * assume DVI.*/
1058 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1059 break;
1060 default:
1061 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1062 break;
1063 }
1064
1065 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1066 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1067 union dwnstream_port_caps_byte0 *port_caps =
1068 (union dwnstream_port_caps_byte0 *)det_caps;
1069 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1070 det_caps, sizeof(det_caps)) == DC_OK) {
1071
1072 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1073 /*Handle DP case as DONGLE_NONE*/
1074 case DOWN_STREAM_DETAILED_DP:
1075 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1076 break;
1077 case DOWN_STREAM_DETAILED_VGA:
1078 link->dpcd_caps.dongle_type =
1079 DISPLAY_DONGLE_DP_VGA_CONVERTER;
1080 break;
1081 case DOWN_STREAM_DETAILED_DVI:
1082 link->dpcd_caps.dongle_type =
1083 DISPLAY_DONGLE_DP_DVI_CONVERTER;
1084 break;
1085 case DOWN_STREAM_DETAILED_HDMI:
1086 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1087 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1088 link->dpcd_caps.dongle_type =
1089 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1090
1091 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1092 if (ds_port.fields.DETAILED_CAPS) {
1093
1094 union dwnstream_port_caps_byte3_hdmi
1095 hdmi_caps = {.raw = det_caps[3] };
1096 union dwnstream_port_caps_byte2
1097 hdmi_color_caps = {.raw = det_caps[2] };
1098 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1099 det_caps[1] * 2500;
1100
1101 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1102 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1103 /*YCBCR capability only for HDMI case*/
1104 if (port_caps->bits.DWN_STRM_PORTX_TYPE
1105 == DOWN_STREAM_DETAILED_HDMI) {
1106 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1107 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1108 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1109 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1110 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1111 hdmi_caps.bits.YCrCr422_CONVERSION;
1112 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1113 hdmi_caps.bits.YCrCr420_CONVERSION;
1114 }
1115
1116 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1117 translate_dpcd_max_bpc(
1118 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1119
1120 if (link->dc->caps.dp_hdmi21_pcon_support) {
1121 union hdmi_encoded_link_bw hdmi_encoded_link_bw;
1122
1123 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1124 dc_link_bw_kbps_from_raw_frl_link_rate_data(
1125 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1126
1127 // Intersect reported max link bw support with the supported link rate post FRL link training
1128 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1129 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1130 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1131 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1132 hdmi_encoded_link_bw);
1133 }
1134
1135 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1136 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1137 }
1138
1139 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1140 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1141 }
1142
1143 break;
1144 }
1145 }
1146 }
1147
1148 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1149
1150 {
1151 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1152
1153 core_link_read_dpcd(
1154 link,
1155 DP_BRANCH_REVISION_START,
1156 (uint8_t *)&dp_hw_fw_revision,
1157 sizeof(dp_hw_fw_revision));
1158
1159 link->dpcd_caps.branch_hw_revision =
1160 dp_hw_fw_revision.ieee_hw_rev;
1161
1162 memmove(
1163 link->dpcd_caps.branch_fw_revision,
1164 dp_hw_fw_revision.ieee_fw_rev,
1165 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1166 }
1167 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1168 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1169 union dp_dfp_cap_ext dfp_cap_ext;
1170 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1171 core_link_read_dpcd(
1172 link,
1173 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1174 dfp_cap_ext.raw,
1175 sizeof(dfp_cap_ext.raw));
1176 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1177 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1178 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1179 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1180 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1181 dfp_cap_ext.fields.max_video_h_active_width[0] +
1182 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1183 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1184 dfp_cap_ext.fields.max_video_v_active_height[0] +
1185 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1186 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1187 dfp_cap_ext.fields.encoding_format_caps;
1188 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1189 dfp_cap_ext.fields.rgb_color_depth_caps;
1190 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1191 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1192 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1193 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1194 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1195 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1196 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1197 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1198 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1199 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1200 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1201 }
1202 }
1203
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1204 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1205 struct dc_link_settings *link_settings)
1206 {
1207 /* Temporary Renoir-specific workaround PHY will sometimes be in bad
1208 * state on hotplugging display from certain USB-C dongle, so add extra
1209 * cycle of enabling and disabling the PHY before first link training.
1210 */
1211 struct link_resource link_res = {0};
1212 enum clock_source_id dp_cs_id = get_clock_source_id(link);
1213
1214 dp_enable_link_phy(link, &link_res, link->connector_signal,
1215 dp_cs_id, link_settings);
1216 dp_disable_link_phy(link, &link_res, link->connector_signal);
1217 }
1218
dp_overwrite_extended_receiver_cap(struct dc_link * link)1219 static bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1220 {
1221 uint8_t dpcd_data[16];
1222 uint32_t read_dpcd_retry_cnt = 3;
1223 enum dc_status status = DC_ERROR_UNEXPECTED;
1224 union dp_downstream_port_present ds_port = { 0 };
1225 union down_stream_port_count down_strm_port_count;
1226 union edp_configuration_cap edp_config_cap;
1227
1228 int i;
1229
1230 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1231 status = core_link_read_dpcd(
1232 link,
1233 DP_DPCD_REV,
1234 dpcd_data,
1235 sizeof(dpcd_data));
1236 if (status == DC_OK)
1237 break;
1238 }
1239
1240 link->dpcd_caps.dpcd_rev.raw =
1241 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1242
1243 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1244 return false;
1245
1246 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1247 DP_DPCD_REV];
1248
1249 get_active_converter_info(ds_port.byte, link);
1250
1251 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1252 DP_DPCD_REV];
1253
1254 link->dpcd_caps.allow_invalid_MSA_timing_param =
1255 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1256
1257 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1258 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1259
1260 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1261 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1262
1263 link->reported_link_cap.lane_count =
1264 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1265 link->reported_link_cap.link_rate = dpcd_data[
1266 DP_MAX_LINK_RATE - DP_DPCD_REV];
1267 link->reported_link_cap.link_spread =
1268 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1269 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1270
1271 edp_config_cap.raw = dpcd_data[
1272 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1273 link->dpcd_caps.panel_mode_edp =
1274 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1275 link->dpcd_caps.dpcd_display_control_capable =
1276 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1277
1278 return true;
1279 }
1280
dc_link_overwrite_extended_receiver_cap(struct dc_link * link)1281 void dc_link_overwrite_extended_receiver_cap(
1282 struct dc_link *link)
1283 {
1284 dp_overwrite_extended_receiver_cap(link);
1285 }
1286
dpcd_set_source_specific_data(struct dc_link * link)1287 void dpcd_set_source_specific_data(struct dc_link *link)
1288 {
1289 if (!link->dc->vendor_signature.is_valid) {
1290 enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
1291 struct dpcd_amd_signature amd_signature = {0};
1292 struct dpcd_amd_device_id amd_device_id = {0};
1293
1294 amd_device_id.device_id_byte1 =
1295 (uint8_t)(link->ctx->asic_id.chip_id);
1296 amd_device_id.device_id_byte2 =
1297 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
1298 amd_device_id.dce_version =
1299 (uint8_t)(link->ctx->dce_version);
1300 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1301 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1302
1303 core_link_read_dpcd(link, DP_SOURCE_OUI,
1304 (uint8_t *)(&amd_signature),
1305 sizeof(amd_signature));
1306
1307 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1308 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1309 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1310
1311 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1312 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1313 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1314
1315 core_link_write_dpcd(link, DP_SOURCE_OUI,
1316 (uint8_t *)(&amd_signature),
1317 sizeof(amd_signature));
1318 }
1319
1320 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1321 (uint8_t *)(&amd_device_id),
1322 sizeof(amd_device_id));
1323
1324 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1325 link->dc->caps.min_horizontal_blanking_period != 0) {
1326
1327 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1328
1329 result_write_min_hblank = core_link_write_dpcd(link,
1330 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1331 sizeof(hblank_size));
1332 }
1333 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1334 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1335 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1336 result_write_min_hblank,
1337 link->link_index,
1338 link->ctx->dce_version,
1339 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1340 link->dc->caps.min_horizontal_blanking_period,
1341 link->dpcd_caps.branch_dev_id,
1342 link->dpcd_caps.branch_dev_name[0],
1343 link->dpcd_caps.branch_dev_name[1],
1344 link->dpcd_caps.branch_dev_name[2],
1345 link->dpcd_caps.branch_dev_name[3],
1346 link->dpcd_caps.branch_dev_name[4],
1347 link->dpcd_caps.branch_dev_name[5]);
1348 } else {
1349 core_link_write_dpcd(link, DP_SOURCE_OUI,
1350 link->dc->vendor_signature.data.raw,
1351 sizeof(link->dc->vendor_signature.data.raw));
1352 }
1353 }
1354
dpcd_write_cable_id_to_dprx(struct dc_link * link)1355 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1356 {
1357 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1358 link->dpcd_caps.cable_id.raw == 0 ||
1359 link->dprx_states.cable_id_written)
1360 return;
1361
1362 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1363 &link->dpcd_caps.cable_id.raw,
1364 sizeof(link->dpcd_caps.cable_id.raw));
1365
1366 link->dprx_states.cable_id_written = 1;
1367 }
1368
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1369 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1370 {
1371 union dmub_rb_cmd cmd;
1372
1373 if (!link->ctx->dmub_srv ||
1374 link->ep_type != DISPLAY_ENDPOINT_PHY ||
1375 link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1376 return false;
1377
1378 memset(&cmd, 0, sizeof(cmd));
1379 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1380 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1381 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1382 link->dc, link->link_enc->transmitter);
1383 if (dc_dmub_srv_cmd_with_reply_data(link->ctx->dmub_srv, &cmd) &&
1384 cmd.cable_id.header.ret_status == 1) {
1385 cable_id->raw = cmd.cable_id.data.output_raw;
1386 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1387 }
1388 return cmd.cable_id.header.ret_status == 1;
1389 }
1390
retrieve_cable_id(struct dc_link * link)1391 static void retrieve_cable_id(struct dc_link *link)
1392 {
1393 union dp_cable_id usbc_cable_id;
1394
1395 link->dpcd_caps.cable_id.raw = 0;
1396 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1397 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1398
1399 if (get_usbc_cable_id(link, &usbc_cable_id))
1400 link->dpcd_caps.cable_id = intersect_cable_id(
1401 &link->dpcd_caps.cable_id, &usbc_cable_id);
1402 }
1403
read_is_mst_supported(struct dc_link * link)1404 bool read_is_mst_supported(struct dc_link *link)
1405 {
1406 bool mst = false;
1407 enum dc_status st = DC_OK;
1408 union dpcd_rev rev;
1409 union mstm_cap cap;
1410
1411 if (link->preferred_training_settings.mst_enable &&
1412 *link->preferred_training_settings.mst_enable == false) {
1413 return false;
1414 }
1415
1416 rev.raw = 0;
1417 cap.raw = 0;
1418
1419 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1420 sizeof(rev));
1421
1422 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1423
1424 st = core_link_read_dpcd(link, DP_MSTM_CAP,
1425 &cap.raw, sizeof(cap));
1426 if (st == DC_OK && cap.bits.MST_CAP == 1)
1427 mst = true;
1428 }
1429 return mst;
1430
1431 }
1432
1433 /* Read additional sink caps defined in source specific DPCD area
1434 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1435 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1436 */
dpcd_read_sink_ext_caps(struct dc_link * link)1437 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1438 {
1439 uint8_t dpcd_data;
1440
1441 if (!link)
1442 return false;
1443
1444 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1445 return false;
1446
1447 link->dpcd_sink_ext_caps.raw = dpcd_data;
1448 return true;
1449 }
1450
dp_retrieve_lttpr_cap(struct dc_link * link)1451 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1452 {
1453 uint8_t lttpr_dpcd_data[8];
1454 enum dc_status status;
1455 bool is_lttpr_present;
1456
1457 /* Logic to determine LTTPR support*/
1458 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1459
1460 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1461 return DC_NOT_SUPPORTED;
1462
1463 /* By reading LTTPR capability, RX assumes that we will enable
1464 * LTTPR extended aux timeout if LTTPR is present.
1465 */
1466 status = core_link_read_dpcd(
1467 link,
1468 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1469 lttpr_dpcd_data,
1470 sizeof(lttpr_dpcd_data));
1471
1472 link->dpcd_caps.lttpr_caps.revision.raw =
1473 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1474 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1475
1476 link->dpcd_caps.lttpr_caps.max_link_rate =
1477 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1478 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1479
1480 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1481 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1482 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1483
1484 link->dpcd_caps.lttpr_caps.max_lane_count =
1485 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1486 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1487
1488 link->dpcd_caps.lttpr_caps.mode =
1489 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1490 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1491
1492 link->dpcd_caps.lttpr_caps.max_ext_timeout =
1493 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1494 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1495 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1496 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1497 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1498
1499 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1500 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1501 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1502
1503 /* If this chip cap is set, at least one retimer must exist in the chain
1504 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1505 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1506 (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1507 ASSERT(0);
1508 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1509 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1510 }
1511
1512 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1513 is_lttpr_present = dp_is_lttpr_present(link);
1514
1515 if (is_lttpr_present)
1516 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1517
1518 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1519 return status;
1520 }
1521
retrieve_link_cap(struct dc_link * link)1522 static bool retrieve_link_cap(struct dc_link *link)
1523 {
1524 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1525 * which means size 16 will be good for both of those DPCD register block reads
1526 */
1527 uint8_t dpcd_data[16];
1528 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1529 */
1530 uint8_t dpcd_dprx_data = '\0';
1531
1532 struct dp_device_vendor_id sink_id;
1533 union down_stream_port_count down_strm_port_count;
1534 union edp_configuration_cap edp_config_cap;
1535 union dp_downstream_port_present ds_port = { 0 };
1536 enum dc_status status = DC_ERROR_UNEXPECTED;
1537 uint32_t read_dpcd_retry_cnt = 3;
1538 int i;
1539 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1540 const uint32_t post_oui_delay = 30; // 30ms
1541
1542 memset(dpcd_data, '\0', sizeof(dpcd_data));
1543 memset(&down_strm_port_count,
1544 '\0', sizeof(union down_stream_port_count));
1545 memset(&edp_config_cap, '\0',
1546 sizeof(union edp_configuration_cap));
1547
1548 /* if extended timeout is supported in hardware,
1549 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1550 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1551 */
1552 try_to_configure_aux_timeout(link->ddc,
1553 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1554
1555 status = dp_retrieve_lttpr_cap(link);
1556
1557 if (status != DC_OK) {
1558 status = wake_up_aux_channel(link);
1559 if (status == DC_OK)
1560 dp_retrieve_lttpr_cap(link);
1561 else
1562 return false;
1563 }
1564
1565 if (dp_is_lttpr_present(link))
1566 configure_lttpr_mode_transparent(link);
1567
1568 /* Read DP tunneling information. */
1569 status = dpcd_get_tunneling_device_data(link);
1570
1571 dpcd_set_source_specific_data(link);
1572 /* Sink may need to configure internals based on vendor, so allow some
1573 * time before proceeding with possibly vendor specific transactions
1574 */
1575 msleep(post_oui_delay);
1576
1577 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1578 status = core_link_read_dpcd(
1579 link,
1580 DP_DPCD_REV,
1581 dpcd_data,
1582 sizeof(dpcd_data));
1583 if (status == DC_OK)
1584 break;
1585 }
1586
1587
1588 if (status != DC_OK) {
1589 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1590 return false;
1591 }
1592
1593 if (!dp_is_lttpr_present(link))
1594 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1595
1596
1597 {
1598 union training_aux_rd_interval aux_rd_interval;
1599
1600 aux_rd_interval.raw =
1601 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1602
1603 link->dpcd_caps.ext_receiver_cap_field_present =
1604 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1605
1606 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1607 uint8_t ext_cap_data[16];
1608
1609 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1610 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1611 status = core_link_read_dpcd(
1612 link,
1613 DP_DP13_DPCD_REV,
1614 ext_cap_data,
1615 sizeof(ext_cap_data));
1616 if (status == DC_OK) {
1617 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1618 break;
1619 }
1620 }
1621 if (status != DC_OK)
1622 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1623 }
1624 }
1625
1626 link->dpcd_caps.dpcd_rev.raw =
1627 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1628
1629 if (link->dpcd_caps.ext_receiver_cap_field_present) {
1630 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1631 status = core_link_read_dpcd(
1632 link,
1633 DP_DPRX_FEATURE_ENUMERATION_LIST,
1634 &dpcd_dprx_data,
1635 sizeof(dpcd_dprx_data));
1636 if (status == DC_OK)
1637 break;
1638 }
1639
1640 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1641
1642 if (status != DC_OK)
1643 dm_error("%s: Read DPRX caps data failed.\n", __func__);
1644
1645 /* AdaptiveSyncCapability */
1646 dpcd_dprx_data = 0;
1647 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1648 status = core_link_read_dpcd(
1649 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1650 &dpcd_dprx_data, sizeof(dpcd_dprx_data));
1651 if (status == DC_OK)
1652 break;
1653 }
1654
1655 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1656
1657 if (status != DC_OK)
1658 dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",
1659 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1660 }
1661
1662 else {
1663 link->dpcd_caps.dprx_feature.raw = 0;
1664 }
1665
1666
1667 /* Error condition checking...
1668 * It is impossible for Sink to report Max Lane Count = 0.
1669 * It is possible for Sink to report Max Link Rate = 0, if it is
1670 * an eDP device that is reporting specialized link rates in the
1671 * SUPPORTED_LINK_RATE table.
1672 */
1673 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1674 return false;
1675
1676 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1677 DP_DPCD_REV];
1678
1679 read_dp_device_vendor_id(link);
1680
1681 /* TODO - decouple raw mst capability from policy decision */
1682 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1683
1684 get_active_converter_info(ds_port.byte, link);
1685
1686 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1687
1688 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1689 DP_DPCD_REV];
1690
1691 link->dpcd_caps.allow_invalid_MSA_timing_param =
1692 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1693
1694 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1695 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1696
1697 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1698 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1699
1700 link->reported_link_cap.lane_count =
1701 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1702 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1703 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1704 link->reported_link_cap.link_spread =
1705 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1706 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1707
1708 edp_config_cap.raw = dpcd_data[
1709 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1710 link->dpcd_caps.panel_mode_edp =
1711 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1712 link->dpcd_caps.dpcd_display_control_capable =
1713 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1714 link->dpcd_caps.channel_coding_cap.raw =
1715 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1716 link->test_pattern_enabled = false;
1717 link->compliance_test_state.raw = 0;
1718
1719 /* read sink count */
1720 core_link_read_dpcd(link,
1721 DP_SINK_COUNT,
1722 &link->dpcd_caps.sink_count.raw,
1723 sizeof(link->dpcd_caps.sink_count.raw));
1724
1725 /* read sink ieee oui */
1726 core_link_read_dpcd(link,
1727 DP_SINK_OUI,
1728 (uint8_t *)(&sink_id),
1729 sizeof(sink_id));
1730
1731 link->dpcd_caps.sink_dev_id =
1732 (sink_id.ieee_oui[0] << 16) +
1733 (sink_id.ieee_oui[1] << 8) +
1734 (sink_id.ieee_oui[2]);
1735
1736 memmove(
1737 link->dpcd_caps.sink_dev_id_str,
1738 sink_id.ieee_device_id,
1739 sizeof(sink_id.ieee_device_id));
1740
1741 core_link_read_dpcd(
1742 link,
1743 DP_SINK_HW_REVISION_START,
1744 (uint8_t *)&dp_hw_fw_revision,
1745 sizeof(dp_hw_fw_revision));
1746
1747 link->dpcd_caps.sink_hw_revision =
1748 dp_hw_fw_revision.ieee_hw_rev;
1749
1750 memmove(
1751 link->dpcd_caps.sink_fw_revision,
1752 dp_hw_fw_revision.ieee_fw_rev,
1753 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1754
1755 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1756 {
1757 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1758 uint8_t fwrev_mbp_2018[] = { 7, 4 };
1759 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1760
1761 /* We also check for the firmware revision as 16,1 models have an
1762 * identical device id and are incorrectly quirked otherwise.
1763 */
1764 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1765 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1766 sizeof(str_mbp_2018)) &&
1767 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1768 sizeof(fwrev_mbp_2018)) ||
1769 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1770 sizeof(fwrev_mbp_2018_vega)))) {
1771 link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1772 }
1773 }
1774
1775 memset(&link->dpcd_caps.dsc_caps, '\0',
1776 sizeof(link->dpcd_caps.dsc_caps));
1777 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1778 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1779 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1780 status = core_link_read_dpcd(
1781 link,
1782 DP_FEC_CAPABILITY,
1783 &link->dpcd_caps.fec_cap.raw,
1784 sizeof(link->dpcd_caps.fec_cap.raw));
1785 status = core_link_read_dpcd(
1786 link,
1787 DP_DSC_SUPPORT,
1788 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1789 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1790 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1791 status = core_link_read_dpcd(
1792 link,
1793 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1794 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1795 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1796 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1797 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1798 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1799 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1800 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1801 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1802 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1803 }
1804
1805 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1806 * only if required.
1807 */
1808 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1809 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1810 link->dpcd_caps.is_branch_dev &&
1811 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1812 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1813 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1814 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1815 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1816 * Clear FEC and DSC capabilities as a work around if that is not the case.
1817 */
1818 link->wa_flags.dpia_forced_tbt3_mode = true;
1819 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1820 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1821 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1822 } else
1823 link->wa_flags.dpia_forced_tbt3_mode = false;
1824 }
1825
1826 if (!dpcd_read_sink_ext_caps(link))
1827 link->dpcd_sink_ext_caps.raw = 0;
1828
1829 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1830 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1831
1832 core_link_read_dpcd(link,
1833 DP_128B132B_SUPPORTED_LINK_RATES,
1834 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1835 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1836 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1837 link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1838 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1839 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1840 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1841 link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1842 else
1843 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1844 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1845 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1846 link->reported_link_cap.link_rate / 100,
1847 link->reported_link_cap.link_rate % 100);
1848
1849 core_link_read_dpcd(link,
1850 DP_SINK_VIDEO_FALLBACK_FORMATS,
1851 &link->dpcd_caps.fallback_formats.raw,
1852 sizeof(link->dpcd_caps.fallback_formats.raw));
1853 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1854 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1855 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1856 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1857 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1858 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1859 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1860 if (link->dpcd_caps.fallback_formats.raw == 0) {
1861 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1862 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1863 }
1864
1865 core_link_read_dpcd(link,
1866 DP_FEC_CAPABILITY_1,
1867 &link->dpcd_caps.fec_cap1.raw,
1868 sizeof(link->dpcd_caps.fec_cap1.raw));
1869 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
1870 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
1871 DC_LOG_DP2("\tFEC aggregated error counters are supported");
1872 }
1873
1874 retrieve_cable_id(link);
1875 dpcd_write_cable_id_to_dprx(link);
1876
1877 /* Connectivity log: detection */
1878 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
1879
1880 return true;
1881 }
1882
detect_dp_sink_caps(struct dc_link * link)1883 bool detect_dp_sink_caps(struct dc_link *link)
1884 {
1885 return retrieve_link_cap(link);
1886 }
1887
detect_edp_sink_caps(struct dc_link * link)1888 void detect_edp_sink_caps(struct dc_link *link)
1889 {
1890 uint8_t supported_link_rates[16];
1891 uint32_t entry;
1892 uint32_t link_rate_in_khz;
1893 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
1894 uint8_t backlight_adj_cap;
1895 uint8_t general_edp_cap;
1896
1897 retrieve_link_cap(link);
1898 link->dpcd_caps.edp_supported_link_rates_count = 0;
1899 memset(supported_link_rates, 0, sizeof(supported_link_rates));
1900
1901 /*
1902 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
1903 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
1904 */
1905 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
1906 (link->panel_config.ilr.optimize_edp_link_rate ||
1907 link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
1908 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
1909 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1910 supported_link_rates, sizeof(supported_link_rates));
1911
1912 for (entry = 0; entry < 16; entry += 2) {
1913 // DPCD register reports per-lane link rate = 16-bit link rate capability
1914 // value X 200 kHz. Need multiplier to find link rate in kHz.
1915 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
1916 supported_link_rates[entry]) * 200;
1917
1918 if (link_rate_in_khz != 0) {
1919 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
1920 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
1921 link->dpcd_caps.edp_supported_link_rates_count++;
1922
1923 if (link->reported_link_cap.link_rate < link_rate)
1924 link->reported_link_cap.link_rate = link_rate;
1925 }
1926 }
1927 }
1928 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
1929 &backlight_adj_cap, sizeof(backlight_adj_cap));
1930
1931 link->dpcd_caps.dynamic_backlight_capable_edp =
1932 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
1933
1934 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
1935 &general_edp_cap, sizeof(general_edp_cap));
1936
1937 link->dpcd_caps.set_power_state_capable_edp =
1938 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
1939
1940 set_default_brightness_aux(link);
1941
1942 core_link_read_dpcd(link, DP_EDP_DPCD_REV,
1943 &link->dpcd_caps.edp_rev,
1944 sizeof(link->dpcd_caps.edp_rev));
1945 /*
1946 * PSR is only valid for eDP v1.3 or higher.
1947 */
1948 if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
1949 core_link_read_dpcd(link, DP_PSR_SUPPORT,
1950 &link->dpcd_caps.psr_info.psr_version,
1951 sizeof(link->dpcd_caps.psr_info.psr_version));
1952 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
1953 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
1954 &link->dpcd_caps.psr_info.force_psrsu_cap,
1955 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
1956 core_link_read_dpcd(link, DP_PSR_CAPS,
1957 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
1958 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
1959 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
1960 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
1961 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
1962 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
1963 }
1964 }
1965
1966 /*
1967 * ALPM is only valid for eDP v1.4 or higher.
1968 */
1969 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
1970 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
1971 &link->dpcd_caps.alpm_caps.raw,
1972 sizeof(link->dpcd_caps.alpm_caps.raw));
1973 }
1974
dc_link_dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)1975 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
1976 {
1977 struct link_encoder *link_enc = NULL;
1978
1979 if (!max_link_enc_cap) {
1980 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
1981 return false;
1982 }
1983
1984 link_enc = link_enc_cfg_get_link_enc(link);
1985 ASSERT(link_enc);
1986
1987 if (link_enc && link_enc->funcs->get_max_link_cap) {
1988 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
1989 return true;
1990 }
1991
1992 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
1993 max_link_enc_cap->lane_count = 1;
1994 max_link_enc_cap->link_rate = 6;
1995 return false;
1996 }
1997
dc_link_get_link_cap(const struct dc_link * link)1998 const struct dc_link_settings *dc_link_get_link_cap(
1999 const struct dc_link *link)
2000 {
2001 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2002 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2003 return &link->preferred_link_setting;
2004 return &link->verified_link_cap;
2005 }
2006
dp_get_max_link_cap(struct dc_link * link)2007 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2008 {
2009 struct dc_link_settings max_link_cap = {0};
2010 enum dc_link_rate lttpr_max_link_rate;
2011 enum dc_link_rate cable_max_link_rate;
2012 struct link_encoder *link_enc = NULL;
2013
2014
2015 link_enc = link_enc_cfg_get_link_enc(link);
2016 ASSERT(link_enc);
2017
2018 /* get max link encoder capability */
2019 if (link_enc)
2020 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2021
2022 /* Lower link settings based on sink's link cap */
2023 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2024 max_link_cap.lane_count =
2025 link->reported_link_cap.lane_count;
2026 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2027 max_link_cap.link_rate =
2028 link->reported_link_cap.link_rate;
2029 if (link->reported_link_cap.link_spread <
2030 max_link_cap.link_spread)
2031 max_link_cap.link_spread =
2032 link->reported_link_cap.link_spread;
2033
2034 /* Lower link settings based on cable attributes
2035 * Cable ID is a DP2 feature to identify max certified link rate that
2036 * a cable can carry. The cable identification method requires both
2037 * cable and display hardware support. Since the specs comes late, it is
2038 * anticipated that the first round of DP2 cables and displays may not
2039 * be fully compatible to reliably return cable ID data. Therefore the
2040 * decision of our cable id policy is that if the cable can return non
2041 * zero cable id data, we will take cable's link rate capability into
2042 * account. However if we get zero data, the cable link rate capability
2043 * is considered inconclusive. In this case, we will not take cable's
2044 * capability into account to avoid of over limiting hardware capability
2045 * from users. The max overall link rate capability is still determined
2046 * after actual dp pre-training. Cable id is considered as an auxiliary
2047 * method of determining max link bandwidth capability.
2048 */
2049 cable_max_link_rate = get_cable_max_link_rate(link);
2050
2051 if (!link->dc->debug.ignore_cable_id &&
2052 cable_max_link_rate != LINK_RATE_UNKNOWN &&
2053 cable_max_link_rate < max_link_cap.link_rate)
2054 max_link_cap.link_rate = cable_max_link_rate;
2055
2056 /* account for lttpr repeaters cap
2057 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2058 */
2059 if (dp_is_lttpr_present(link)) {
2060 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2061 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2062 lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2063
2064 if (lttpr_max_link_rate < max_link_cap.link_rate)
2065 max_link_cap.link_rate = lttpr_max_link_rate;
2066
2067 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2068 __func__,
2069 max_link_cap.lane_count,
2070 max_link_cap.link_rate);
2071 }
2072
2073 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2074 link->dc->debug.disable_uhbr)
2075 max_link_cap.link_rate = LINK_RATE_HIGH3;
2076
2077 return max_link_cap;
2078 }
2079
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2080 static bool dp_verify_link_cap(
2081 struct dc_link *link,
2082 struct dc_link_settings *known_limit_link_setting,
2083 int *fail_count)
2084 {
2085 struct dc_link_settings cur_link_settings = {0};
2086 struct dc_link_settings max_link_settings = *known_limit_link_setting;
2087 bool success = false;
2088 bool skip_video_pattern;
2089 enum clock_source_id dp_cs_id = get_clock_source_id(link);
2090 enum link_training_result status = LINK_TRAINING_SUCCESS;
2091 union hpd_irq_data irq_data;
2092 struct link_resource link_res;
2093
2094 memset(&irq_data, 0, sizeof(irq_data));
2095 cur_link_settings = max_link_settings;
2096
2097 /* Grant extended timeout request */
2098 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2099 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2100
2101 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2102 }
2103
2104 do {
2105 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2106 continue;
2107
2108 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2109 dp_enable_link_phy(
2110 link,
2111 &link_res,
2112 link->connector_signal,
2113 dp_cs_id,
2114 &cur_link_settings);
2115
2116 status = dp_perform_link_training(
2117 link,
2118 &link_res,
2119 &cur_link_settings,
2120 skip_video_pattern);
2121
2122 if (status == LINK_TRAINING_SUCCESS) {
2123 success = true;
2124 udelay(1000);
2125 if (dc_link_dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2126 dc_link_check_link_loss_status(
2127 link,
2128 &irq_data))
2129 (*fail_count)++;
2130
2131 } else {
2132 (*fail_count)++;
2133 }
2134 dp_trace_lt_total_count_increment(link, true);
2135 dp_trace_lt_result_update(link, status, true);
2136 dp_disable_link_phy(link, &link_res, link->connector_signal);
2137 } while (!success && decide_fallback_link_setting(link,
2138 &max_link_settings, &cur_link_settings, status));
2139
2140 link->verified_link_cap = success ?
2141 cur_link_settings : fail_safe_link_settings;
2142 return success;
2143 }
2144
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2145 bool dp_verify_link_cap_with_retries(
2146 struct dc_link *link,
2147 struct dc_link_settings *known_limit_link_setting,
2148 int attempts)
2149 {
2150 int i = 0;
2151 bool success = false;
2152 int fail_count = 0;
2153
2154 dp_trace_detect_lt_init(link);
2155
2156 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2157 link->dc->debug.usbc_combo_phy_reset_wa)
2158 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2159
2160 dp_trace_set_lt_start_timestamp(link, false);
2161 for (i = 0; i < attempts; i++) {
2162 enum dc_connection_type type = dc_connection_none;
2163
2164 memset(&link->verified_link_cap, 0,
2165 sizeof(struct dc_link_settings));
2166 if (!dc_link_detect_connection_type(link, &type) || type == dc_connection_none) {
2167 link->verified_link_cap = fail_safe_link_settings;
2168 break;
2169 } else if (dp_verify_link_cap(link, known_limit_link_setting,
2170 &fail_count) && fail_count == 0) {
2171 success = true;
2172 break;
2173 }
2174 msleep(10);
2175 }
2176
2177 dp_trace_lt_fail_count_update(link, fail_count, true);
2178 dp_trace_set_lt_end_timestamp(link, true);
2179
2180 return success;
2181 }
2182
2183 /**
2184 * dc_link_is_dp_sink_present() - Check if there is a native DP
2185 * or passive DP-HDMI dongle connected
2186 */
dc_link_is_dp_sink_present(struct dc_link * link)2187 bool dc_link_is_dp_sink_present(struct dc_link *link)
2188 {
2189 enum gpio_result gpio_result;
2190 uint32_t clock_pin = 0;
2191 uint8_t retry = 0;
2192 struct ddc *ddc;
2193
2194 enum connector_id connector_id =
2195 dal_graphics_object_id_get_connector_id(link->link_id);
2196
2197 bool present =
2198 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2199 (connector_id == CONNECTOR_ID_EDP) ||
2200 (connector_id == CONNECTOR_ID_USBC));
2201
2202 ddc = get_ddc_pin(link->ddc);
2203
2204 if (!ddc) {
2205 BREAK_TO_DEBUGGER();
2206 return present;
2207 }
2208
2209 /* Open GPIO and set it to I2C mode */
2210 /* Note: this GpioMode_Input will be converted
2211 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2212 * which indicates we need additional delay
2213 */
2214
2215 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2216 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2217 dal_ddc_close(ddc);
2218
2219 return present;
2220 }
2221
2222 /*
2223 * Read GPIO: DP sink is present if both clock and data pins are zero
2224 *
2225 * [W/A] plug-unplug DP cable, sometimes customer board has
2226 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2227 * then monitor can't br light up. Add retry 3 times
2228 * But in real passive dongle, it need additional 3ms to detect
2229 */
2230 do {
2231 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2232 ASSERT(gpio_result == GPIO_RESULT_OK);
2233 if (clock_pin)
2234 udelay(1000);
2235 else
2236 break;
2237 } while (retry++ < 3);
2238
2239 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2240
2241 dal_ddc_close(ddc);
2242
2243 return present;
2244 }
2245