1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/init.h>
3 #include <linux/suspend.h>
4 #include <linux/of_address.h>
5
6 #include <asm/io.h>
7 #include <asm/time.h>
8 #include <asm/mpc52xx.h>
9 #include <asm/switch_to.h>
10
11 /* defined in lite5200_sleep.S and only used here */
12 extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
13
14 static struct mpc52xx_cdm __iomem *cdm;
15 static struct mpc52xx_intr __iomem *pic;
16 static struct mpc52xx_sdma __iomem *bes;
17 static struct mpc52xx_xlb __iomem *xlb;
18 static struct mpc52xx_gpio __iomem *gps;
19 static struct mpc52xx_gpio_wkup __iomem *gpw;
20 static void __iomem *pci;
21 static void __iomem *sram;
22 static const int sram_size = 0x4000; /* 16 kBytes */
23 static void __iomem *mbar;
24
25 static suspend_state_t lite5200_pm_target_state;
26
lite5200_pm_valid(suspend_state_t state)27 static int lite5200_pm_valid(suspend_state_t state)
28 {
29 switch (state) {
30 case PM_SUSPEND_STANDBY:
31 case PM_SUSPEND_MEM:
32 return 1;
33 default:
34 return 0;
35 }
36 }
37
lite5200_pm_begin(suspend_state_t state)38 static int lite5200_pm_begin(suspend_state_t state)
39 {
40 if (lite5200_pm_valid(state)) {
41 lite5200_pm_target_state = state;
42 return 0;
43 }
44 return -EINVAL;
45 }
46
lite5200_pm_prepare(void)47 static int lite5200_pm_prepare(void)
48 {
49 struct device_node *np;
50 const struct of_device_id immr_ids[] = {
51 { .compatible = "fsl,mpc5200-immr", },
52 { .compatible = "fsl,mpc5200b-immr", },
53 { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
54 { .type = "builtin", .compatible = "mpc5200", }, /* efika */
55 {}
56 };
57 u64 regaddr64 = 0;
58 const u32 *regaddr_p;
59
60 /* deep sleep? let mpc52xx code handle that */
61 if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
62 return mpc52xx_pm_prepare();
63
64 if (lite5200_pm_target_state != PM_SUSPEND_MEM)
65 return -EINVAL;
66
67 /* map registers */
68 np = of_find_matching_node(NULL, immr_ids);
69 regaddr_p = of_get_address(np, 0, NULL, NULL);
70 if (regaddr_p)
71 regaddr64 = of_translate_address(np, regaddr_p);
72 of_node_put(np);
73
74 mbar = ioremap((u32) regaddr64, 0xC000);
75 if (!mbar) {
76 printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
77 return -ENOSYS;
78 }
79
80 cdm = mbar + 0x200;
81 pic = mbar + 0x500;
82 gps = mbar + 0xb00;
83 gpw = mbar + 0xc00;
84 pci = mbar + 0xd00;
85 bes = mbar + 0x1200;
86 xlb = mbar + 0x1f00;
87 sram = mbar + 0x8000;
88
89 return 0;
90 }
91
92 /* save and restore registers not bound to any real devices */
93 static struct mpc52xx_cdm scdm;
94 static struct mpc52xx_intr spic;
95 static struct mpc52xx_sdma sbes;
96 static struct mpc52xx_xlb sxlb;
97 static struct mpc52xx_gpio sgps;
98 static struct mpc52xx_gpio_wkup sgpw;
99 static char spci[0x200];
100
lite5200_save_regs(void)101 static void lite5200_save_regs(void)
102 {
103 _memcpy_fromio(&spic, pic, sizeof(*pic));
104 _memcpy_fromio(&sbes, bes, sizeof(*bes));
105 _memcpy_fromio(&scdm, cdm, sizeof(*cdm));
106 _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
107 _memcpy_fromio(&sgps, gps, sizeof(*gps));
108 _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
109 _memcpy_fromio(spci, pci, 0x200);
110
111 _memcpy_fromio(saved_sram, sram, sram_size);
112 }
113
lite5200_restore_regs(void)114 static void lite5200_restore_regs(void)
115 {
116 int i;
117 _memcpy_toio(sram, saved_sram, sram_size);
118
119 /* PCI Configuration */
120 _memcpy_toio(pci, spci, 0x200);
121
122 /*
123 * GPIOs. Interrupt Master Enable has higher address then other
124 * registers, so just memcpy is ok.
125 */
126 _memcpy_toio(gpw, &sgpw, sizeof(*gpw));
127 _memcpy_toio(gps, &sgps, sizeof(*gps));
128
129
130 /* XLB Arbitrer */
131 out_be32(&xlb->snoop_window, sxlb.snoop_window);
132 out_be32(&xlb->master_priority, sxlb.master_priority);
133 out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
134
135 /* enable */
136 out_be32(&xlb->int_enable, sxlb.int_enable);
137 out_be32(&xlb->config, sxlb.config);
138
139
140 /* CDM - Clock Distribution Module */
141 out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
142 out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
143
144 out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
145 out_8(&cdm->fd_enable, scdm.fd_enable);
146 out_be16(&cdm->fd_counters, scdm.fd_counters);
147
148 out_be32(&cdm->clk_enables, scdm.clk_enables);
149
150 out_8(&cdm->osc_disable, scdm.osc_disable);
151
152 out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
153 out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
154 out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
155 out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
156
157
158 /* BESTCOMM */
159 out_be32(&bes->taskBar, sbes.taskBar);
160 out_be32(&bes->currentPointer, sbes.currentPointer);
161 out_be32(&bes->endPointer, sbes.endPointer);
162 out_be32(&bes->variablePointer, sbes.variablePointer);
163
164 out_8(&bes->IntVect1, sbes.IntVect1);
165 out_8(&bes->IntVect2, sbes.IntVect2);
166 out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
167
168 for (i=0; i<32; i++)
169 out_8(&bes->ipr[i], sbes.ipr[i]);
170
171 out_be32(&bes->cReqSelect, sbes.cReqSelect);
172 out_be32(&bes->task_size0, sbes.task_size0);
173 out_be32(&bes->task_size1, sbes.task_size1);
174 out_be32(&bes->MDEDebug, sbes.MDEDebug);
175 out_be32(&bes->ADSDebug, sbes.ADSDebug);
176 out_be32(&bes->Value1, sbes.Value1);
177 out_be32(&bes->Value2, sbes.Value2);
178 out_be32(&bes->Control, sbes.Control);
179 out_be32(&bes->Status, sbes.Status);
180 out_be32(&bes->PTDDebug, sbes.PTDDebug);
181
182 /* restore tasks */
183 for (i=0; i<16; i++)
184 out_be16(&bes->tcr[i], sbes.tcr[i]);
185
186 /* enable interrupts */
187 out_be32(&bes->IntPend, sbes.IntPend);
188 out_be32(&bes->IntMask, sbes.IntMask);
189
190
191 /* PIC */
192 out_be32(&pic->per_pri1, spic.per_pri1);
193 out_be32(&pic->per_pri2, spic.per_pri2);
194 out_be32(&pic->per_pri3, spic.per_pri3);
195
196 out_be32(&pic->main_pri1, spic.main_pri1);
197 out_be32(&pic->main_pri2, spic.main_pri2);
198
199 out_be32(&pic->enc_status, spic.enc_status);
200
201 /* unmask and enable interrupts */
202 out_be32(&pic->per_mask, spic.per_mask);
203 out_be32(&pic->main_mask, spic.main_mask);
204 out_be32(&pic->ctrl, spic.ctrl);
205 }
206
lite5200_pm_enter(suspend_state_t state)207 static int lite5200_pm_enter(suspend_state_t state)
208 {
209 /* deep sleep? let mpc52xx code handle that */
210 if (state == PM_SUSPEND_STANDBY) {
211 return mpc52xx_pm_enter(state);
212 }
213
214 lite5200_save_regs();
215
216 /* effectively save FP regs */
217 enable_kernel_fp();
218
219 lite5200_low_power(sram, mbar);
220
221 lite5200_restore_regs();
222
223 iounmap(mbar);
224 return 0;
225 }
226
lite5200_pm_finish(void)227 static void lite5200_pm_finish(void)
228 {
229 /* deep sleep? let mpc52xx code handle that */
230 if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
231 mpc52xx_pm_finish();
232 }
233
lite5200_pm_end(void)234 static void lite5200_pm_end(void)
235 {
236 lite5200_pm_target_state = PM_SUSPEND_ON;
237 }
238
239 static const struct platform_suspend_ops lite5200_pm_ops = {
240 .valid = lite5200_pm_valid,
241 .begin = lite5200_pm_begin,
242 .prepare = lite5200_pm_prepare,
243 .enter = lite5200_pm_enter,
244 .finish = lite5200_pm_finish,
245 .end = lite5200_pm_end,
246 };
247
lite5200_pm_init(void)248 int __init lite5200_pm_init(void)
249 {
250 suspend_set_ops(&lite5200_pm_ops);
251 return 0;
252 }
253