1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
5 * Copyright (C) 2011 John Crispin <john@phrozen.org>
6 */
7
8 #include <linux/ioport.h>
9 #include <linux/export.h>
10 #include <linux/clkdev.h>
11 #include <linux/of_address.h>
12 #include <asm/delay.h>
13
14 #include <lantiq_soc.h>
15
16 #include "../clk.h"
17
18 /* infrastructure control register */
19 #define SYS1_INFRAC 0x00bc
20 /* Configuration fuses for drivers and pll */
21 #define STATUS_CONFIG 0x0040
22
23 /* GPE frequency selection */
24 #define GPPC_OFFSET 24
25 #define GPEFREQ_MASK 0x0000C00
26 #define GPEFREQ_OFFSET 10
27 /* Clock status register */
28 #define SYSCTL_CLKS 0x0000
29 /* Clock enable register */
30 #define SYSCTL_CLKEN 0x0004
31 /* Clock clear register */
32 #define SYSCTL_CLKCLR 0x0008
33 /* Activation Status Register */
34 #define SYSCTL_ACTS 0x0020
35 /* Activation Register */
36 #define SYSCTL_ACT 0x0024
37 /* Deactivation Register */
38 #define SYSCTL_DEACT 0x0028
39 /* reboot Register */
40 #define SYSCTL_RBT 0x002c
41 /* CPU0 Clock Control Register */
42 #define SYS1_CPU0CC 0x0040
43 /* HRST_OUT_N Control Register */
44 #define SYS1_HRSTOUTC 0x00c0
45 /* clock divider bit */
46 #define CPU0CC_CPUDIV 0x0001
47
48 /* Activation Status Register */
49 #define ACTS_ASC0_ACT 0x00001000
50 #define ACTS_SSC0 0x00002000
51 #define ACTS_ASC1_ACT 0x00000800
52 #define ACTS_I2C_ACT 0x00004000
53 #define ACTS_P0 0x00010000
54 #define ACTS_P1 0x00010000
55 #define ACTS_P2 0x00020000
56 #define ACTS_P3 0x00020000
57 #define ACTS_P4 0x00040000
58 #define ACTS_PADCTRL0 0x00100000
59 #define ACTS_PADCTRL1 0x00100000
60 #define ACTS_PADCTRL2 0x00200000
61 #define ACTS_PADCTRL3 0x00200000
62 #define ACTS_PADCTRL4 0x00400000
63
64 #define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
65 #define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
66 #define sysctl_w32_mask(m, clear, set, reg) \
67 sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
68
69 #define status_w32(x, y) ltq_w32((x), status_membase + (y))
70 #define status_r32(x) ltq_r32(status_membase + (x))
71
72 static void __iomem *sysctl_membase[3], *status_membase;
73 void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
74
falcon_trigger_hrst(int level)75 void falcon_trigger_hrst(int level)
76 {
77 sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
78 }
79
sysctl_wait(struct clk * clk,unsigned int test,unsigned int reg)80 static inline void sysctl_wait(struct clk *clk,
81 unsigned int test, unsigned int reg)
82 {
83 int err = 1000000;
84
85 do {} while (--err && ((sysctl_r32(clk->module, reg)
86 & clk->bits) != test));
87 if (!err)
88 pr_err("module de/activation failed %d %08X %08X %08X\n",
89 clk->module, clk->bits, test,
90 sysctl_r32(clk->module, reg) & clk->bits);
91 }
92
sysctl_activate(struct clk * clk)93 static int sysctl_activate(struct clk *clk)
94 {
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
97 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
98 return 0;
99 }
100
sysctl_deactivate(struct clk * clk)101 static void sysctl_deactivate(struct clk *clk)
102 {
103 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
104 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
105 sysctl_wait(clk, 0, SYSCTL_ACTS);
106 }
107
sysctl_clken(struct clk * clk)108 static int sysctl_clken(struct clk *clk)
109 {
110 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
111 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
112 sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
113 return 0;
114 }
115
sysctl_clkdis(struct clk * clk)116 static void sysctl_clkdis(struct clk *clk)
117 {
118 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
119 sysctl_wait(clk, 0, SYSCTL_CLKS);
120 }
121
sysctl_reboot(struct clk * clk)122 static void sysctl_reboot(struct clk *clk)
123 {
124 unsigned int act;
125 unsigned int bits;
126
127 act = sysctl_r32(clk->module, SYSCTL_ACT);
128 bits = ~act & clk->bits;
129 if (bits != 0) {
130 sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
131 sysctl_w32(clk->module, bits, SYSCTL_ACT);
132 sysctl_wait(clk, bits, SYSCTL_ACTS);
133 }
134 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
135 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
136 }
137
138 /* enable the ONU core */
falcon_gpe_enable(void)139 static void falcon_gpe_enable(void)
140 {
141 unsigned int freq;
142 unsigned int status;
143
144 /* if the clock is already enabled */
145 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
146 if (status & (1 << (GPPC_OFFSET + 1)))
147 return;
148
149 freq = (status_r32(STATUS_CONFIG) &
150 GPEFREQ_MASK) >>
151 GPEFREQ_OFFSET;
152 if (freq == 0)
153 freq = 1; /* use 625MHz on unfused chip */
154
155 /* apply new frequency */
156 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
157 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
158 udelay(1);
159
160 /* enable new frequency */
161 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
162 udelay(1);
163 }
164
clkdev_add_sys(const char * dev,unsigned int module,unsigned int bits)165 static inline void clkdev_add_sys(const char *dev, unsigned int module,
166 unsigned int bits)
167 {
168 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
169
170 if (!clk)
171 return;
172 clk->cl.dev_id = dev;
173 clk->cl.con_id = NULL;
174 clk->cl.clk = clk;
175 clk->module = module;
176 clk->bits = bits;
177 clk->activate = sysctl_activate;
178 clk->deactivate = sysctl_deactivate;
179 clk->enable = sysctl_clken;
180 clk->disable = sysctl_clkdis;
181 clk->reboot = sysctl_reboot;
182 clkdev_add(&clk->cl);
183 }
184
ltq_soc_init(void)185 void __init ltq_soc_init(void)
186 {
187 struct device_node *np_status =
188 of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
189 struct device_node *np_ebu =
190 of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
191 struct device_node *np_sys1 =
192 of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
193 struct device_node *np_syseth =
194 of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
195 struct device_node *np_sysgpe =
196 of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
197 struct resource res_status, res_ebu, res_sys[3];
198 int i;
199
200 /* check if all the core register ranges are available */
201 if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
202 panic("Failed to load core nodes from devicetree");
203
204 if (of_address_to_resource(np_status, 0, &res_status) ||
205 of_address_to_resource(np_ebu, 0, &res_ebu) ||
206 of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
207 of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
208 of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
209 panic("Failed to get core resources");
210
211 of_node_put(np_status);
212 of_node_put(np_ebu);
213 of_node_put(np_sys1);
214 of_node_put(np_syseth);
215 of_node_put(np_sysgpe);
216
217 if ((request_mem_region(res_status.start, resource_size(&res_status),
218 res_status.name) < 0) ||
219 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
220 res_ebu.name) < 0) ||
221 (request_mem_region(res_sys[0].start,
222 resource_size(&res_sys[0]),
223 res_sys[0].name) < 0) ||
224 (request_mem_region(res_sys[1].start,
225 resource_size(&res_sys[1]),
226 res_sys[1].name) < 0) ||
227 (request_mem_region(res_sys[2].start,
228 resource_size(&res_sys[2]),
229 res_sys[2].name) < 0))
230 pr_err("Failed to request core resources");
231
232 status_membase = ioremap(res_status.start,
233 resource_size(&res_status));
234 ltq_ebu_membase = ioremap(res_ebu.start,
235 resource_size(&res_ebu));
236
237 if (!status_membase || !ltq_ebu_membase)
238 panic("Failed to remap core resources");
239
240 for (i = 0; i < 3; i++) {
241 sysctl_membase[i] = ioremap(res_sys[i].start,
242 resource_size(&res_sys[i]));
243 if (!sysctl_membase[i])
244 panic("Failed to remap sysctrl resources");
245 }
246 ltq_sys1_membase = sysctl_membase[0];
247
248 falcon_gpe_enable();
249
250 /* get our 3 static rates for cpu, fpi and io clocks */
251 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
252 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
253 else
254 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
255
256 /* add our clock domains */
257 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
258 clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
259 clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
260 clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
261 clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
262 clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
263 clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
264 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
265 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
266 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
267 clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
268 clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
269 clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0);
270 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
271 }
272