1 /******************************************************************************
2 * i8259.c
3 *
4 * Well, this is required for SMP systems as well, as it build interrupt
5 * tables for IO APICS as well as uniprocessor 8259-alikes.
6 */
7
8 #include <xen/init.h>
9 #include <xen/types.h>
10 #include <asm/regs.h>
11 #include <xen/errno.h>
12 #include <xen/sched.h>
13 #include <xen/irq.h>
14 #include <asm/atomic.h>
15 #include <asm/system.h>
16 #include <asm/io.h>
17 #include <asm/desc.h>
18 #include <xen/bitops.h>
19 #include <xen/delay.h>
20 #include <asm/apic.h>
21 #include <asm/asm_defns.h>
22 #include <io_ports.h>
23
24 /*
25 * This is the 'legacy' 8259A Programmable Interrupt Controller,
26 * present in the majority of PC/AT boxes.
27 * plus some generic x86 specific things if generic specifics makes
28 * any sense at all.
29 * this file should become arch/i386/kernel/irq.c when the old irq.c
30 * moves to arch independent land
31 */
32
33 static DEFINE_SPINLOCK(i8259A_lock);
34
35 static bool _mask_and_ack_8259A_irq(unsigned int irq);
36
bogus_8259A_irq(unsigned int irq)37 bool bogus_8259A_irq(unsigned int irq)
38 {
39 return _mask_and_ack_8259A_irq(irq);
40 }
41
mask_and_ack_8259A_irq(struct irq_desc * desc)42 static void mask_and_ack_8259A_irq(struct irq_desc *desc)
43 {
44 _mask_and_ack_8259A_irq(desc->irq);
45 }
46
startup_8259A_irq(struct irq_desc * desc)47 static unsigned int startup_8259A_irq(struct irq_desc *desc)
48 {
49 enable_8259A_irq(desc);
50 return 0; /* never anything pending */
51 }
52
end_8259A_irq(struct irq_desc * desc,u8 vector)53 static void end_8259A_irq(struct irq_desc *desc, u8 vector)
54 {
55 if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
56 enable_8259A_irq(desc);
57 }
58
59 static struct hw_interrupt_type __read_mostly i8259A_irq_type = {
60 .typename = "XT-PIC",
61 .startup = startup_8259A_irq,
62 .shutdown = disable_8259A_irq,
63 .enable = enable_8259A_irq,
64 .disable = disable_8259A_irq,
65 .ack = mask_and_ack_8259A_irq,
66 .end = end_8259A_irq
67 };
68
69 /*
70 * 8259A PIC functions to handle ISA devices:
71 */
72
73 #define aeoi_mode (i8259A_irq_type.ack == disable_8259A_irq)
74
75 /*
76 * This contains the irq mask for both 8259A irq controllers,
77 */
78 static unsigned int cached_irq_mask = 0xffff;
79
80 #define __byte(x,y) (((unsigned char *)&(y))[x])
81 #define cached_21 (__byte(0,cached_irq_mask))
82 #define cached_A1 (__byte(1,cached_irq_mask))
83
84 /*
85 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
86 * boards the timer interrupt is not really connected to any IO-APIC pin,
87 * it's fed to the master 8259A's IR0 line only.
88 *
89 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
90 * this 'mixed mode' IRQ handling costs nothing because it's only used
91 * at IRQ setup time.
92 */
93 unsigned int __read_mostly io_apic_irqs;
94
_disable_8259A_irq(unsigned int irq)95 static void _disable_8259A_irq(unsigned int irq)
96 {
97 unsigned int mask = 1 << irq;
98 unsigned long flags;
99
100 spin_lock_irqsave(&i8259A_lock, flags);
101 cached_irq_mask |= mask;
102 if (irq & 8)
103 outb(cached_A1,0xA1);
104 else
105 outb(cached_21,0x21);
106 per_cpu(vector_irq, 0)[LEGACY_VECTOR(irq)] = ~irq;
107 spin_unlock_irqrestore(&i8259A_lock, flags);
108 }
109
disable_8259A_irq(struct irq_desc * desc)110 void disable_8259A_irq(struct irq_desc *desc)
111 {
112 _disable_8259A_irq(desc->irq);
113 }
114
enable_8259A_irq(struct irq_desc * desc)115 void enable_8259A_irq(struct irq_desc *desc)
116 {
117 unsigned int mask = ~(1 << desc->irq);
118 unsigned long flags;
119
120 spin_lock_irqsave(&i8259A_lock, flags);
121 cached_irq_mask &= mask;
122 per_cpu(vector_irq, 0)[LEGACY_VECTOR(desc->irq)] = desc->irq;
123 if (desc->irq & 8)
124 outb(cached_A1,0xA1);
125 else
126 outb(cached_21,0x21);
127 spin_unlock_irqrestore(&i8259A_lock, flags);
128 }
129
i8259A_irq_pending(unsigned int irq)130 int i8259A_irq_pending(unsigned int irq)
131 {
132 unsigned int mask = 1<<irq;
133 unsigned long flags;
134 int ret;
135
136 spin_lock_irqsave(&i8259A_lock, flags);
137 if (irq < 8)
138 ret = inb(0x20) & mask;
139 else
140 ret = inb(0xA0) & (mask >> 8);
141 spin_unlock_irqrestore(&i8259A_lock, flags);
142
143 return ret;
144 }
145
mask_8259A(void)146 void mask_8259A(void)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&i8259A_lock, flags);
151 outb(0xff, 0xA1);
152 outb(0xff, 0x21);
153 spin_unlock_irqrestore(&i8259A_lock, flags);
154 }
155
unmask_8259A(void)156 void unmask_8259A(void)
157 {
158 unsigned long flags;
159
160 spin_lock_irqsave(&i8259A_lock, flags);
161 outb(cached_A1, 0xA1);
162 outb(cached_21, 0x21);
163 spin_unlock_irqrestore(&i8259A_lock, flags);
164 }
165
166 /*
167 * This function assumes to be called rarely. Switching between
168 * 8259A registers is slow.
169 * This has to be protected by the irq controller spinlock
170 * before being called.
171 */
i8259A_irq_real(unsigned int irq)172 static inline int i8259A_irq_real(unsigned int irq)
173 {
174 int value;
175 int irqmask = 1<<irq;
176
177 if (irq < 8) {
178 outb(0x0B,0x20); /* ISR register */
179 value = inb(0x20) & irqmask;
180 outb(0x0A,0x20); /* back to the IRR register */
181 return value;
182 }
183 outb(0x0B,0xA0); /* ISR register */
184 value = inb(0xA0) & (irqmask >> 8);
185 outb(0x0A,0xA0); /* back to the IRR register */
186 return value;
187 }
188
189 /*
190 * Careful! The 8259A is a fragile beast, it pretty
191 * much _has_ to be done exactly like this (mask it
192 * first, _then_ send the EOI, and the order of EOI
193 * to the two 8259s is important! Return a boolean
194 * indicating whether the irq was genuine or spurious.
195 */
_mask_and_ack_8259A_irq(unsigned int irq)196 static bool _mask_and_ack_8259A_irq(unsigned int irq)
197 {
198 unsigned int irqmask = 1 << irq;
199 unsigned long flags;
200 bool is_real_irq = true; /* Assume real unless spurious */
201
202 spin_lock_irqsave(&i8259A_lock, flags);
203
204 /*
205 * Lightweight spurious IRQ detection. We do not want
206 * to overdo spurious IRQ handling - it's usually a sign
207 * of hardware problems, so we only do the checks we can
208 * do without slowing down good hardware unnecesserily.
209 *
210 * Note that IRQ7 and IRQ15 (the two spurious IRQs
211 * usually resulting from the 8259A-1|2 PICs) occur
212 * even if the IRQ is masked in the 8259A. Thus we
213 * can check spurious 8259A IRQs without doing the
214 * quite slow i8259A_irq_real() call for every IRQ.
215 * This does not cover 100% of spurious interrupts,
216 * but should be enough to warn the user that there
217 * is something bad going on ...
218 */
219 if ((cached_irq_mask & irqmask) && !i8259A_irq_real(irq)) {
220 static int spurious_irq_mask;
221 is_real_irq = false;
222 /* Report spurious IRQ, once per IRQ line. */
223 if (!(spurious_irq_mask & irqmask)) {
224 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
225 spurious_irq_mask |= irqmask;
226 }
227 /*
228 * Theoretically we do not have to handle this IRQ,
229 * but in Linux this does not cause problems and is
230 * simpler for us.
231 */
232 }
233
234 cached_irq_mask |= irqmask;
235
236 if (irq & 8) {
237 inb(0xA1); /* DUMMY - (do we need this?) */
238 outb(cached_A1,0xA1);
239 if (!aeoi_mode) {
240 outb(0x60 + (irq & 7), 0xA0);/* 'Specific EOI' to slave */
241 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
242 }
243 } else {
244 inb(0x21); /* DUMMY - (do we need this?) */
245 outb(cached_21,0x21);
246 if (!aeoi_mode)
247 outb(0x60 + irq, 0x20);/* 'Specific EOI' to master */
248 }
249
250 spin_unlock_irqrestore(&i8259A_lock, flags);
251
252 return is_real_irq;
253 }
254
255 static char irq_trigger[2];
256 /**
257 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
258 */
restore_ELCR(char * trigger)259 static void restore_ELCR(char *trigger)
260 {
261 outb(trigger[0], 0x4d0);
262 outb(trigger[1], 0x4d1);
263 }
264
save_ELCR(char * trigger)265 static void save_ELCR(char *trigger)
266 {
267 /* IRQ 0,1,2,8,13 are marked as reserved */
268 trigger[0] = inb(0x4d0) & 0xF8;
269 trigger[1] = inb(0x4d1) & 0xDE;
270 }
271
i8259A_resume(void)272 int i8259A_resume(void)
273 {
274 init_8259A(aeoi_mode);
275 restore_ELCR(irq_trigger);
276 return 0;
277 }
278
i8259A_suspend(void)279 int i8259A_suspend(void)
280 {
281 save_ELCR(irq_trigger);
282 return 0;
283 }
284
init_8259A(int auto_eoi)285 void init_8259A(int auto_eoi)
286 {
287 unsigned long flags;
288
289 spin_lock_irqsave(&i8259A_lock, flags);
290
291 outb(0xff, 0x21); /* mask all of 8259A-1 */
292 outb(0xff, 0xA1); /* mask all of 8259A-2 */
293
294 /*
295 * outb_p - this has to work on a wide range of PC hardware.
296 */
297 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
298 outb_p(FIRST_LEGACY_VECTOR + 0, 0x21); /* ICW2: 8259A-1 IR0-7 */
299 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
300 if (auto_eoi)
301 outb_p(0x03, 0x21); /* master does Auto EOI */
302 else
303 outb_p(0x01, 0x21); /* master expects normal EOI */
304
305 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
306 outb_p(FIRST_LEGACY_VECTOR + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 */
307 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
308 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
309 is to be investigated) */
310
311 if (auto_eoi)
312 /*
313 * in AEOI mode we just have to mask the interrupt
314 * when acking.
315 */
316 i8259A_irq_type.ack = disable_8259A_irq;
317 else
318 i8259A_irq_type.ack = mask_and_ack_8259A_irq;
319
320 udelay(100); /* wait for 8259A to initialize */
321
322 outb(cached_21, 0x21); /* restore master IRQ mask */
323 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
324
325 spin_unlock_irqrestore(&i8259A_lock, flags);
326 }
327
make_8259A_irq(unsigned int irq)328 void __init make_8259A_irq(unsigned int irq)
329 {
330 io_apic_irqs &= ~(1 << irq);
331 irq_to_desc(irq)->handler = &i8259A_irq_type;
332 }
333
334 static struct irqaction __read_mostly cascade = { no_action, "cascade", NULL};
335
init_IRQ(void)336 void __init init_IRQ(void)
337 {
338 int irq, cpu = smp_processor_id();
339
340 init_bsp_APIC();
341
342 init_8259A(0);
343
344 BUG_ON(init_irq_data() < 0);
345
346 for (irq = 0; platform_legacy_irq(irq); irq++) {
347 struct irq_desc *desc = irq_to_desc(irq);
348
349 if ( irq == 2 ) /* IRQ2 doesn't exist */
350 continue;
351 desc->handler = &i8259A_irq_type;
352 per_cpu(vector_irq, cpu)[FIRST_LEGACY_VECTOR + irq] = irq;
353 cpumask_copy(desc->arch.cpu_mask, cpumask_of(cpu));
354 desc->arch.vector = FIRST_LEGACY_VECTOR + irq;
355 }
356
357 per_cpu(vector_irq, cpu)[IRQ0_VECTOR] = 0;
358
359 apic_intr_init();
360
361 setup_irq(2, 0, &cascade);
362 }
363
364