1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define PCI_REVISION_ID_HIP08 0x21
40 #define PCI_REVISION_ID_HIP09 0x30
41
42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
43
44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
45
46 #define BA_BYTE_LEN 8
47
48 #define HNS_ROCE_MIN_CQE_NUM 0x40
49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
50
51 #define HNS_ROCE_MAX_IRQ_NUM 128
52
53 #define HNS_ROCE_SGE_IN_WQE 2
54 #define HNS_ROCE_SGE_SHIFT 4
55
56 #define EQ_ENABLE 1
57 #define EQ_DISABLE 0
58
59 #define HNS_ROCE_CEQ 0
60 #define HNS_ROCE_AEQ 1
61
62 #define HNS_ROCE_CEQE_SIZE 0x4
63 #define HNS_ROCE_AEQE_SIZE 0x10
64
65 #define HNS_ROCE_V3_EQE_SIZE 0x40
66
67 #define HNS_ROCE_V2_CQE_SIZE 32
68 #define HNS_ROCE_V3_CQE_SIZE 64
69
70 #define HNS_ROCE_V2_QPC_SZ 256
71 #define HNS_ROCE_V3_QPC_SZ 512
72
73 #define HNS_ROCE_MAX_PORTS 6
74 #define HNS_ROCE_GID_SIZE 16
75 #define HNS_ROCE_SGE_SIZE 16
76 #define HNS_ROCE_DWQE_SIZE 65536
77
78 #define HNS_ROCE_HOP_NUM_0 0xff
79
80 #define MR_TYPE_MR 0x00
81 #define MR_TYPE_FRMR 0x01
82 #define MR_TYPE_DMA 0x03
83
84 #define HNS_ROCE_FRMR_MAX_PA 512
85
86 #define PKEY_ID 0xffff
87 #define NODE_DESC_SIZE 64
88 #define DB_REG_OFFSET 0x1000
89
90 /* Configure to HW for PAGE_SIZE larger than 4KB */
91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
92
93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
94 #define SRQ_DB_REG 0x230
95
96 #define HNS_ROCE_QP_BANK_NUM 8
97 #define HNS_ROCE_CQ_BANK_NUM 4
98
99 #define CQ_BANKID_SHIFT 2
100
101 enum {
102 SERV_TYPE_RC,
103 SERV_TYPE_UC,
104 SERV_TYPE_RD,
105 SERV_TYPE_UD,
106 SERV_TYPE_XRC = 5,
107 };
108
109 enum hns_roce_event {
110 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
111 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
112 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
113 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
114 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
115 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
116 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
117 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
118 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
119 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
120 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
121 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
122 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
123 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
124 /* 0x10 and 0x11 is unused in currently application case */
125 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
126 HNS_ROCE_EVENT_TYPE_MB = 0x13,
127 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
128 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
129 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
130 };
131
132 enum {
133 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
134 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
135 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
136 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
137 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
138 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
139 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
140 HNS_ROCE_CAP_FLAG_MW = BIT(7),
141 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
142 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
143 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
144 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12),
145 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
146 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
147 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19),
148 };
149
150 #define HNS_ROCE_DB_TYPE_COUNT 2
151 #define HNS_ROCE_DB_UNIT_SIZE 4
152
153 enum {
154 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
155 };
156
157 enum hns_roce_reset_stage {
158 HNS_ROCE_STATE_NON_RST,
159 HNS_ROCE_STATE_RST_BEF_DOWN,
160 HNS_ROCE_STATE_RST_DOWN,
161 HNS_ROCE_STATE_RST_UNINIT,
162 HNS_ROCE_STATE_RST_INIT,
163 HNS_ROCE_STATE_RST_INITED,
164 };
165
166 enum hns_roce_instance_state {
167 HNS_ROCE_STATE_NON_INIT,
168 HNS_ROCE_STATE_INIT,
169 HNS_ROCE_STATE_INITED,
170 HNS_ROCE_STATE_UNINIT,
171 };
172
173 enum {
174 HNS_ROCE_RST_DIRECT_RETURN = 0,
175 };
176
177 #define HNS_ROCE_CMD_SUCCESS 1
178
179 /* The minimum page size is 4K for hardware */
180 #define HNS_HW_PAGE_SHIFT 12
181 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
182
183 struct hns_roce_uar {
184 u64 pfn;
185 unsigned long index;
186 unsigned long logic_idx;
187 };
188
189 enum hns_roce_mmap_type {
190 HNS_ROCE_MMAP_TYPE_DB = 1,
191 HNS_ROCE_MMAP_TYPE_DWQE,
192 };
193
194 struct hns_user_mmap_entry {
195 struct rdma_user_mmap_entry rdma_entry;
196 enum hns_roce_mmap_type mmap_type;
197 u64 address;
198 };
199
200 struct hns_roce_ucontext {
201 struct ib_ucontext ibucontext;
202 struct hns_roce_uar uar;
203 struct list_head page_list;
204 struct mutex page_mutex;
205 struct hns_user_mmap_entry *db_mmap_entry;
206 u32 config;
207 };
208
209 struct hns_roce_pd {
210 struct ib_pd ibpd;
211 unsigned long pdn;
212 };
213
214 struct hns_roce_xrcd {
215 struct ib_xrcd ibxrcd;
216 u32 xrcdn;
217 };
218
219 struct hns_roce_bitmap {
220 /* Bitmap Traversal last a bit which is 1 */
221 unsigned long last;
222 unsigned long top;
223 unsigned long max;
224 unsigned long reserved_top;
225 unsigned long mask;
226 spinlock_t lock;
227 unsigned long *table;
228 };
229
230 struct hns_roce_ida {
231 struct ida ida;
232 u32 min; /* Lowest ID to allocate. */
233 u32 max; /* Highest ID to allocate. */
234 };
235
236 /* For Hardware Entry Memory */
237 struct hns_roce_hem_table {
238 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
239 u32 type;
240 /* HEM array elment num */
241 unsigned long num_hem;
242 /* Single obj size */
243 unsigned long obj_size;
244 unsigned long table_chunk_size;
245 struct mutex mutex;
246 struct hns_roce_hem **hem;
247 u64 **bt_l1;
248 dma_addr_t *bt_l1_dma_addr;
249 u64 **bt_l0;
250 dma_addr_t *bt_l0_dma_addr;
251 };
252
253 struct hns_roce_buf_region {
254 u32 offset; /* page offset */
255 u32 count; /* page count */
256 int hopnum; /* addressing hop num */
257 };
258
259 #define HNS_ROCE_MAX_BT_REGION 3
260 #define HNS_ROCE_MAX_BT_LEVEL 3
261 struct hns_roce_hem_list {
262 struct list_head root_bt;
263 /* link all bt dma mem by hop config */
264 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
265 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
266 dma_addr_t root_ba; /* pointer to the root ba table */
267 };
268
269 struct hns_roce_buf_attr {
270 struct {
271 size_t size; /* region size */
272 int hopnum; /* multi-hop addressing hop num */
273 } region[HNS_ROCE_MAX_BT_REGION];
274 unsigned int region_count; /* valid region count */
275 unsigned int page_shift; /* buffer page shift */
276 unsigned int user_access; /* umem access flag */
277 bool mtt_only; /* only alloc buffer-required MTT memory */
278 };
279
280 struct hns_roce_hem_cfg {
281 dma_addr_t root_ba; /* root BA table's address */
282 bool is_direct; /* addressing without BA table */
283 unsigned int ba_pg_shift; /* BA table page shift */
284 unsigned int buf_pg_shift; /* buffer page shift */
285 unsigned int buf_pg_count; /* buffer page count */
286 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
287 unsigned int region_count;
288 };
289
290 /* memory translate region */
291 struct hns_roce_mtr {
292 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
293 struct ib_umem *umem; /* user space buffer */
294 struct hns_roce_buf *kmem; /* kernel space buffer */
295 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
296 };
297
298 struct hns_roce_mw {
299 struct ib_mw ibmw;
300 u32 pdn;
301 u32 rkey;
302 int enabled; /* MW's active status */
303 u32 pbl_hop_num;
304 u32 pbl_ba_pg_sz;
305 u32 pbl_buf_pg_sz;
306 };
307
308 struct hns_roce_mr {
309 struct ib_mr ibmr;
310 u64 iova; /* MR's virtual original addr */
311 u64 size; /* Address range of MR */
312 u32 key; /* Key of MR */
313 u32 pd; /* PD num of MR */
314 u32 access; /* Access permission of MR */
315 int enabled; /* MR's active status */
316 int type; /* MR's register type */
317 u32 pbl_hop_num; /* multi-hop number */
318 struct hns_roce_mtr pbl_mtr;
319 u32 npages;
320 dma_addr_t *page_list;
321 };
322
323 struct hns_roce_mr_table {
324 struct hns_roce_ida mtpt_ida;
325 struct hns_roce_hem_table mtpt_table;
326 };
327
328 struct hns_roce_wq {
329 u64 *wrid; /* Work request ID */
330 spinlock_t lock;
331 u32 wqe_cnt; /* WQE num */
332 u32 max_gs;
333 u32 rsv_sge;
334 u32 offset;
335 u32 wqe_shift; /* WQE size */
336 u32 head;
337 u32 tail;
338 void __iomem *db_reg;
339 u32 ext_sge_cnt;
340 };
341
342 struct hns_roce_sge {
343 unsigned int sge_cnt; /* SGE num */
344 u32 offset;
345 u32 sge_shift; /* SGE size */
346 };
347
348 struct hns_roce_buf_list {
349 void *buf;
350 dma_addr_t map;
351 };
352
353 /*
354 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
355 * dma address range.
356 *
357 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
358 *
359 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
360 * the allocated size is smaller than the required size.
361 */
362 enum {
363 HNS_ROCE_BUF_DIRECT = BIT(0),
364 HNS_ROCE_BUF_NOSLEEP = BIT(1),
365 HNS_ROCE_BUF_NOFAIL = BIT(2),
366 };
367
368 struct hns_roce_buf {
369 struct hns_roce_buf_list *trunk_list;
370 u32 ntrunks;
371 u32 npages;
372 unsigned int trunk_shift;
373 unsigned int page_shift;
374 };
375
376 struct hns_roce_db_pgdir {
377 struct list_head list;
378 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
379 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
380 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
381 u32 *page;
382 dma_addr_t db_dma;
383 };
384
385 struct hns_roce_user_db_page {
386 struct list_head list;
387 struct ib_umem *umem;
388 unsigned long user_virt;
389 refcount_t refcount;
390 };
391
392 struct hns_roce_db {
393 u32 *db_record;
394 union {
395 struct hns_roce_db_pgdir *pgdir;
396 struct hns_roce_user_db_page *user_page;
397 } u;
398 dma_addr_t dma;
399 void *virt_addr;
400 unsigned long index;
401 unsigned long order;
402 };
403
404 struct hns_roce_cq {
405 struct ib_cq ib_cq;
406 struct hns_roce_mtr mtr;
407 struct hns_roce_db db;
408 u32 flags;
409 spinlock_t lock;
410 u32 cq_depth;
411 u32 cons_index;
412 u32 *set_ci_db;
413 void __iomem *db_reg;
414 int arm_sn;
415 int cqe_size;
416 unsigned long cqn;
417 u32 vector;
418 refcount_t refcount;
419 struct completion free;
420 struct list_head sq_list; /* all qps on this send cq */
421 struct list_head rq_list; /* all qps on this recv cq */
422 int is_armed; /* cq is armed */
423 struct list_head node; /* all armed cqs are on a list */
424 };
425
426 struct hns_roce_idx_que {
427 struct hns_roce_mtr mtr;
428 u32 entry_shift;
429 unsigned long *bitmap;
430 u32 head;
431 u32 tail;
432 };
433
434 struct hns_roce_srq {
435 struct ib_srq ibsrq;
436 unsigned long srqn;
437 u32 wqe_cnt;
438 int max_gs;
439 u32 rsv_sge;
440 u32 wqe_shift;
441 u32 cqn;
442 u32 xrcdn;
443 void __iomem *db_reg;
444
445 refcount_t refcount;
446 struct completion free;
447
448 struct hns_roce_mtr buf_mtr;
449
450 u64 *wrid;
451 struct hns_roce_idx_que idx_que;
452 spinlock_t lock;
453 struct mutex mutex;
454 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
455 };
456
457 struct hns_roce_uar_table {
458 struct hns_roce_bitmap bitmap;
459 };
460
461 struct hns_roce_bank {
462 struct ida ida;
463 u32 inuse; /* Number of IDs allocated */
464 u32 min; /* Lowest ID to allocate. */
465 u32 max; /* Highest ID to allocate. */
466 u32 next; /* Next ID to allocate. */
467 };
468
469 struct hns_roce_idx_table {
470 u32 *spare_idx;
471 u32 head;
472 u32 tail;
473 };
474
475 struct hns_roce_qp_table {
476 struct hns_roce_hem_table qp_table;
477 struct hns_roce_hem_table irrl_table;
478 struct hns_roce_hem_table trrl_table;
479 struct hns_roce_hem_table sccc_table;
480 struct mutex scc_mutex;
481 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
482 struct mutex bank_mutex;
483 struct hns_roce_idx_table idx_table;
484 };
485
486 struct hns_roce_cq_table {
487 struct xarray array;
488 struct hns_roce_hem_table table;
489 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
490 struct mutex bank_mutex;
491 };
492
493 struct hns_roce_srq_table {
494 struct hns_roce_ida srq_ida;
495 struct xarray xa;
496 struct hns_roce_hem_table table;
497 };
498
499 struct hns_roce_av {
500 u8 port;
501 u8 gid_index;
502 u8 stat_rate;
503 u8 hop_limit;
504 u32 flowlabel;
505 u16 udp_sport;
506 u8 sl;
507 u8 tclass;
508 u8 dgid[HNS_ROCE_GID_SIZE];
509 u8 mac[ETH_ALEN];
510 u16 vlan_id;
511 u8 vlan_en;
512 };
513
514 struct hns_roce_ah {
515 struct ib_ah ibah;
516 struct hns_roce_av av;
517 };
518
519 struct hns_roce_cmd_context {
520 struct completion done;
521 int result;
522 int next;
523 u64 out_param;
524 u16 token;
525 u16 busy;
526 };
527
528 enum hns_roce_cmdq_state {
529 HNS_ROCE_CMDQ_STATE_NORMAL,
530 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
531 };
532
533 struct hns_roce_cmdq {
534 struct dma_pool *pool;
535 struct semaphore poll_sem;
536 /*
537 * Event mode: cmd register mutex protection,
538 * ensure to not exceed max_cmds and user use limit region
539 */
540 struct semaphore event_sem;
541 int max_cmds;
542 spinlock_t context_lock;
543 int free_head;
544 struct hns_roce_cmd_context *context;
545 /*
546 * Process whether use event mode, init default non-zero
547 * After the event queue of cmd event ready,
548 * can switch into event mode
549 * close device, switch into poll mode(non event mode)
550 */
551 u8 use_events;
552 enum hns_roce_cmdq_state state;
553 };
554
555 struct hns_roce_cmd_mailbox {
556 void *buf;
557 dma_addr_t dma;
558 };
559
560 struct hns_roce_mbox_msg {
561 u64 in_param;
562 u64 out_param;
563 u8 cmd;
564 u32 tag;
565 u16 token;
566 u8 event_en;
567 };
568
569 struct hns_roce_dev;
570
571 enum {
572 HNS_ROCE_FLUSH_FLAG = 0,
573 };
574
575 struct hns_roce_work {
576 struct hns_roce_dev *hr_dev;
577 struct work_struct work;
578 int event_type;
579 int sub_type;
580 u32 queue_num;
581 };
582
583 struct hns_roce_qp {
584 struct ib_qp ibqp;
585 struct hns_roce_wq rq;
586 struct hns_roce_db rdb;
587 struct hns_roce_db sdb;
588 unsigned long en_flags;
589 enum ib_sig_type sq_signal_bits;
590 struct hns_roce_wq sq;
591
592 struct hns_roce_mtr mtr;
593
594 u32 buff_size;
595 struct mutex mutex;
596 u8 port;
597 u8 phy_port;
598 u8 sl;
599 u8 resp_depth;
600 u8 state;
601 u32 atomic_rd_en;
602 u32 qkey;
603 void (*event)(struct hns_roce_qp *qp,
604 enum hns_roce_event event_type);
605 unsigned long qpn;
606
607 u32 xrcdn;
608
609 refcount_t refcount;
610 struct completion free;
611
612 struct hns_roce_sge sge;
613 u32 next_sge;
614 enum ib_mtu path_mtu;
615 u32 max_inline_data;
616 u8 free_mr_en;
617
618 /* 0: flush needed, 1: unneeded */
619 unsigned long flush_flag;
620 struct hns_roce_work flush_work;
621 struct list_head node; /* all qps are on a list */
622 struct list_head rq_node; /* all recv qps are on a list */
623 struct list_head sq_node; /* all send qps are on a list */
624 struct hns_user_mmap_entry *dwqe_mmap_entry;
625 u32 config;
626 };
627
628 struct hns_roce_ib_iboe {
629 spinlock_t lock;
630 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
631 struct notifier_block nb;
632 u8 phy_port[HNS_ROCE_MAX_PORTS];
633 };
634
635 struct hns_roce_ceqe {
636 __le32 comp;
637 __le32 rsv[15];
638 };
639
640 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)
641
642 #define CEQE_CQN CEQE_FIELD_LOC(23, 0)
643 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31)
644
645 struct hns_roce_aeqe {
646 __le32 asyn;
647 union {
648 struct {
649 __le32 num;
650 u32 rsv0;
651 u32 rsv1;
652 } queue_event;
653
654 struct {
655 __le64 out_param;
656 __le16 token;
657 u8 status;
658 u8 rsv0;
659 } __packed cmd;
660 } event;
661 __le32 rsv[12];
662 };
663
664 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)
665
666 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
667 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
668 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
669 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)
670
671 struct hns_roce_eq {
672 struct hns_roce_dev *hr_dev;
673 void __iomem *db_reg;
674
675 int type_flag; /* Aeq:1 ceq:0 */
676 int eqn;
677 u32 entries;
678 int eqe_size;
679 int irq;
680 u32 cons_index;
681 int over_ignore;
682 int coalesce;
683 int arm_st;
684 int hop_num;
685 struct hns_roce_mtr mtr;
686 u16 eq_max_cnt;
687 u32 eq_period;
688 int shift;
689 int event_type;
690 int sub_type;
691 };
692
693 struct hns_roce_eq_table {
694 struct hns_roce_eq *eq;
695 };
696
697 enum cong_type {
698 CONG_TYPE_DCQCN,
699 CONG_TYPE_LDCP,
700 CONG_TYPE_HC3,
701 CONG_TYPE_DIP,
702 };
703
704 struct hns_roce_caps {
705 u64 fw_ver;
706 u8 num_ports;
707 int gid_table_len[HNS_ROCE_MAX_PORTS];
708 int pkey_table_len[HNS_ROCE_MAX_PORTS];
709 int local_ca_ack_delay;
710 int num_uars;
711 u32 phy_num_uars;
712 u32 max_sq_sg;
713 u32 max_sq_inline;
714 u32 max_rq_sg;
715 u32 rsv0;
716 u32 num_qps;
717 u32 num_pi_qps;
718 u32 reserved_qps;
719 u32 num_srqs;
720 u32 max_wqes;
721 u32 max_srq_wrs;
722 u32 max_srq_sges;
723 u32 max_sq_desc_sz;
724 u32 max_rq_desc_sz;
725 u32 rsv2;
726 int max_qp_init_rdma;
727 int max_qp_dest_rdma;
728 u32 num_cqs;
729 u32 max_cqes;
730 u32 min_cqes;
731 u32 min_wqes;
732 u32 reserved_cqs;
733 u32 reserved_srqs;
734 int num_aeq_vectors;
735 int num_comp_vectors;
736 int num_other_vectors;
737 u32 num_mtpts;
738 u32 rsv1;
739 u32 num_srqwqe_segs;
740 u32 num_idx_segs;
741 int reserved_mrws;
742 int reserved_uars;
743 int num_pds;
744 int reserved_pds;
745 u32 num_xrcds;
746 u32 reserved_xrcds;
747 u32 mtt_entry_sz;
748 u32 cqe_sz;
749 u32 page_size_cap;
750 u32 reserved_lkey;
751 int mtpt_entry_sz;
752 int qpc_sz;
753 int irrl_entry_sz;
754 int trrl_entry_sz;
755 int cqc_entry_sz;
756 int sccc_sz;
757 int qpc_timer_entry_sz;
758 int cqc_timer_entry_sz;
759 int srqc_entry_sz;
760 int idx_entry_sz;
761 u32 pbl_ba_pg_sz;
762 u32 pbl_buf_pg_sz;
763 u32 pbl_hop_num;
764 int aeqe_depth;
765 int ceqe_depth;
766 u32 aeqe_size;
767 u32 ceqe_size;
768 enum ib_mtu max_mtu;
769 u32 qpc_bt_num;
770 u32 qpc_timer_bt_num;
771 u32 srqc_bt_num;
772 u32 cqc_bt_num;
773 u32 cqc_timer_bt_num;
774 u32 mpt_bt_num;
775 u32 eqc_bt_num;
776 u32 smac_bt_num;
777 u32 sgid_bt_num;
778 u32 sccc_bt_num;
779 u32 gmv_bt_num;
780 u32 qpc_ba_pg_sz;
781 u32 qpc_buf_pg_sz;
782 u32 qpc_hop_num;
783 u32 srqc_ba_pg_sz;
784 u32 srqc_buf_pg_sz;
785 u32 srqc_hop_num;
786 u32 cqc_ba_pg_sz;
787 u32 cqc_buf_pg_sz;
788 u32 cqc_hop_num;
789 u32 mpt_ba_pg_sz;
790 u32 mpt_buf_pg_sz;
791 u32 mpt_hop_num;
792 u32 mtt_ba_pg_sz;
793 u32 mtt_buf_pg_sz;
794 u32 mtt_hop_num;
795 u32 wqe_sq_hop_num;
796 u32 wqe_sge_hop_num;
797 u32 wqe_rq_hop_num;
798 u32 sccc_ba_pg_sz;
799 u32 sccc_buf_pg_sz;
800 u32 sccc_hop_num;
801 u32 qpc_timer_ba_pg_sz;
802 u32 qpc_timer_buf_pg_sz;
803 u32 qpc_timer_hop_num;
804 u32 cqc_timer_ba_pg_sz;
805 u32 cqc_timer_buf_pg_sz;
806 u32 cqc_timer_hop_num;
807 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
808 u32 cqe_buf_pg_sz;
809 u32 cqe_hop_num;
810 u32 srqwqe_ba_pg_sz;
811 u32 srqwqe_buf_pg_sz;
812 u32 srqwqe_hop_num;
813 u32 idx_ba_pg_sz;
814 u32 idx_buf_pg_sz;
815 u32 idx_hop_num;
816 u32 eqe_ba_pg_sz;
817 u32 eqe_buf_pg_sz;
818 u32 eqe_hop_num;
819 u32 gmv_entry_num;
820 u32 gmv_entry_sz;
821 u32 gmv_ba_pg_sz;
822 u32 gmv_buf_pg_sz;
823 u32 gmv_hop_num;
824 u32 sl_num;
825 u32 llm_buf_pg_sz;
826 u32 chunk_sz; /* chunk size in non multihop mode */
827 u64 flags;
828 u16 default_ceq_max_cnt;
829 u16 default_ceq_period;
830 u16 default_aeq_max_cnt;
831 u16 default_aeq_period;
832 u16 default_aeq_arm_st;
833 u16 default_ceq_arm_st;
834 enum cong_type cong_type;
835 };
836
837 enum hns_roce_device_state {
838 HNS_ROCE_DEVICE_STATE_INITED,
839 HNS_ROCE_DEVICE_STATE_RST_DOWN,
840 HNS_ROCE_DEVICE_STATE_UNINIT,
841 };
842
843 struct hns_roce_hw {
844 int (*cmq_init)(struct hns_roce_dev *hr_dev);
845 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
846 int (*hw_profile)(struct hns_roce_dev *hr_dev);
847 int (*hw_init)(struct hns_roce_dev *hr_dev);
848 void (*hw_exit)(struct hns_roce_dev *hr_dev);
849 int (*post_mbox)(struct hns_roce_dev *hr_dev,
850 struct hns_roce_mbox_msg *mbox_msg);
851 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
852 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
853 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
854 const union ib_gid *gid, const struct ib_gid_attr *attr);
855 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
856 const u8 *addr);
857 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
858 struct hns_roce_mr *mr);
859 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
860 struct hns_roce_mr *mr, int flags,
861 void *mb_buf);
862 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
863 struct hns_roce_mr *mr);
864 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
865 void (*write_cqc)(struct hns_roce_dev *hr_dev,
866 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
867 dma_addr_t dma_handle);
868 int (*set_hem)(struct hns_roce_dev *hr_dev,
869 struct hns_roce_hem_table *table, int obj, u32 step_idx);
870 int (*clear_hem)(struct hns_roce_dev *hr_dev,
871 struct hns_roce_hem_table *table, int obj,
872 u32 step_idx);
873 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
874 int attr_mask, enum ib_qp_state cur_state,
875 enum ib_qp_state new_state, struct ib_udata *udata);
876 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
877 struct hns_roce_qp *hr_qp);
878 void (*dereg_mr)(struct hns_roce_dev *hr_dev);
879 int (*init_eq)(struct hns_roce_dev *hr_dev);
880 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
881 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
882 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer);
883 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer);
884 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer);
885 const struct ib_device_ops *hns_roce_dev_ops;
886 const struct ib_device_ops *hns_roce_dev_srq_ops;
887 };
888
889 struct hns_roce_dev {
890 struct ib_device ib_dev;
891 struct pci_dev *pci_dev;
892 struct device *dev;
893 struct hns_roce_uar priv_uar;
894 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
895 spinlock_t sm_lock;
896 bool active;
897 bool is_reset;
898 bool dis_db;
899 unsigned long reset_cnt;
900 struct hns_roce_ib_iboe iboe;
901 enum hns_roce_device_state state;
902 struct list_head qp_list; /* list of all qps on this dev */
903 spinlock_t qp_list_lock; /* protect qp_list */
904 struct list_head dip_list; /* list of all dest ips on this dev */
905 spinlock_t dip_list_lock; /* protect dip_list */
906
907 struct list_head pgdir_list;
908 struct mutex pgdir_mutex;
909 int irq[HNS_ROCE_MAX_IRQ_NUM];
910 u8 __iomem *reg_base;
911 void __iomem *mem_base;
912 struct hns_roce_caps caps;
913 struct xarray qp_table_xa;
914
915 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
916 u64 sys_image_guid;
917 u32 vendor_id;
918 u32 vendor_part_id;
919 u32 hw_rev;
920 void __iomem *priv_addr;
921
922 struct hns_roce_cmdq cmd;
923 struct hns_roce_ida pd_ida;
924 struct hns_roce_ida xrcd_ida;
925 struct hns_roce_ida uar_ida;
926 struct hns_roce_mr_table mr_table;
927 struct hns_roce_cq_table cq_table;
928 struct hns_roce_srq_table srq_table;
929 struct hns_roce_qp_table qp_table;
930 struct hns_roce_eq_table eq_table;
931 struct hns_roce_hem_table qpc_timer_table;
932 struct hns_roce_hem_table cqc_timer_table;
933 /* GMV is the memory area that the driver allocates for the hardware
934 * to store SGID, SMAC and VLAN information.
935 */
936 struct hns_roce_hem_table gmv_table;
937
938 int cmd_mod;
939 int loop_idc;
940 u32 sdb_offset;
941 u32 odb_offset;
942 const struct hns_roce_hw *hw;
943 void *priv;
944 struct workqueue_struct *irq_workq;
945 struct work_struct ecc_work;
946 u32 func_num;
947 u32 is_vf;
948 u32 cong_algo_tmpl_id;
949 u64 dwqe_page;
950 };
951
to_hr_dev(struct ib_device * ib_dev)952 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
953 {
954 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
955 }
956
957 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)958 *to_hr_ucontext(struct ib_ucontext *ibucontext)
959 {
960 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
961 }
962
to_hr_pd(struct ib_pd * ibpd)963 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
964 {
965 return container_of(ibpd, struct hns_roce_pd, ibpd);
966 }
967
to_hr_xrcd(struct ib_xrcd * ibxrcd)968 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
969 {
970 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
971 }
972
to_hr_ah(struct ib_ah * ibah)973 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
974 {
975 return container_of(ibah, struct hns_roce_ah, ibah);
976 }
977
to_hr_mr(struct ib_mr * ibmr)978 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
979 {
980 return container_of(ibmr, struct hns_roce_mr, ibmr);
981 }
982
to_hr_mw(struct ib_mw * ibmw)983 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
984 {
985 return container_of(ibmw, struct hns_roce_mw, ibmw);
986 }
987
to_hr_qp(struct ib_qp * ibqp)988 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
989 {
990 return container_of(ibqp, struct hns_roce_qp, ibqp);
991 }
992
to_hr_cq(struct ib_cq * ib_cq)993 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
994 {
995 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
996 }
997
to_hr_srq(struct ib_srq * ibsrq)998 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
999 {
1000 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1001 }
1002
1003 static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1004 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1005 {
1006 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1007 }
1008
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1009 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1010 {
1011 writeq(*(u64 *)val, dest);
1012 }
1013
1014 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1015 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1016 {
1017 return xa_load(&hr_dev->qp_table_xa, qpn);
1018 }
1019
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1020 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1021 unsigned int offset)
1022 {
1023 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1024 (offset & ((1 << buf->trunk_shift) - 1));
1025 }
1026
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1027 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1028 unsigned int offset)
1029 {
1030 return buf->trunk_list[offset >> buf->trunk_shift].map +
1031 (offset & ((1 << buf->trunk_shift) - 1));
1032 }
1033
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1034 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1035 {
1036 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1037 }
1038
1039 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1040
to_hr_hw_page_addr(u64 addr)1041 static inline u64 to_hr_hw_page_addr(u64 addr)
1042 {
1043 return addr >> HNS_HW_PAGE_SHIFT;
1044 }
1045
to_hr_hw_page_shift(u32 page_shift)1046 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1047 {
1048 return page_shift - HNS_HW_PAGE_SHIFT;
1049 }
1050
to_hr_hem_hopnum(u32 hopnum,u32 count)1051 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1052 {
1053 if (count > 0)
1054 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1055
1056 return 0;
1057 }
1058
to_hr_hem_entries_size(u32 count,u32 buf_shift)1059 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1060 {
1061 return hr_hw_page_align(count << buf_shift);
1062 }
1063
to_hr_hem_entries_count(u32 count,u32 buf_shift)1064 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1065 {
1066 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1067 }
1068
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1069 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1070 {
1071 if (!count)
1072 return 0;
1073
1074 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1075 }
1076
1077 #define DSCP_SHIFT 2
1078
get_tclass(const struct ib_global_route * grh)1079 static inline u8 get_tclass(const struct ib_global_route *grh)
1080 {
1081 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1082 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1083 }
1084
1085 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1086 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1087
1088 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1089 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1090 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1091 u64 out_param);
1092 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1093 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1094
1095 /* hns roce hw need current block and next block addr from mtt */
1096 #define MTT_MIN_COUNT 2
1097 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1098 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1099 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1100 struct hns_roce_buf_attr *buf_attr,
1101 unsigned int page_shift, struct ib_udata *udata,
1102 unsigned long user_addr);
1103 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1104 struct hns_roce_mtr *mtr);
1105 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1106 dma_addr_t *pages, unsigned int page_cnt);
1107
1108 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1109 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1110 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1111 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1112 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1113 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1114
1115 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1116 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1117 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1118
1119 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1120
1121 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1122 struct ib_udata *udata);
1123 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1124 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1125 {
1126 return 0;
1127 }
1128
1129 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1130 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1131
1132 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1133 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1134 u64 virt_addr, int access_flags,
1135 struct ib_udata *udata);
1136 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1137 u64 length, u64 virt_addr,
1138 int mr_access_flags, struct ib_pd *pd,
1139 struct ib_udata *udata);
1140 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1141 u32 max_num_sg);
1142 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1143 unsigned int *sg_offset);
1144 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1145 unsigned long key_to_hw_index(u32 key);
1146
1147 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1148 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1149
1150 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1151 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1152 u32 page_shift, u32 flags);
1153
1154 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1155 int buf_cnt, struct hns_roce_buf *buf,
1156 unsigned int page_shift);
1157 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1158 int buf_cnt, struct ib_umem *umem,
1159 unsigned int page_shift);
1160
1161 int hns_roce_create_srq(struct ib_srq *srq,
1162 struct ib_srq_init_attr *srq_init_attr,
1163 struct ib_udata *udata);
1164 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1165 enum ib_srq_attr_mask srq_attr_mask,
1166 struct ib_udata *udata);
1167 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1168
1169 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1170 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1171
1172 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1173 struct ib_udata *udata);
1174 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1175 int attr_mask, struct ib_udata *udata);
1176 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1177 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1178 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1179 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1180 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1181 struct ib_cq *ib_cq);
1182 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1183 struct hns_roce_cq *recv_cq);
1184 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1185 struct hns_roce_cq *recv_cq);
1186 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1187 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1188 struct ib_udata *udata);
1189 __be32 send_ieth(const struct ib_send_wr *wr);
1190 int to_hr_qp_type(int qp_type);
1191
1192 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1193 struct ib_udata *udata);
1194
1195 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1196 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1197 struct hns_roce_db *db);
1198 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1199 struct hns_roce_db *db);
1200 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1201 int order);
1202 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1203
1204 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1205 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1206 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1207 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1208 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1209 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1210 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1211 int hns_roce_init(struct hns_roce_dev *hr_dev);
1212 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1213 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq);
1214 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq);
1215 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp);
1216 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp);
1217 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr);
1218 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr);
1219 struct hns_user_mmap_entry *
1220 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1221 size_t length,
1222 enum hns_roce_mmap_type mmap_type);
1223 #endif /* _HNS_ROCE_DEVICE_H */
1224