1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/percpu.h>
20 #include <linux/psci.h>
21 #include <asm/arch_gicv3.h>
22 #include <asm/barrier.h>
23 #include <asm/cpufeature.h>
24 #include <asm/cputype.h>
25 #include <asm/daifflags.h>
26 #include <asm/fpsimd.h>
27 #include <asm/kvm.h>
28 #include <asm/kvm_asm.h>
29
30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
31
32 #define KVM_HALT_POLL_NS_DEFAULT 500000
33
34 #include <kvm/arm_vgic.h>
35 #include <kvm/arm_arch_timer.h>
36 #include <kvm/arm_pmu.h>
37
38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
39
40 #define KVM_VCPU_MAX_FEATURES 7
41
42 #define KVM_REQ_SLEEP \
43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
48 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
49 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
50
51 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
52 KVM_DIRTY_LOG_INITIALLY_SET)
53
54 #define KVM_HAVE_MMU_RWLOCK
55
56 /*
57 * Mode of operation configurable with kvm-arm.mode early param.
58 * See Documentation/admin-guide/kernel-parameters.txt for more information.
59 */
60 enum kvm_mode {
61 KVM_MODE_DEFAULT,
62 KVM_MODE_PROTECTED,
63 KVM_MODE_NV,
64 KVM_MODE_NONE,
65 };
66 #ifdef CONFIG_KVM
67 enum kvm_mode kvm_get_mode(void);
68 #else
kvm_get_mode(void)69 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
70 #endif
71
72 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
73
74 extern unsigned int __ro_after_init kvm_sve_max_vl;
75 int __init kvm_arm_init_sve(void);
76
77 u32 __attribute_const__ kvm_target_cpu(void);
78 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
79 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
80
81 struct kvm_hyp_memcache {
82 phys_addr_t head;
83 unsigned long nr_pages;
84 };
85
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))86 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
87 phys_addr_t *p,
88 phys_addr_t (*to_pa)(void *virt))
89 {
90 *p = mc->head;
91 mc->head = to_pa(p);
92 mc->nr_pages++;
93 }
94
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))95 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
96 void *(*to_va)(phys_addr_t phys))
97 {
98 phys_addr_t *p = to_va(mc->head);
99
100 if (!mc->nr_pages)
101 return NULL;
102
103 mc->head = *p;
104 mc->nr_pages--;
105
106 return p;
107 }
108
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)109 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
110 unsigned long min_pages,
111 void *(*alloc_fn)(void *arg),
112 phys_addr_t (*to_pa)(void *virt),
113 void *arg)
114 {
115 while (mc->nr_pages < min_pages) {
116 phys_addr_t *p = alloc_fn(arg);
117
118 if (!p)
119 return -ENOMEM;
120 push_hyp_memcache(mc, p, to_pa);
121 }
122
123 return 0;
124 }
125
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)126 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
127 void (*free_fn)(void *virt, void *arg),
128 void *(*to_va)(phys_addr_t phys),
129 void *arg)
130 {
131 while (mc->nr_pages)
132 free_fn(pop_hyp_memcache(mc, to_va), arg);
133 }
134
135 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
136 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
137
138 struct kvm_vmid {
139 atomic64_t id;
140 };
141
142 struct kvm_s2_mmu {
143 struct kvm_vmid vmid;
144
145 /*
146 * stage2 entry level table
147 *
148 * Two kvm_s2_mmu structures in the same VM can point to the same
149 * pgd here. This happens when running a guest using a
150 * translation regime that isn't affected by its own stage-2
151 * translation, such as a non-VHE hypervisor running at vEL2, or
152 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
153 * canonical stage-2 page tables.
154 */
155 phys_addr_t pgd_phys;
156 struct kvm_pgtable *pgt;
157
158 /* The last vcpu id that ran on each physical CPU */
159 int __percpu *last_vcpu_ran;
160
161 struct kvm_arch *arch;
162 };
163
164 struct kvm_arch_memory_slot {
165 };
166
167 /**
168 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
169 *
170 * @std_bmap: Bitmap of standard secure service calls
171 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
172 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
173 */
174 struct kvm_smccc_features {
175 unsigned long std_bmap;
176 unsigned long std_hyp_bmap;
177 unsigned long vendor_hyp_bmap;
178 };
179
180 typedef unsigned int pkvm_handle_t;
181
182 struct kvm_protected_vm {
183 pkvm_handle_t handle;
184 struct kvm_hyp_memcache teardown_mc;
185 };
186
187 struct kvm_arch {
188 struct kvm_s2_mmu mmu;
189
190 /* VTCR_EL2 value for this VM */
191 u64 vtcr;
192
193 /* Interrupt controller */
194 struct vgic_dist vgic;
195
196 /* Mandated version of PSCI */
197 u32 psci_version;
198
199 /*
200 * If we encounter a data abort without valid instruction syndrome
201 * information, report this to user space. User space can (and
202 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
203 * supported.
204 */
205 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
206 /* Memory Tagging Extension enabled for the guest */
207 #define KVM_ARCH_FLAG_MTE_ENABLED 1
208 /* At least one vCPU has ran in the VM */
209 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
210 /*
211 * The following two bits are used to indicate the guest's EL1
212 * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT
213 * bit is valid only when KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED is set.
214 * Otherwise, the guest's EL1 register width has not yet been
215 * determined yet.
216 */
217 #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3
218 #define KVM_ARCH_FLAG_EL1_32BIT 4
219 /* PSCI SYSTEM_SUSPEND enabled for the guest */
220 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
221
222 unsigned long flags;
223
224 /*
225 * VM-wide PMU filter, implemented as a bitmap and big enough for
226 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
227 */
228 unsigned long *pmu_filter;
229 struct arm_pmu *arm_pmu;
230
231 cpumask_var_t supported_cpus;
232
233 u8 pfr0_csv2;
234 u8 pfr0_csv3;
235 struct {
236 u8 imp:4;
237 u8 unimp:4;
238 } dfr0_pmuver;
239
240 /* Hypercall features firmware registers' descriptor */
241 struct kvm_smccc_features smccc_feat;
242
243 /*
244 * For an untrusted host VM, 'pkvm.handle' is used to lookup
245 * the associated pKVM instance in the hypervisor.
246 */
247 struct kvm_protected_vm pkvm;
248 };
249
250 struct kvm_vcpu_fault_info {
251 u64 esr_el2; /* Hyp Syndrom Register */
252 u64 far_el2; /* Hyp Fault Address Register */
253 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
254 u64 disr_el1; /* Deferred [SError] Status Register */
255 };
256
257 enum vcpu_sysreg {
258 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
259 MPIDR_EL1, /* MultiProcessor Affinity Register */
260 CLIDR_EL1, /* Cache Level ID Register */
261 CSSELR_EL1, /* Cache Size Selection Register */
262 SCTLR_EL1, /* System Control Register */
263 ACTLR_EL1, /* Auxiliary Control Register */
264 CPACR_EL1, /* Coprocessor Access Control */
265 ZCR_EL1, /* SVE Control */
266 TTBR0_EL1, /* Translation Table Base Register 0 */
267 TTBR1_EL1, /* Translation Table Base Register 1 */
268 TCR_EL1, /* Translation Control Register */
269 ESR_EL1, /* Exception Syndrome Register */
270 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
271 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
272 FAR_EL1, /* Fault Address Register */
273 MAIR_EL1, /* Memory Attribute Indirection Register */
274 VBAR_EL1, /* Vector Base Address Register */
275 CONTEXTIDR_EL1, /* Context ID Register */
276 TPIDR_EL0, /* Thread ID, User R/W */
277 TPIDRRO_EL0, /* Thread ID, User R/O */
278 TPIDR_EL1, /* Thread ID, Privileged */
279 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
280 CNTKCTL_EL1, /* Timer Control Register (EL1) */
281 PAR_EL1, /* Physical Address Register */
282 MDSCR_EL1, /* Monitor Debug System Control Register */
283 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
284 OSLSR_EL1, /* OS Lock Status Register */
285 DISR_EL1, /* Deferred Interrupt Status Register */
286
287 /* Performance Monitors Registers */
288 PMCR_EL0, /* Control Register */
289 PMSELR_EL0, /* Event Counter Selection Register */
290 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
291 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
292 PMCCNTR_EL0, /* Cycle Counter Register */
293 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
294 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
295 PMCCFILTR_EL0, /* Cycle Count Filter Register */
296 PMCNTENSET_EL0, /* Count Enable Set Register */
297 PMINTENSET_EL1, /* Interrupt Enable Set Register */
298 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
299 PMUSERENR_EL0, /* User Enable Register */
300
301 /* Pointer Authentication Registers in a strict increasing order. */
302 APIAKEYLO_EL1,
303 APIAKEYHI_EL1,
304 APIBKEYLO_EL1,
305 APIBKEYHI_EL1,
306 APDAKEYLO_EL1,
307 APDAKEYHI_EL1,
308 APDBKEYLO_EL1,
309 APDBKEYHI_EL1,
310 APGAKEYLO_EL1,
311 APGAKEYHI_EL1,
312
313 ELR_EL1,
314 SP_EL1,
315 SPSR_EL1,
316
317 CNTVOFF_EL2,
318 CNTV_CVAL_EL0,
319 CNTV_CTL_EL0,
320 CNTP_CVAL_EL0,
321 CNTP_CTL_EL0,
322
323 /* Memory Tagging Extension registers */
324 RGSR_EL1, /* Random Allocation Tag Seed Register */
325 GCR_EL1, /* Tag Control Register */
326 TFSR_EL1, /* Tag Fault Status Register (EL1) */
327 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
328
329 /* 32bit specific registers. */
330 DACR32_EL2, /* Domain Access Control Register */
331 IFSR32_EL2, /* Instruction Fault Status Register */
332 FPEXC32_EL2, /* Floating-Point Exception Control Register */
333 DBGVCR32_EL2, /* Debug Vector Catch Register */
334
335 /* EL2 registers */
336 VPIDR_EL2, /* Virtualization Processor ID Register */
337 VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */
338 SCTLR_EL2, /* System Control Register (EL2) */
339 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
340 HCR_EL2, /* Hypervisor Configuration Register */
341 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
342 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
343 HSTR_EL2, /* Hypervisor System Trap Register */
344 HACR_EL2, /* Hypervisor Auxiliary Control Register */
345 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
346 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
347 TCR_EL2, /* Translation Control Register (EL2) */
348 VTTBR_EL2, /* Virtualization Translation Table Base Register */
349 VTCR_EL2, /* Virtualization Translation Control Register */
350 SPSR_EL2, /* EL2 saved program status register */
351 ELR_EL2, /* EL2 exception link register */
352 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
353 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
354 ESR_EL2, /* Exception Syndrome Register (EL2) */
355 FAR_EL2, /* Fault Address Register (EL2) */
356 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
357 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
358 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
359 VBAR_EL2, /* Vector Base Address Register (EL2) */
360 RVBAR_EL2, /* Reset Vector Base Address Register */
361 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
362 TPIDR_EL2, /* EL2 Software Thread ID Register */
363 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
364 SP_EL2, /* EL2 Stack Pointer */
365
366 NR_SYS_REGS /* Nothing after this line! */
367 };
368
369 struct kvm_cpu_context {
370 struct user_pt_regs regs; /* sp = sp_el0 */
371
372 u64 spsr_abt;
373 u64 spsr_und;
374 u64 spsr_irq;
375 u64 spsr_fiq;
376
377 struct user_fpsimd_state fp_regs;
378
379 u64 sys_regs[NR_SYS_REGS];
380
381 struct kvm_vcpu *__hyp_running_vcpu;
382 };
383
384 struct kvm_host_data {
385 struct kvm_cpu_context host_ctxt;
386 };
387
388 struct kvm_host_psci_config {
389 /* PSCI version used by host. */
390 u32 version;
391
392 /* Function IDs used by host if version is v0.1. */
393 struct psci_0_1_function_ids function_ids_0_1;
394
395 bool psci_0_1_cpu_suspend_implemented;
396 bool psci_0_1_cpu_on_implemented;
397 bool psci_0_1_cpu_off_implemented;
398 bool psci_0_1_migrate_implemented;
399 };
400
401 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
402 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
403
404 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
405 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
406
407 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
408 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
409
410 struct vcpu_reset_state {
411 unsigned long pc;
412 unsigned long r0;
413 bool be;
414 bool reset;
415 };
416
417 struct kvm_vcpu_arch {
418 struct kvm_cpu_context ctxt;
419
420 /*
421 * Guest floating point state
422 *
423 * The architecture has two main floating point extensions,
424 * the original FPSIMD and SVE. These have overlapping
425 * register views, with the FPSIMD V registers occupying the
426 * low 128 bits of the SVE Z registers. When the core
427 * floating point code saves the register state of a task it
428 * records which view it saved in fp_type.
429 */
430 void *sve_state;
431 enum fp_type fp_type;
432 unsigned int sve_max_vl;
433 u64 svcr;
434
435 /* Stage 2 paging state used by the hardware on next switch */
436 struct kvm_s2_mmu *hw_mmu;
437
438 /* Values of trap registers for the guest. */
439 u64 hcr_el2;
440 u64 mdcr_el2;
441 u64 cptr_el2;
442
443 /* Values of trap registers for the host before guest entry. */
444 u64 mdcr_el2_host;
445
446 /* Exception Information */
447 struct kvm_vcpu_fault_info fault;
448
449 /* Ownership of the FP regs */
450 enum {
451 FP_STATE_FREE,
452 FP_STATE_HOST_OWNED,
453 FP_STATE_GUEST_OWNED,
454 } fp_state;
455
456 /* Configuration flags, set once and for all before the vcpu can run */
457 u8 cflags;
458
459 /* Input flags to the hypervisor code, potentially cleared after use */
460 u8 iflags;
461
462 /* State flags for kernel bookkeeping, unused by the hypervisor code */
463 u8 sflags;
464
465 /*
466 * Don't run the guest (internal implementation need).
467 *
468 * Contrary to the flags above, this is set/cleared outside of
469 * a vcpu context, and thus cannot be mixed with the flags
470 * themselves (or the flag accesses need to be made atomic).
471 */
472 bool pause;
473
474 /*
475 * We maintain more than a single set of debug registers to support
476 * debugging the guest from the host and to maintain separate host and
477 * guest state during world switches. vcpu_debug_state are the debug
478 * registers of the vcpu as the guest sees them. host_debug_state are
479 * the host registers which are saved and restored during
480 * world switches. external_debug_state contains the debug
481 * values we want to debug the guest. This is set via the
482 * KVM_SET_GUEST_DEBUG ioctl.
483 *
484 * debug_ptr points to the set of debug registers that should be loaded
485 * onto the hardware when running the guest.
486 */
487 struct kvm_guest_debug_arch *debug_ptr;
488 struct kvm_guest_debug_arch vcpu_debug_state;
489 struct kvm_guest_debug_arch external_debug_state;
490
491 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
492 struct task_struct *parent_task;
493
494 struct {
495 /* {Break,watch}point registers */
496 struct kvm_guest_debug_arch regs;
497 /* Statistical profiling extension */
498 u64 pmscr_el1;
499 /* Self-hosted trace */
500 u64 trfcr_el1;
501 } host_debug_state;
502
503 /* VGIC state */
504 struct vgic_cpu vgic_cpu;
505 struct arch_timer_cpu timer_cpu;
506 struct kvm_pmu pmu;
507
508 /*
509 * Guest registers we preserve during guest debugging.
510 *
511 * These shadow registers are updated by the kvm_handle_sys_reg
512 * trap handler if the guest accesses or updates them while we
513 * are using guest debug.
514 */
515 struct {
516 u32 mdscr_el1;
517 bool pstate_ss;
518 } guest_debug_preserved;
519
520 /* vcpu power state */
521 struct kvm_mp_state mp_state;
522
523 /* Cache some mmu pages needed inside spinlock regions */
524 struct kvm_mmu_memory_cache mmu_page_cache;
525
526 /* Target CPU and feature flags */
527 int target;
528 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
529
530 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
531 u64 vsesr_el2;
532
533 /* Additional reset state */
534 struct vcpu_reset_state reset_state;
535
536 /* Guest PV state */
537 struct {
538 u64 last_steal;
539 gpa_t base;
540 } steal;
541
542 /* Per-vcpu CCSIDR override or NULL */
543 u32 *ccsidr;
544 };
545
546 /*
547 * Each 'flag' is composed of a comma-separated triplet:
548 *
549 * - the flag-set it belongs to in the vcpu->arch structure
550 * - the value for that flag
551 * - the mask for that flag
552 *
553 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
554 * unpack_vcpu_flag() extract the flag value from the triplet for
555 * direct use outside of the flag accessors.
556 */
557 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
558
559 #define __unpack_flag(_set, _f, _m) _f
560 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
561
562 #define __build_check_flag(v, flagset, f, m) \
563 do { \
564 typeof(v->arch.flagset) *_fset; \
565 \
566 /* Check that the flags fit in the mask */ \
567 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
568 /* Check that the flags fit in the type */ \
569 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
570 } while (0)
571
572 #define __vcpu_get_flag(v, flagset, f, m) \
573 ({ \
574 __build_check_flag(v, flagset, f, m); \
575 \
576 v->arch.flagset & (m); \
577 })
578
579 #define __vcpu_set_flag(v, flagset, f, m) \
580 do { \
581 typeof(v->arch.flagset) *fset; \
582 \
583 __build_check_flag(v, flagset, f, m); \
584 \
585 fset = &v->arch.flagset; \
586 if (HWEIGHT(m) > 1) \
587 *fset &= ~(m); \
588 *fset |= (f); \
589 } while (0)
590
591 #define __vcpu_clear_flag(v, flagset, f, m) \
592 do { \
593 typeof(v->arch.flagset) *fset; \
594 \
595 __build_check_flag(v, flagset, f, m); \
596 \
597 fset = &v->arch.flagset; \
598 *fset &= ~(m); \
599 } while (0)
600
601 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
602 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
603 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
604
605 /* SVE exposed to guest */
606 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0))
607 /* SVE config completed */
608 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
609 /* PTRAUTH exposed to guest */
610 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2))
611
612 /* Exception pending */
613 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
614 /*
615 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
616 * be set together with an exception...
617 */
618 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
619 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
620 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
621
622 /* Helpers to encode exceptions with minimum fuss */
623 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
624 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
625 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
626
627 /*
628 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
629 * values:
630 *
631 * For AArch32 EL1:
632 */
633 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
634 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
635 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
636 /* For AArch64: */
637 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
638 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
639 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
640 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
641 /* For AArch64 with NV: */
642 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
643 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
644 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
645 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
646 /* Guest debug is live */
647 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
648 /* Save SPE context if active */
649 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
650 /* Save TRBE context if active */
651 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
652 /* vcpu running in HYP context */
653 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
654
655 /* SVE enabled for host EL0 */
656 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
657 /* SME enabled for EL0 */
658 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1))
659 /* Physical CPU not in supported_cpus */
660 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
661 /* WFIT instruction trapped */
662 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
663 /* vcpu system registers loaded on physical CPU */
664 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
665 /* Software step state is Active-pending */
666 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
667
668
669 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
670 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
671 sve_ffr_offset((vcpu)->arch.sve_max_vl))
672
673 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
674
675 #define vcpu_sve_state_size(vcpu) ({ \
676 size_t __size_ret; \
677 unsigned int __vcpu_vq; \
678 \
679 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
680 __size_ret = 0; \
681 } else { \
682 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
683 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
684 } \
685 \
686 __size_ret; \
687 })
688
689 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
690 KVM_GUESTDBG_USE_SW_BP | \
691 KVM_GUESTDBG_USE_HW | \
692 KVM_GUESTDBG_SINGLESTEP)
693
694 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
695 vcpu_get_flag(vcpu, GUEST_HAS_SVE))
696
697 #ifdef CONFIG_ARM64_PTR_AUTH
698 #define vcpu_has_ptrauth(vcpu) \
699 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
700 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
701 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
702 #else
703 #define vcpu_has_ptrauth(vcpu) false
704 #endif
705
706 #define vcpu_on_unsupported_cpu(vcpu) \
707 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
708
709 #define vcpu_set_on_unsupported_cpu(vcpu) \
710 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
711
712 #define vcpu_clear_on_unsupported_cpu(vcpu) \
713 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
714
715 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
716
717 /*
718 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
719 * memory backed version of a register, and not the one most recently
720 * accessed by a running VCPU. For example, for userspace access or
721 * for system registers that are never context switched, but only
722 * emulated.
723 */
724 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
725
726 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
727
728 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
729
730 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
731 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
732
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)733 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
734 {
735 /*
736 * *** VHE ONLY ***
737 *
738 * System registers listed in the switch are not saved on every
739 * exit from the guest but are only saved on vcpu_put.
740 *
741 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
742 * should never be listed below, because the guest cannot modify its
743 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
744 * thread when emulating cross-VCPU communication.
745 */
746 if (!has_vhe())
747 return false;
748
749 switch (reg) {
750 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
751 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
752 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
753 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
754 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
755 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
756 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
757 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
758 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
759 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
760 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
761 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
762 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
763 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
764 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
765 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
766 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
767 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
768 case PAR_EL1: *val = read_sysreg_par(); break;
769 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
770 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
771 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
772 default: return false;
773 }
774
775 return true;
776 }
777
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)778 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
779 {
780 /*
781 * *** VHE ONLY ***
782 *
783 * System registers listed in the switch are not restored on every
784 * entry to the guest but are only restored on vcpu_load.
785 *
786 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
787 * should never be listed below, because the MPIDR should only be set
788 * once, before running the VCPU, and never changed later.
789 */
790 if (!has_vhe())
791 return false;
792
793 switch (reg) {
794 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
795 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
796 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
797 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
798 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
799 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
800 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
801 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
802 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
803 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
804 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
805 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
806 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
807 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
808 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
809 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
810 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
811 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
812 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
813 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
814 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
815 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
816 default: return false;
817 }
818
819 return true;
820 }
821
822 struct kvm_vm_stat {
823 struct kvm_vm_stat_generic generic;
824 };
825
826 struct kvm_vcpu_stat {
827 struct kvm_vcpu_stat_generic generic;
828 u64 hvc_exit_stat;
829 u64 wfe_exit_stat;
830 u64 wfi_exit_stat;
831 u64 mmio_exit_user;
832 u64 mmio_exit_kernel;
833 u64 signal_exits;
834 u64 exits;
835 };
836
837 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
838 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
839 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
840 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
841 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
842
843 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
844 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
845
846 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
847 struct kvm_vcpu_events *events);
848
849 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
850 struct kvm_vcpu_events *events);
851
852 #define KVM_ARCH_WANT_MMU_NOTIFIER
853
854 void kvm_arm_halt_guest(struct kvm *kvm);
855 void kvm_arm_resume_guest(struct kvm *kvm);
856
857 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
858
859 #ifndef __KVM_NVHE_HYPERVISOR__
860 #define kvm_call_hyp_nvhe(f, ...) \
861 ({ \
862 struct arm_smccc_res res; \
863 \
864 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
865 ##__VA_ARGS__, &res); \
866 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
867 \
868 res.a1; \
869 })
870
871 /*
872 * The couple of isb() below are there to guarantee the same behaviour
873 * on VHE as on !VHE, where the eret to EL1 acts as a context
874 * synchronization event.
875 */
876 #define kvm_call_hyp(f, ...) \
877 do { \
878 if (has_vhe()) { \
879 f(__VA_ARGS__); \
880 isb(); \
881 } else { \
882 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
883 } \
884 } while(0)
885
886 #define kvm_call_hyp_ret(f, ...) \
887 ({ \
888 typeof(f(__VA_ARGS__)) ret; \
889 \
890 if (has_vhe()) { \
891 ret = f(__VA_ARGS__); \
892 isb(); \
893 } else { \
894 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
895 } \
896 \
897 ret; \
898 })
899 #else /* __KVM_NVHE_HYPERVISOR__ */
900 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
901 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
902 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
903 #endif /* __KVM_NVHE_HYPERVISOR__ */
904
905 void force_vm_exit(const cpumask_t *mask);
906
907 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
908 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
909
910 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
911 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
912 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
913 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
914 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
915 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
916 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
917
918 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
919
920 int __init kvm_sys_reg_table_init(void);
921
922 /* MMIO helpers */
923 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
924 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
925
926 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
927 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
928
929 /*
930 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
931 * arrived in guest context. For arm64, any event that arrives while a vCPU is
932 * loaded is considered to be "in guest".
933 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)934 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
935 {
936 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
937 }
938
939 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
940 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
941 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
942
943 bool kvm_arm_pvtime_supported(void);
944 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
945 struct kvm_device_attr *attr);
946 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
947 struct kvm_device_attr *attr);
948 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
949 struct kvm_device_attr *attr);
950
951 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
952 int __init kvm_arm_vmid_alloc_init(void);
953 void __init kvm_arm_vmid_alloc_free(void);
954 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
955 void kvm_arm_vmid_clear_active(void);
956
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)957 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
958 {
959 vcpu_arch->steal.base = INVALID_GPA;
960 }
961
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)962 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
963 {
964 return (vcpu_arch->steal.base != INVALID_GPA);
965 }
966
967 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
968
969 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
970
971 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
972
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)973 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
974 {
975 /* The host's MPIDR is immutable, so let's set it up at boot time */
976 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
977 }
978
kvm_system_needs_idmapped_vectors(void)979 static inline bool kvm_system_needs_idmapped_vectors(void)
980 {
981 return cpus_have_const_cap(ARM64_SPECTRE_V3A);
982 }
983
984 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
985
kvm_arch_sync_events(struct kvm * kvm)986 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)987 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
988
989 void kvm_arm_init_debug(void);
990 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
991 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
992 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
993 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
994
995 #define kvm_vcpu_os_lock_enabled(vcpu) \
996 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
997
998 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
999 struct kvm_device_attr *attr);
1000 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1001 struct kvm_device_attr *attr);
1002 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1003 struct kvm_device_attr *attr);
1004
1005 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1006 struct kvm_arm_copy_mte_tags *copy_tags);
1007
1008 /* Guest/host FPSIMD coordination helpers */
1009 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1010 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1011 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1012 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1013 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1014 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1015
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1016 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1017 {
1018 return (!has_vhe() && attr->exclude_host);
1019 }
1020
1021 /* Flags for host debug state */
1022 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1023 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1024
1025 #ifdef CONFIG_KVM
1026 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1027 void kvm_clr_pmu_events(u32 clr);
1028 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)1029 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)1030 static inline void kvm_clr_pmu_events(u32 clr) {}
1031 #endif
1032
1033 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1034 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1035
1036 int __init kvm_set_ipa_limit(void);
1037
1038 #define __KVM_HAVE_ARCH_VM_ALLOC
1039 struct kvm *kvm_arch_alloc_vm(void);
1040
kvm_vm_is_protected(struct kvm * kvm)1041 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1042 {
1043 return false;
1044 }
1045
1046 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1047
1048 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1049 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1050
1051 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1052
1053 #define kvm_has_mte(kvm) \
1054 (system_supports_mte() && \
1055 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1056
1057 #define kvm_supports_32bit_el0() \
1058 (system_supports_32bit_el0() && \
1059 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1060
1061 int kvm_trng_call(struct kvm_vcpu *vcpu);
1062 #ifdef CONFIG_KVM
1063 extern phys_addr_t hyp_mem_base;
1064 extern phys_addr_t hyp_mem_size;
1065 void __init kvm_hyp_reserve(void);
1066 #else
kvm_hyp_reserve(void)1067 static inline void kvm_hyp_reserve(void) { }
1068 #endif
1069
1070 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1071 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1072
1073 #endif /* __ARM64_KVM_HOST_H__ */
1074