1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #ifndef __ETNAVIV_GPU_H__
7 #define __ETNAVIV_GPU_H__
8
9 #include "etnaviv_cmdbuf.h"
10 #include "etnaviv_gem.h"
11 #include "etnaviv_mmu.h"
12 #include "etnaviv_drv.h"
13 #include "common.xml.h"
14
15 struct etnaviv_gem_submit;
16 struct etnaviv_vram_mapping;
17
18 struct etnaviv_chip_identity {
19 u32 model;
20 u32 revision;
21 u32 product_id;
22 u32 customer_id;
23 u32 eco_id;
24
25 /* Supported feature fields. */
26 u32 features;
27
28 /* Supported minor feature fields. */
29 u32 minor_features0;
30 u32 minor_features1;
31 u32 minor_features2;
32 u32 minor_features3;
33 u32 minor_features4;
34 u32 minor_features5;
35 u32 minor_features6;
36 u32 minor_features7;
37 u32 minor_features8;
38 u32 minor_features9;
39 u32 minor_features10;
40 u32 minor_features11;
41
42 /* Number of streams supported. */
43 u32 stream_count;
44
45 /* Total number of temporary registers per thread. */
46 u32 register_max;
47
48 /* Maximum number of threads. */
49 u32 thread_count;
50
51 /* Number of shader cores. */
52 u32 shader_core_count;
53
54 /* Number of Neural Network cores. */
55 u32 nn_core_count;
56
57 /* Size of the vertex cache. */
58 u32 vertex_cache_size;
59
60 /* Number of entries in the vertex output buffer. */
61 u32 vertex_output_buffer_size;
62
63 /* Number of pixel pipes. */
64 u32 pixel_pipes;
65
66 /* Number of instructions. */
67 u32 instruction_count;
68
69 /* Number of constants. */
70 u32 num_constants;
71
72 /* Buffer size */
73 u32 buffer_size;
74
75 /* Number of varyings */
76 u8 varyings_count;
77 };
78
79 enum etnaviv_sec_mode {
80 ETNA_SEC_NONE = 0,
81 ETNA_SEC_KERNEL,
82 ETNA_SEC_TZ
83 };
84
85 struct etnaviv_event {
86 struct dma_fence *fence;
87 struct etnaviv_gem_submit *submit;
88
89 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
90 };
91
92 struct etnaviv_cmdbuf_suballoc;
93 struct regulator;
94 struct clk;
95
96 #define ETNA_NR_EVENTS 30
97
98 struct etnaviv_gpu {
99 struct drm_device *drm;
100 struct thermal_cooling_device *cooling;
101 struct device *dev;
102 struct mutex lock;
103 struct etnaviv_chip_identity identity;
104 enum etnaviv_sec_mode sec_mode;
105 struct workqueue_struct *wq;
106 struct mutex sched_lock;
107 struct drm_gpu_scheduler sched;
108 bool initialized;
109 bool fe_running;
110
111 /* 'ring'-buffer: */
112 struct etnaviv_cmdbuf buffer;
113 int exec_state;
114
115 /* event management: */
116 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
117 struct etnaviv_event event[ETNA_NR_EVENTS];
118 struct completion event_free;
119 spinlock_t event_spinlock;
120
121 u32 idle_mask;
122
123 /* Fencing support */
124 struct xarray user_fences;
125 u32 next_user_fence;
126 u32 next_fence;
127 u32 completed_fence;
128 wait_queue_head_t fence_event;
129 u64 fence_context;
130 spinlock_t fence_spinlock;
131
132 /* worker for handling 'sync' points: */
133 struct work_struct sync_point_work;
134 int sync_point_event;
135
136 /* hang detection */
137 u32 hangcheck_dma_addr;
138 u32 hangcheck_fence;
139
140 void __iomem *mmio;
141 int irq;
142
143 struct etnaviv_iommu_context *mmu_context;
144 unsigned int flush_seq;
145
146 /* Power Control: */
147 struct clk *clk_bus;
148 struct clk *clk_reg;
149 struct clk *clk_core;
150 struct clk *clk_shader;
151
152 unsigned int freq_scale;
153 unsigned long base_rate_core;
154 unsigned long base_rate_shader;
155 };
156
gpu_write(struct etnaviv_gpu * gpu,u32 reg,u32 data)157 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
158 {
159 writel(data, gpu->mmio + reg);
160 }
161
gpu_read(struct etnaviv_gpu * gpu,u32 reg)162 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
163 {
164 return readl(gpu->mmio + reg);
165 }
166
gpu_fix_power_address(struct etnaviv_gpu * gpu,u32 reg)167 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg)
168 {
169 /* Power registers in GC300 < 2.0 are offset by 0x100 */
170 if (gpu->identity.model == chipModel_GC300 &&
171 gpu->identity.revision < 0x2000)
172 reg += 0x100;
173
174 return reg;
175 }
176
gpu_write_power(struct etnaviv_gpu * gpu,u32 reg,u32 data)177 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data)
178 {
179 writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
180 }
181
gpu_read_power(struct etnaviv_gpu * gpu,u32 reg)182 static inline u32 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg)
183 {
184 return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
185 }
186
187 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
188
189 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
190 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
191
192 #ifdef CONFIG_DEBUG_FS
193 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
194 #endif
195
196 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit);
197 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
198 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
199 u32 fence, struct drm_etnaviv_timespec *timeout);
200 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
201 struct etnaviv_gem_object *etnaviv_obj,
202 struct drm_etnaviv_timespec *timeout);
203 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
204 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
205 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
206 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
207 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
208
209 extern struct platform_driver etnaviv_gpu_driver;
210
211 #endif /* __ETNAVIV_GPU_H__ */
212