1 /*
2 * Copyright (c) 2015 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/trace.h>
9 #include <lk/debug.h>
10 #include <stdint.h>
11 #include <lk/bits.h>
12 #include <arch.h>
13 #include <arch/mips.h>
14 #include <platform.h>
15
16 #define LOCAL_TRACE 0
17
arch_early_init(void)18 void arch_early_init(void) {
19 LTRACE;
20
21 /* configure the vector table */
22 uint32_t temp = mips_read_c0_status();
23 temp &= ~(1<<22); /* unset BEV, which moves vectors to 0x80000000 */
24 temp &= ~(1<<2); /* clear ERL */
25
26 /* mask all of the irq handlers */
27 temp &= ~(1<<8); // IM0
28 temp &= ~(1<<9); // IM1
29 temp &= ~(1<<10); // IM2
30 temp &= ~(1<<11); // IM3
31 temp &= ~(1<<12); // IM4
32 temp &= ~(1<<13); // IM5
33 temp &= ~(1<<14); // IM6
34 temp &= ~(1<<15); // IM7
35 temp &= ~(1<<16); // IM8
36 temp &= ~(1<<18); // IM9 (note the bit gap)
37
38 mips_write_c0_status(temp);
39
40 /* set ebase */
41 mips_write_c0_ebase(MEMBASE);
42
43 /* make sure we take exceptions in 32bit mips mode */
44 mips_write_c0_config3(mips_read_c0_config3() & ~(1<<16));
45
46 /* set vectored mode */
47 temp = mips_read_c0_intctl();
48 temp &= ~(0b1111 << 5);
49 temp |= 1 << 5; /* 32 byte spacing */
50 STATIC_ASSERT(VECTORED_OFFSET_SHIFT == 32);
51
52 mips_write_c0_intctl(temp);
53
54 temp = mips_read_c0_cause();
55 temp |= (1<<23); /* IV vectored mode */
56 mips_write_c0_cause(temp);
57 }
58
arch_init(void)59 void arch_init(void) {
60 LTRACE;
61
62 printf("MIPS registers:\n");
63 printf("\tPRId 0x%x\n", mips_read_c0_prid());
64 printf("\tconfig 0x%x\n", mips_read_c0_config());
65 printf("\tconfig1 0x%x\n", mips_read_c0_config1());
66 printf("\tconfig2 0x%x\n", mips_read_c0_config2());
67 printf("\tconfig3 0x%x\n", mips_read_c0_config3());
68 printf("\tconfig4 0x%x\n", mips_read_c0_config4());
69 printf("\tconfig5 0x%x\n", mips_read_c0_config5());
70 printf("\tconfig6 0x%x\n", mips_read_c0_config6());
71 printf("\tconfig7 0x%x\n", mips_read_c0_config7());
72 printf("\tstatus 0x%x\n", mips_read_c0_status());
73 uint32_t intctl = mips_read_c0_intctl();
74 printf("\tintctl 0x%x\n", intctl);
75 printf("\t\tIPTI 0x%lx\n", BITS_SHIFT(intctl, 31, 29));
76 printf("\t\tIPPCI 0x%lx\n", BITS_SHIFT(intctl, 28, 26));
77 printf("\t\tIPFDC 0x%lx\n", BITS_SHIFT(intctl, 25, 23));
78 printf("\tsrsctl 0x%x\n", mips_read_c0_srsctl());
79 printf("\tebase 0x%x\n", mips_read_c0_ebase());
80 printf("\tcount 0x%x\n", mips_read_c0_count());
81 printf("\tcompare 0x%x\n", mips_read_c0_compare());
82
83 __asm__ volatile("syscall");
84
85 LTRACE_EXIT;
86 }
87
arch_idle(void)88 void arch_idle(void) {
89 asm volatile("wait");
90 }
91
arch_chain_load(void * entry,ulong arg0,ulong arg1,ulong arg2,ulong arg3)92 void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
93 PANIC_UNIMPLEMENTED;
94 }
95
mips_enable_irq(uint num)96 void mips_enable_irq(uint num) {
97 uint32_t temp = mips_read_c0_status();
98 if (num < 9) {
99 temp |= (1 << (num + 8));
100 } else if (num == 9) {
101 temp |= (1 << 18);
102 }
103 mips_write_c0_status(temp);
104 }
105
mips_disable_irq(uint num)106 void mips_disable_irq(uint num) {
107 uint32_t temp = mips_read_c0_status();
108 if (num < 9) {
109 temp &= ~(1 << (num + 8));
110 } else if (num == 9) {
111 temp &= ~(1 << 18);
112 }
113 mips_write_c0_status(temp);
114 }
115
116 /* unimplemented cache operations */
arch_disable_cache(uint flags)117 void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
arch_enable_cache(uint flags)118 void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
119
arch_clean_cache_range(addr_t start,size_t len)120 void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
arch_clean_invalidate_cache_range(addr_t start,size_t len)121 void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
arch_invalidate_cache_range(addr_t start,size_t len)122 void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
arch_sync_cache_range(addr_t start,size_t len)123 void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
124