1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/mlx5/driver.h>
34 #include <linux/mlx5/eswitch.h>
35 #include "mlx5_core.h"
36 #include "../../mlxfw/mlxfw.h"
37 #include "lib/tout.h"
38
39 enum {
40 MCQS_IDENTIFIER_BOOT_IMG = 0x1,
41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4,
42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5,
43 MCQS_IDENTIFIER_CS_TOKEN = 0x6,
44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7,
45 MCQS_IDENTIFIER_GEARBOX = 0xA,
46 };
47
48 enum {
49 MCQS_UPDATE_STATE_IDLE,
50 MCQS_UPDATE_STATE_IN_PROGRESS,
51 MCQS_UPDATE_STATE_APPLIED,
52 MCQS_UPDATE_STATE_ACTIVE,
53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
54 MCQS_UPDATE_STATE_FAILED,
55 MCQS_UPDATE_STATE_CANCELED,
56 MCQS_UPDATE_STATE_BUSY,
57 };
58
59 enum {
60 MCQI_INFO_TYPE_CAPABILITIES = 0x0,
61 MCQI_INFO_TYPE_VERSION = 0x1,
62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5,
63 };
64
65 enum {
66 MCQI_FW_RUNNING_VERSION = 0,
67 MCQI_FW_STORED_VERSION = 1,
68 };
69
mlx5_query_board_id(struct mlx5_core_dev * dev)70 int mlx5_query_board_id(struct mlx5_core_dev *dev)
71 {
72 u32 *out;
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78 if (!out)
79 return -ENOMEM;
80
81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
83 if (err)
84 goto out;
85
86 memcpy(dev->board_id,
87 MLX5_ADDR_OF(query_adapter_out, out,
88 query_adapter_struct.vsd_contd_psid),
89 MLX5_FLD_SZ_BYTES(query_adapter_out,
90 query_adapter_struct.vsd_contd_psid));
91
92 out:
93 kfree(out);
94 return err;
95 }
96
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)97 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
98 {
99 u32 *out;
100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
102 int err;
103
104 out = kzalloc(outlen, GFP_KERNEL);
105 if (!out)
106 return -ENOMEM;
107
108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
110 if (err)
111 goto out;
112
113 *vendor_id = MLX5_GET(query_adapter_out, out,
114 query_adapter_struct.ieee_vendor_id);
115 out:
116 kfree(out);
117 return err;
118 }
119 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
120
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 {
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126 }
127
mlx5_get_mcam_access_reg_group(struct mlx5_core_dev * dev,enum mlx5_mcam_reg_groups group)128 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
129 enum mlx5_mcam_reg_groups group)
130 {
131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
133 }
134
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)135 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
136 {
137 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
139 MLX5_QCAM_REGS_FIRST_128);
140 }
141
mlx5_query_hca_caps(struct mlx5_core_dev * dev)142 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
143 {
144 int err;
145
146 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
147 if (err)
148 return err;
149
150 if (MLX5_CAP_GEN(dev, port_selection_cap)) {
151 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
152 if (err)
153 return err;
154 }
155
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) {
157 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
158 if (err)
159 return err;
160 }
161
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
163 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
164 if (err)
165 return err;
166 }
167
168 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
169 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
170 if (err)
171 return err;
172 }
173
174 if (MLX5_CAP_GEN(dev, pg)) {
175 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
176 if (err)
177 return err;
178 }
179
180 if (MLX5_CAP_GEN(dev, atomic)) {
181 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
182 if (err)
183 return err;
184 }
185
186 if (MLX5_CAP_GEN(dev, roce)) {
187 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
188 if (err)
189 return err;
190 }
191
192 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
193 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
194 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
195 if (err)
196 return err;
197 }
198
199 if (MLX5_CAP_GEN(dev, vport_group_manager) &&
200 MLX5_ESWITCH_MANAGER(dev)) {
201 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
202 if (err)
203 return err;
204 }
205
206 if (MLX5_ESWITCH_MANAGER(dev)) {
207 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
208 if (err)
209 return err;
210 }
211
212 if (MLX5_CAP_GEN(dev, vector_calc)) {
213 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
214 if (err)
215 return err;
216 }
217
218 if (MLX5_CAP_GEN(dev, qos)) {
219 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
220 if (err)
221 return err;
222 }
223
224 if (MLX5_CAP_GEN(dev, debug))
225 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
226
227 if (MLX5_CAP_GEN(dev, pcam_reg))
228 mlx5_get_pcam_reg(dev);
229
230 if (MLX5_CAP_GEN(dev, mcam_reg)) {
231 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
232 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
233 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
234 }
235
236 if (MLX5_CAP_GEN(dev, qcam_reg))
237 mlx5_get_qcam_reg(dev);
238
239 if (MLX5_CAP_GEN(dev, device_memory)) {
240 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
241 if (err)
242 return err;
243 }
244
245 if (MLX5_CAP_GEN(dev, event_cap)) {
246 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT);
247 if (err)
248 return err;
249 }
250
251 if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) {
252 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
253 if (err)
254 return err;
255 }
256
257 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
258 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
259 err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION);
260 if (err)
261 return err;
262 }
263
264 if (MLX5_CAP_GEN(dev, ipsec_offload)) {
265 err = mlx5_core_get_caps(dev, MLX5_CAP_IPSEC);
266 if (err)
267 return err;
268 }
269
270 if (MLX5_CAP_GEN(dev, crypto)) {
271 err = mlx5_core_get_caps(dev, MLX5_CAP_CRYPTO);
272 if (err)
273 return err;
274 }
275
276 if (MLX5_CAP_GEN(dev, shampo)) {
277 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_SHAMPO);
278 if (err)
279 return err;
280 }
281
282 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
283 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD) {
284 err = mlx5_core_get_caps(dev, MLX5_CAP_MACSEC);
285 if (err)
286 return err;
287 }
288
289 if (MLX5_CAP_GEN(dev, adv_virtualization)) {
290 err = mlx5_core_get_caps(dev, MLX5_CAP_ADV_VIRTUALIZATION);
291 if (err)
292 return err;
293 }
294
295 return 0;
296 }
297
mlx5_cmd_init_hca(struct mlx5_core_dev * dev,uint32_t * sw_owner_id)298 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
299 {
300 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
301 int i;
302
303 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
304
305 if (MLX5_CAP_GEN(dev, sw_owner_id)) {
306 for (i = 0; i < 4; i++)
307 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
308 sw_owner_id[i]);
309 }
310
311 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) &&
312 dev->priv.sw_vhca_id > 0)
313 MLX5_SET(init_hca_in, in, sw_vhca_id, dev->priv.sw_vhca_id);
314
315 return mlx5_cmd_exec_in(dev, init_hca, in);
316 }
317
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)318 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
319 {
320 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
321
322 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
323 return mlx5_cmd_exec_in(dev, teardown_hca, in);
324 }
325
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)326 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
327 {
328 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
329 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
330 int force_state;
331 int ret;
332
333 if (!MLX5_CAP_GEN(dev, force_teardown)) {
334 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
335 return -EOPNOTSUPP;
336 }
337
338 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
339 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
340
341 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
342 if (ret)
343 return ret;
344
345 force_state = MLX5_GET(teardown_hca_out, out, state);
346 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
347 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
348 return -EIO;
349 }
350
351 return 0;
352 }
353
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)354 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
355 {
356 unsigned long end, delay_ms = mlx5_tout_ms(dev, TEARDOWN);
357 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
358 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
359 int state;
360 int ret;
361
362 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
363 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
364 return -EOPNOTSUPP;
365 }
366
367 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
368 MLX5_SET(teardown_hca_in, in, profile,
369 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
370
371 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
372 if (ret)
373 return ret;
374
375 state = MLX5_GET(teardown_hca_out, out, state);
376 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
377 mlx5_core_warn(dev, "teardown with fast mode failed\n");
378 return -EIO;
379 }
380
381 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
382
383 /* Loop until device state turns to disable */
384 end = jiffies + msecs_to_jiffies(delay_ms);
385 do {
386 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
387 break;
388
389 cond_resched();
390 } while (!time_after(jiffies, end));
391
392 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
393 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
394 mlx5_get_nic_state(dev), delay_ms);
395 return -EIO;
396 }
397
398 return 0;
399 }
400
401 enum mlxsw_reg_mcc_instruction {
402 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
403 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
404 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
405 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
406 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
407 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
408 };
409
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)410 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
411 enum mlxsw_reg_mcc_instruction instr,
412 u16 component_index, u32 update_handle,
413 u32 component_size)
414 {
415 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
416 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
417
418 memset(in, 0, sizeof(in));
419
420 MLX5_SET(mcc_reg, in, instruction, instr);
421 MLX5_SET(mcc_reg, in, component_index, component_index);
422 MLX5_SET(mcc_reg, in, update_handle, update_handle);
423 MLX5_SET(mcc_reg, in, component_size, component_size);
424
425 return mlx5_core_access_reg(dev, in, sizeof(in), out,
426 sizeof(out), MLX5_REG_MCC, 0, 1);
427 }
428
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)429 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
430 u32 *update_handle, u8 *error_code,
431 u8 *control_state)
432 {
433 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
434 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
435 int err;
436
437 memset(in, 0, sizeof(in));
438 memset(out, 0, sizeof(out));
439 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
440
441 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
442 sizeof(out), MLX5_REG_MCC, 0, 0);
443 if (err)
444 goto out;
445
446 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
447 *error_code = MLX5_GET(mcc_reg, out, error_code);
448 *control_state = MLX5_GET(mcc_reg, out, control_state);
449
450 out:
451 return err;
452 }
453
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)454 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
455 u32 update_handle,
456 u32 offset, u16 size,
457 u8 *data)
458 {
459 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
460 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
461 int i, j, dw_size = size >> 2;
462 __be32 data_element;
463 u32 *in;
464
465 in = kzalloc(in_size, GFP_KERNEL);
466 if (!in)
467 return -ENOMEM;
468
469 MLX5_SET(mcda_reg, in, update_handle, update_handle);
470 MLX5_SET(mcda_reg, in, offset, offset);
471 MLX5_SET(mcda_reg, in, size, size);
472
473 for (i = 0; i < dw_size; i++) {
474 j = i * 4;
475 data_element = htonl(*(u32 *)&data[j]);
476 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
477 }
478
479 err = mlx5_core_access_reg(dev, in, in_size, out,
480 sizeof(out), MLX5_REG_MCDA, 0, 1);
481 kfree(in);
482 return err;
483 }
484
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u8 info_type,u16 data_size,void * mcqi_data)485 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
486 u16 component_index, bool read_pending,
487 u8 info_type, u16 data_size, void *mcqi_data)
488 {
489 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
490 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
491 void *data;
492 int err;
493
494 MLX5_SET(mcqi_reg, in, component_index, component_index);
495 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
496 MLX5_SET(mcqi_reg, in, info_type, info_type);
497 MLX5_SET(mcqi_reg, in, data_size, data_size);
498
499 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
500 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
501 MLX5_REG_MCQI, 0, 0);
502 if (err)
503 return err;
504
505 data = MLX5_ADDR_OF(mcqi_reg, out, data);
506 memcpy(mcqi_data, data, data_size);
507
508 return 0;
509 }
510
mlx5_reg_mcqi_caps_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)511 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
512 u32 *max_component_size, u8 *log_mcda_word_size,
513 u16 *mcda_max_write_size)
514 {
515 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
516 int err;
517
518 err = mlx5_reg_mcqi_query(dev, component_index, 0,
519 MCQI_INFO_TYPE_CAPABILITIES,
520 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
521 if (err)
522 return err;
523
524 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
525 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
526 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
527
528 return 0;
529 }
530
531 struct mlx5_mlxfw_dev {
532 struct mlxfw_dev mlxfw_dev;
533 struct mlx5_core_dev *mlx5_core_dev;
534 };
535
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)536 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
537 u16 component_index, u32 *p_max_size,
538 u8 *p_align_bits, u16 *p_max_write_size)
539 {
540 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
541 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
542 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
543
544 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
545 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
546 return -EOPNOTSUPP;
547 }
548
549 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
550 p_align_bits, p_max_write_size);
551 }
552
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)553 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
554 {
555 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
556 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
557 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
558 u8 control_state, error_code;
559 int err;
560
561 *fwhandle = 0;
562 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
563 if (err)
564 return err;
565
566 if (control_state != MLXFW_FSM_STATE_IDLE)
567 return -EBUSY;
568
569 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
570 0, *fwhandle, 0);
571 }
572
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)573 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
574 u16 component_index, u32 component_size)
575 {
576 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
577 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
578 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
579
580 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
581 component_index, fwhandle, component_size);
582 }
583
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)584 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
585 u8 *data, u16 size, u32 offset)
586 {
587 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
588 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
589 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
590
591 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
592 }
593
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)594 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
595 u16 component_index)
596 {
597 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
598 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
599 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
600
601 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
602 component_index, fwhandle, 0);
603 }
604
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)605 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
606 {
607 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
608 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
609 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
610
611 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
612 fwhandle, 0);
613 }
614
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)615 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
616 enum mlxfw_fsm_state *fsm_state,
617 enum mlxfw_fsm_state_err *fsm_state_err)
618 {
619 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
620 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
621 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
622 u8 control_state, error_code;
623 int err;
624
625 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
626 if (err)
627 return err;
628
629 *fsm_state = control_state;
630 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
631 MLXFW_FSM_STATE_ERR_MAX);
632 return 0;
633 }
634
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)635 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
636 {
637 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
638 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
639 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
640
641 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
642 }
643
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)644 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
645 {
646 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
647 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
648 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
649
650 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
651 fwhandle, 0);
652 }
653
mlx5_fsm_reactivate(struct mlxfw_dev * mlxfw_dev,u8 * status)654 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
655 {
656 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
657 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
658 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
659 u32 out[MLX5_ST_SZ_DW(mirc_reg)];
660 u32 in[MLX5_ST_SZ_DW(mirc_reg)];
661 unsigned long exp_time;
662 int err;
663
664 exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FSM_REACTIVATE));
665
666 if (!MLX5_CAP_MCAM_REG2(dev, mirc))
667 return -EOPNOTSUPP;
668
669 memset(in, 0, sizeof(in));
670
671 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
672 sizeof(out), MLX5_REG_MIRC, 0, 1);
673 if (err)
674 return err;
675
676 do {
677 memset(out, 0, sizeof(out));
678 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
679 sizeof(out), MLX5_REG_MIRC, 0, 0);
680 if (err)
681 return err;
682
683 *status = MLX5_GET(mirc_reg, out, status_code);
684 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
685 return 0;
686
687 msleep(20);
688 } while (time_before(jiffies, exp_time));
689
690 return 0;
691 }
692
693 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
694 .component_query = mlx5_component_query,
695 .fsm_lock = mlx5_fsm_lock,
696 .fsm_component_update = mlx5_fsm_component_update,
697 .fsm_block_download = mlx5_fsm_block_download,
698 .fsm_component_verify = mlx5_fsm_component_verify,
699 .fsm_activate = mlx5_fsm_activate,
700 .fsm_reactivate = mlx5_fsm_reactivate,
701 .fsm_query_state = mlx5_fsm_query_state,
702 .fsm_cancel = mlx5_fsm_cancel,
703 .fsm_release = mlx5_fsm_release
704 };
705
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware,struct netlink_ext_ack * extack)706 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
707 const struct firmware *firmware,
708 struct netlink_ext_ack *extack)
709 {
710 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
711 .mlxfw_dev = {
712 .ops = &mlx5_mlxfw_dev_ops,
713 .psid = dev->board_id,
714 .psid_size = strlen(dev->board_id),
715 .devlink = priv_to_devlink(dev),
716 },
717 .mlx5_core_dev = dev
718 };
719
720 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
721 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
722 !MLX5_CAP_MCAM_REG(dev, mcc) ||
723 !MLX5_CAP_MCAM_REG(dev, mcda)) {
724 pr_info("%s flashing isn't supported by the running FW\n", __func__);
725 return -EOPNOTSUPP;
726 }
727
728 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
729 firmware, extack);
730 }
731
mlx5_reg_mcqi_version_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u32 * mcqi_version_out)732 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
733 u16 component_index, bool read_pending,
734 u32 *mcqi_version_out)
735 {
736 return mlx5_reg_mcqi_query(dev, component_index, read_pending,
737 MCQI_INFO_TYPE_VERSION,
738 MLX5_ST_SZ_BYTES(mcqi_version),
739 mcqi_version_out);
740 }
741
mlx5_reg_mcqs_query(struct mlx5_core_dev * dev,u32 * out,u16 component_index)742 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
743 u16 component_index)
744 {
745 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
746 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
747 int err;
748
749 memset(out, 0, out_sz);
750
751 MLX5_SET(mcqs_reg, in, component_index, component_index);
752
753 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
754 out_sz, MLX5_REG_MCQS, 0, 0);
755 return err;
756 }
757
758 /* scans component index sequentially, to find the boot img index */
mlx5_get_boot_img_component_index(struct mlx5_core_dev * dev)759 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
760 {
761 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
762 u16 identifier, component_idx = 0;
763 bool quit;
764 int err;
765
766 do {
767 err = mlx5_reg_mcqs_query(dev, out, component_idx);
768 if (err)
769 return err;
770
771 identifier = MLX5_GET(mcqs_reg, out, identifier);
772 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
773 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
774 } while (!quit && ++component_idx);
775
776 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
777 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
778 component_idx);
779 return -EOPNOTSUPP;
780 }
781
782 return component_idx;
783 }
784
785 static int
mlx5_fw_image_pending(struct mlx5_core_dev * dev,int component_index,bool * pending_version_exists)786 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
787 int component_index,
788 bool *pending_version_exists)
789 {
790 u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
791 u8 component_update_state;
792 int err;
793
794 err = mlx5_reg_mcqs_query(dev, out, component_index);
795 if (err)
796 return err;
797
798 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
799
800 if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
801 *pending_version_exists = false;
802 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
803 *pending_version_exists = true;
804 } else {
805 mlx5_core_warn(dev,
806 "mcqs: can't read pending fw version while fw state is %d\n",
807 component_update_state);
808 return -ENODATA;
809 }
810 return 0;
811 }
812
mlx5_fw_version_query(struct mlx5_core_dev * dev,u32 * running_ver,u32 * pending_ver)813 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
814 u32 *running_ver, u32 *pending_ver)
815 {
816 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
817 bool pending_version_exists;
818 int component_index;
819 int err;
820
821 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
822 !MLX5_CAP_MCAM_REG(dev, mcqs)) {
823 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
824 return -EOPNOTSUPP;
825 }
826
827 component_index = mlx5_get_boot_img_component_index(dev);
828 if (component_index < 0)
829 return component_index;
830
831 err = mlx5_reg_mcqi_version_query(dev, component_index,
832 MCQI_FW_RUNNING_VERSION,
833 reg_mcqi_version);
834 if (err)
835 return err;
836
837 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
838
839 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
840 if (err)
841 return err;
842
843 if (!pending_version_exists) {
844 *pending_ver = 0;
845 return 0;
846 }
847
848 err = mlx5_reg_mcqi_version_query(dev, component_index,
849 MCQI_FW_STORED_VERSION,
850 reg_mcqi_version);
851 if (err)
852 return err;
853
854 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
855
856 return 0;
857 }
858