1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3  * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4  */
5 
6 #include <linux/gfp.h>
7 #include <linux/mlx5/qp.h>
8 #include <linux/mlx5/driver.h>
9 #include "mlx5_ib.h"
10 #include "qp.h"
11 
12 static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
13 			       struct mlx5_core_dct *dct);
14 
15 static struct mlx5_core_rsc_common *
mlx5_get_rsc(struct mlx5_qp_table * table,u32 rsn)16 mlx5_get_rsc(struct mlx5_qp_table *table, u32 rsn)
17 {
18 	struct mlx5_core_rsc_common *common;
19 	unsigned long flags;
20 
21 	spin_lock_irqsave(&table->lock, flags);
22 
23 	common = radix_tree_lookup(&table->tree, rsn);
24 	if (common)
25 		refcount_inc(&common->refcount);
26 
27 	spin_unlock_irqrestore(&table->lock, flags);
28 
29 	return common;
30 }
31 
mlx5_core_put_rsc(struct mlx5_core_rsc_common * common)32 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
33 {
34 	if (refcount_dec_and_test(&common->refcount))
35 		complete(&common->free);
36 }
37 
qp_allowed_event_types(void)38 static u64 qp_allowed_event_types(void)
39 {
40 	u64 mask;
41 
42 	mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) |
43 	       BIT(MLX5_EVENT_TYPE_COMM_EST) |
44 	       BIT(MLX5_EVENT_TYPE_SQ_DRAINED) |
45 	       BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
46 	       BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR) |
47 	       BIT(MLX5_EVENT_TYPE_PATH_MIG_FAILED) |
48 	       BIT(MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) |
49 	       BIT(MLX5_EVENT_TYPE_WQ_ACCESS_ERROR);
50 
51 	return mask;
52 }
53 
rq_allowed_event_types(void)54 static u64 rq_allowed_event_types(void)
55 {
56 	u64 mask;
57 
58 	mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
59 	       BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
60 
61 	return mask;
62 }
63 
sq_allowed_event_types(void)64 static u64 sq_allowed_event_types(void)
65 {
66 	return BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
67 }
68 
dct_allowed_event_types(void)69 static u64 dct_allowed_event_types(void)
70 {
71 	return BIT(MLX5_EVENT_TYPE_DCT_DRAINED);
72 }
73 
is_event_type_allowed(int rsc_type,int event_type)74 static bool is_event_type_allowed(int rsc_type, int event_type)
75 {
76 	switch (rsc_type) {
77 	case MLX5_EVENT_QUEUE_TYPE_QP:
78 		return BIT(event_type) & qp_allowed_event_types();
79 	case MLX5_EVENT_QUEUE_TYPE_RQ:
80 		return BIT(event_type) & rq_allowed_event_types();
81 	case MLX5_EVENT_QUEUE_TYPE_SQ:
82 		return BIT(event_type) & sq_allowed_event_types();
83 	case MLX5_EVENT_QUEUE_TYPE_DCT:
84 		return BIT(event_type) & dct_allowed_event_types();
85 	default:
86 		WARN(1, "Event arrived for unknown resource type");
87 		return false;
88 	}
89 }
90 
rsc_event_notifier(struct notifier_block * nb,unsigned long type,void * data)91 static int rsc_event_notifier(struct notifier_block *nb,
92 			      unsigned long type, void *data)
93 {
94 	struct mlx5_core_rsc_common *common;
95 	struct mlx5_qp_table *table;
96 	struct mlx5_core_dct *dct;
97 	u8 event_type = (u8)type;
98 	struct mlx5_core_qp *qp;
99 	struct mlx5_eqe *eqe;
100 	u32 rsn;
101 
102 	switch (event_type) {
103 	case MLX5_EVENT_TYPE_DCT_DRAINED:
104 		eqe = data;
105 		rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
106 		rsn |= (MLX5_RES_DCT << MLX5_USER_INDEX_LEN);
107 		break;
108 	case MLX5_EVENT_TYPE_PATH_MIG:
109 	case MLX5_EVENT_TYPE_COMM_EST:
110 	case MLX5_EVENT_TYPE_SQ_DRAINED:
111 	case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
112 	case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
113 	case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
114 	case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
115 	case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
116 		eqe = data;
117 		rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
118 		rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
119 		break;
120 	default:
121 		return NOTIFY_DONE;
122 	}
123 
124 	table = container_of(nb, struct mlx5_qp_table, nb);
125 	common = mlx5_get_rsc(table, rsn);
126 	if (!common)
127 		return NOTIFY_OK;
128 
129 	if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type))
130 		goto out;
131 
132 	switch (common->res) {
133 	case MLX5_RES_QP:
134 	case MLX5_RES_RQ:
135 	case MLX5_RES_SQ:
136 		qp = (struct mlx5_core_qp *)common;
137 		qp->event(qp, event_type);
138 		/* Need to put resource in event handler */
139 		return NOTIFY_OK;
140 	case MLX5_RES_DCT:
141 		dct = (struct mlx5_core_dct *)common;
142 		if (event_type == MLX5_EVENT_TYPE_DCT_DRAINED)
143 			complete(&dct->drained);
144 		break;
145 	default:
146 		break;
147 	}
148 out:
149 	mlx5_core_put_rsc(common);
150 
151 	return NOTIFY_OK;
152 }
153 
create_resource_common(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,int rsc_type)154 static int create_resource_common(struct mlx5_ib_dev *dev,
155 				  struct mlx5_core_qp *qp, int rsc_type)
156 {
157 	struct mlx5_qp_table *table = &dev->qp_table;
158 	int err;
159 
160 	qp->common.res = rsc_type;
161 	spin_lock_irq(&table->lock);
162 	err = radix_tree_insert(&table->tree,
163 				qp->qpn | (rsc_type << MLX5_USER_INDEX_LEN),
164 				qp);
165 	spin_unlock_irq(&table->lock);
166 	if (err)
167 		return err;
168 
169 	refcount_set(&qp->common.refcount, 1);
170 	init_completion(&qp->common.free);
171 	qp->pid = current->pid;
172 
173 	return 0;
174 }
175 
destroy_resource_common(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp)176 static void destroy_resource_common(struct mlx5_ib_dev *dev,
177 				    struct mlx5_core_qp *qp)
178 {
179 	struct mlx5_qp_table *table = &dev->qp_table;
180 	unsigned long flags;
181 
182 	spin_lock_irqsave(&table->lock, flags);
183 	radix_tree_delete(&table->tree,
184 			  qp->qpn | (qp->common.res << MLX5_USER_INDEX_LEN));
185 	spin_unlock_irqrestore(&table->lock, flags);
186 	mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
187 	wait_for_completion(&qp->common.free);
188 }
189 
_mlx5_core_destroy_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct,bool need_cleanup)190 static int _mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
191 				  struct mlx5_core_dct *dct, bool need_cleanup)
192 {
193 	u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {};
194 	struct mlx5_core_qp *qp = &dct->mqp;
195 	int err;
196 
197 	err = mlx5_core_drain_dct(dev, dct);
198 	if (err) {
199 		if (dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
200 			goto destroy;
201 
202 		return err;
203 	}
204 	wait_for_completion(&dct->drained);
205 destroy:
206 	if (need_cleanup)
207 		destroy_resource_common(dev, &dct->mqp);
208 	MLX5_SET(destroy_dct_in, in, opcode, MLX5_CMD_OP_DESTROY_DCT);
209 	MLX5_SET(destroy_dct_in, in, dctn, qp->qpn);
210 	MLX5_SET(destroy_dct_in, in, uid, qp->uid);
211 	err = mlx5_cmd_exec_in(dev->mdev, destroy_dct, in);
212 	return err;
213 }
214 
mlx5_core_create_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct,u32 * in,int inlen,u32 * out,int outlen)215 int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
216 			 u32 *in, int inlen, u32 *out, int outlen)
217 {
218 	struct mlx5_core_qp *qp = &dct->mqp;
219 	int err;
220 
221 	init_completion(&dct->drained);
222 	MLX5_SET(create_dct_in, in, opcode, MLX5_CMD_OP_CREATE_DCT);
223 
224 	err = mlx5_cmd_do(dev->mdev, in, inlen, out, outlen);
225 	if (err)
226 		return err;
227 
228 	qp->qpn = MLX5_GET(create_dct_out, out, dctn);
229 	qp->uid = MLX5_GET(create_dct_in, in, uid);
230 	err = create_resource_common(dev, qp, MLX5_RES_DCT);
231 	if (err)
232 		goto err_cmd;
233 
234 	return 0;
235 err_cmd:
236 	_mlx5_core_destroy_dct(dev, dct, false);
237 	return err;
238 }
239 
mlx5_qpc_create_qp(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,u32 * in,int inlen,u32 * out)240 int mlx5_qpc_create_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
241 		       u32 *in, int inlen, u32 *out)
242 {
243 	u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
244 	int err;
245 
246 	MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
247 
248 	err = mlx5_cmd_exec(dev->mdev, in, inlen, out,
249 			    MLX5_ST_SZ_BYTES(create_qp_out));
250 	if (err)
251 		return err;
252 
253 	qp->uid = MLX5_GET(create_qp_in, in, uid);
254 	qp->qpn = MLX5_GET(create_qp_out, out, qpn);
255 
256 	err = create_resource_common(dev, qp, MLX5_RES_QP);
257 	if (err)
258 		goto err_cmd;
259 
260 	mlx5_debug_qp_add(dev->mdev, qp);
261 
262 	return 0;
263 
264 err_cmd:
265 	MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP);
266 	MLX5_SET(destroy_qp_in, din, qpn, qp->qpn);
267 	MLX5_SET(destroy_qp_in, din, uid, qp->uid);
268 	mlx5_cmd_exec_in(dev->mdev, destroy_qp, din);
269 	return err;
270 }
271 
mlx5_core_drain_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct)272 static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
273 			       struct mlx5_core_dct *dct)
274 {
275 	u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {};
276 	struct mlx5_core_qp *qp = &dct->mqp;
277 
278 	MLX5_SET(drain_dct_in, in, opcode, MLX5_CMD_OP_DRAIN_DCT);
279 	MLX5_SET(drain_dct_in, in, dctn, qp->qpn);
280 	MLX5_SET(drain_dct_in, in, uid, qp->uid);
281 	return mlx5_cmd_exec_in(dev->mdev, drain_dct, in);
282 }
283 
mlx5_core_destroy_dct(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct)284 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
285 			  struct mlx5_core_dct *dct)
286 {
287 	return _mlx5_core_destroy_dct(dev, dct, true);
288 }
289 
mlx5_core_destroy_qp(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp)290 int mlx5_core_destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp)
291 {
292 	u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
293 
294 	mlx5_debug_qp_remove(dev->mdev, qp);
295 
296 	destroy_resource_common(dev, qp);
297 
298 	MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
299 	MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
300 	MLX5_SET(destroy_qp_in, in, uid, qp->uid);
301 	mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
302 	return 0;
303 }
304 
mlx5_core_set_delay_drop(struct mlx5_ib_dev * dev,u32 timeout_usec)305 int mlx5_core_set_delay_drop(struct mlx5_ib_dev *dev,
306 			     u32 timeout_usec)
307 {
308 	u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {};
309 
310 	MLX5_SET(set_delay_drop_params_in, in, opcode,
311 		 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS);
312 	MLX5_SET(set_delay_drop_params_in, in, delay_drop_timeout,
313 		 timeout_usec / 100);
314 	return mlx5_cmd_exec_in(dev->mdev, set_delay_drop_params, in);
315 }
316 
317 struct mbox_info {
318 	u32 *in;
319 	u32 *out;
320 	int inlen;
321 	int outlen;
322 };
323 
mbox_alloc(struct mbox_info * mbox,int inlen,int outlen)324 static int mbox_alloc(struct mbox_info *mbox, int inlen, int outlen)
325 {
326 	mbox->inlen  = inlen;
327 	mbox->outlen = outlen;
328 	mbox->in = kzalloc(mbox->inlen, GFP_KERNEL);
329 	mbox->out = kzalloc(mbox->outlen, GFP_KERNEL);
330 	if (!mbox->in || !mbox->out) {
331 		kfree(mbox->in);
332 		kfree(mbox->out);
333 		return -ENOMEM;
334 	}
335 
336 	return 0;
337 }
338 
mbox_free(struct mbox_info * mbox)339 static void mbox_free(struct mbox_info *mbox)
340 {
341 	kfree(mbox->in);
342 	kfree(mbox->out);
343 }
344 
get_ece_from_mbox(void * out,u16 opcode)345 static int get_ece_from_mbox(void *out, u16 opcode)
346 {
347 	int ece = 0;
348 
349 	switch (opcode) {
350 	case MLX5_CMD_OP_INIT2INIT_QP:
351 		ece = MLX5_GET(init2init_qp_out, out, ece);
352 		break;
353 	case MLX5_CMD_OP_INIT2RTR_QP:
354 		ece = MLX5_GET(init2rtr_qp_out, out, ece);
355 		break;
356 	case MLX5_CMD_OP_RTR2RTS_QP:
357 		ece = MLX5_GET(rtr2rts_qp_out, out, ece);
358 		break;
359 	case MLX5_CMD_OP_RTS2RTS_QP:
360 		ece = MLX5_GET(rts2rts_qp_out, out, ece);
361 		break;
362 	case MLX5_CMD_OP_RST2INIT_QP:
363 		ece = MLX5_GET(rst2init_qp_out, out, ece);
364 		break;
365 	default:
366 		break;
367 	}
368 
369 	return ece;
370 }
371 
modify_qp_mbox_alloc(struct mlx5_core_dev * dev,u16 opcode,int qpn,u32 opt_param_mask,void * qpc,struct mbox_info * mbox,u16 uid,u32 ece)372 static int modify_qp_mbox_alloc(struct mlx5_core_dev *dev, u16 opcode, int qpn,
373 				u32 opt_param_mask, void *qpc,
374 				struct mbox_info *mbox, u16 uid, u32 ece)
375 {
376 	mbox->out = NULL;
377 	mbox->in = NULL;
378 
379 #define MBOX_ALLOC(mbox, typ)  \
380 	mbox_alloc(mbox, MLX5_ST_SZ_BYTES(typ##_in), MLX5_ST_SZ_BYTES(typ##_out))
381 
382 #define MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid)                            \
383 	do {                                                                   \
384 		MLX5_SET(typ##_in, in, opcode, _opcode);                       \
385 		MLX5_SET(typ##_in, in, qpn, _qpn);                             \
386 		MLX5_SET(typ##_in, in, uid, _uid);                             \
387 	} while (0)
388 
389 #define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc, _uid)          \
390 	do {                                                                   \
391 		MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid);                   \
392 		MLX5_SET(typ##_in, in, opt_param_mask, _opt_p);                \
393 		memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc,                  \
394 		       MLX5_ST_SZ_BYTES(qpc));                                 \
395 	} while (0)
396 
397 	switch (opcode) {
398 	/* 2RST & 2ERR */
399 	case MLX5_CMD_OP_2RST_QP:
400 		if (MBOX_ALLOC(mbox, qp_2rst))
401 			return -ENOMEM;
402 		MOD_QP_IN_SET(qp_2rst, mbox->in, opcode, qpn, uid);
403 		break;
404 	case MLX5_CMD_OP_2ERR_QP:
405 		if (MBOX_ALLOC(mbox, qp_2err))
406 			return -ENOMEM;
407 		MOD_QP_IN_SET(qp_2err, mbox->in, opcode, qpn, uid);
408 		break;
409 
410 	/* MODIFY with QPC */
411 	case MLX5_CMD_OP_RST2INIT_QP:
412 		if (MBOX_ALLOC(mbox, rst2init_qp))
413 			return -ENOMEM;
414 		MOD_QP_IN_SET_QPC(rst2init_qp, mbox->in, opcode, qpn,
415 				  opt_param_mask, qpc, uid);
416 		MLX5_SET(rst2init_qp_in, mbox->in, ece, ece);
417 		break;
418 	case MLX5_CMD_OP_INIT2RTR_QP:
419 		if (MBOX_ALLOC(mbox, init2rtr_qp))
420 			return -ENOMEM;
421 		MOD_QP_IN_SET_QPC(init2rtr_qp, mbox->in, opcode, qpn,
422 				  opt_param_mask, qpc, uid);
423 		MLX5_SET(init2rtr_qp_in, mbox->in, ece, ece);
424 		break;
425 	case MLX5_CMD_OP_RTR2RTS_QP:
426 		if (MBOX_ALLOC(mbox, rtr2rts_qp))
427 			return -ENOMEM;
428 		MOD_QP_IN_SET_QPC(rtr2rts_qp, mbox->in, opcode, qpn,
429 				  opt_param_mask, qpc, uid);
430 		MLX5_SET(rtr2rts_qp_in, mbox->in, ece, ece);
431 		break;
432 	case MLX5_CMD_OP_RTS2RTS_QP:
433 		if (MBOX_ALLOC(mbox, rts2rts_qp))
434 			return -ENOMEM;
435 		MOD_QP_IN_SET_QPC(rts2rts_qp, mbox->in, opcode, qpn,
436 				  opt_param_mask, qpc, uid);
437 		MLX5_SET(rts2rts_qp_in, mbox->in, ece, ece);
438 		break;
439 	case MLX5_CMD_OP_SQERR2RTS_QP:
440 		if (MBOX_ALLOC(mbox, sqerr2rts_qp))
441 			return -ENOMEM;
442 		MOD_QP_IN_SET_QPC(sqerr2rts_qp, mbox->in, opcode, qpn,
443 				  opt_param_mask, qpc, uid);
444 		break;
445 	case MLX5_CMD_OP_SQD_RTS_QP:
446 		if (MBOX_ALLOC(mbox, sqd2rts_qp))
447 			return -ENOMEM;
448 		MOD_QP_IN_SET_QPC(sqd2rts_qp, mbox->in, opcode, qpn,
449 				  opt_param_mask, qpc, uid);
450 		break;
451 	case MLX5_CMD_OP_INIT2INIT_QP:
452 		if (MBOX_ALLOC(mbox, init2init_qp))
453 			return -ENOMEM;
454 		MOD_QP_IN_SET_QPC(init2init_qp, mbox->in, opcode, qpn,
455 				  opt_param_mask, qpc, uid);
456 		MLX5_SET(init2init_qp_in, mbox->in, ece, ece);
457 		break;
458 	default:
459 		return -EINVAL;
460 	}
461 	return 0;
462 }
463 
mlx5_core_qp_modify(struct mlx5_ib_dev * dev,u16 opcode,u32 opt_param_mask,void * qpc,struct mlx5_core_qp * qp,u32 * ece)464 int mlx5_core_qp_modify(struct mlx5_ib_dev *dev, u16 opcode, u32 opt_param_mask,
465 			void *qpc, struct mlx5_core_qp *qp, u32 *ece)
466 {
467 	struct mbox_info mbox;
468 	int err;
469 
470 	err = modify_qp_mbox_alloc(dev->mdev, opcode, qp->qpn, opt_param_mask,
471 				   qpc, &mbox, qp->uid, (ece) ? *ece : 0);
472 	if (err)
473 		return err;
474 
475 	err = mlx5_cmd_exec(dev->mdev, mbox.in, mbox.inlen, mbox.out,
476 			    mbox.outlen);
477 
478 	if (ece)
479 		*ece = get_ece_from_mbox(mbox.out, opcode);
480 
481 	mbox_free(&mbox);
482 	return err;
483 }
484 
mlx5_init_qp_table(struct mlx5_ib_dev * dev)485 int mlx5_init_qp_table(struct mlx5_ib_dev *dev)
486 {
487 	struct mlx5_qp_table *table = &dev->qp_table;
488 
489 	spin_lock_init(&table->lock);
490 	INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
491 	mlx5_qp_debugfs_init(dev->mdev);
492 
493 	table->nb.notifier_call = rsc_event_notifier;
494 	mlx5_notifier_register(dev->mdev, &table->nb);
495 
496 	return 0;
497 }
498 
mlx5_cleanup_qp_table(struct mlx5_ib_dev * dev)499 void mlx5_cleanup_qp_table(struct mlx5_ib_dev *dev)
500 {
501 	struct mlx5_qp_table *table = &dev->qp_table;
502 
503 	mlx5_notifier_unregister(dev->mdev, &table->nb);
504 	mlx5_qp_debugfs_cleanup(dev->mdev);
505 }
506 
mlx5_core_qp_query(struct mlx5_ib_dev * dev,struct mlx5_core_qp * qp,u32 * out,int outlen,bool qpc_ext)507 int mlx5_core_qp_query(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
508 		       u32 *out, int outlen, bool qpc_ext)
509 {
510 	u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {};
511 
512 	MLX5_SET(query_qp_in, in, opcode, MLX5_CMD_OP_QUERY_QP);
513 	MLX5_SET(query_qp_in, in, qpn, qp->qpn);
514 	MLX5_SET(query_qp_in, in, qpc_ext, qpc_ext);
515 
516 	return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, outlen);
517 }
518 
mlx5_core_dct_query(struct mlx5_ib_dev * dev,struct mlx5_core_dct * dct,u32 * out,int outlen)519 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
520 			u32 *out, int outlen)
521 {
522 	u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {};
523 	struct mlx5_core_qp *qp = &dct->mqp;
524 
525 	MLX5_SET(query_dct_in, in, opcode, MLX5_CMD_OP_QUERY_DCT);
526 	MLX5_SET(query_dct_in, in, dctn, qp->qpn);
527 
528 	return mlx5_cmd_exec(dev->mdev, (void *)&in, sizeof(in), (void *)out,
529 			     outlen);
530 }
531 
mlx5_core_xrcd_alloc(struct mlx5_ib_dev * dev,u32 * xrcdn)532 int mlx5_core_xrcd_alloc(struct mlx5_ib_dev *dev, u32 *xrcdn)
533 {
534 	u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {};
535 	u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {};
536 	int err;
537 
538 	MLX5_SET(alloc_xrcd_in, in, opcode, MLX5_CMD_OP_ALLOC_XRCD);
539 	err = mlx5_cmd_exec_inout(dev->mdev, alloc_xrcd, in, out);
540 	if (!err)
541 		*xrcdn = MLX5_GET(alloc_xrcd_out, out, xrcd);
542 	return err;
543 }
544 
mlx5_core_xrcd_dealloc(struct mlx5_ib_dev * dev,u32 xrcdn)545 int mlx5_core_xrcd_dealloc(struct mlx5_ib_dev *dev, u32 xrcdn)
546 {
547 	u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {};
548 
549 	MLX5_SET(dealloc_xrcd_in, in, opcode, MLX5_CMD_OP_DEALLOC_XRCD);
550 	MLX5_SET(dealloc_xrcd_in, in, xrcd, xrcdn);
551 	return mlx5_cmd_exec_in(dev->mdev, dealloc_xrcd, in);
552 }
553 
destroy_rq_tracked(struct mlx5_ib_dev * dev,u32 rqn,u16 uid)554 static void destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
555 {
556 	u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
557 
558 	MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
559 	MLX5_SET(destroy_rq_in, in, rqn, rqn);
560 	MLX5_SET(destroy_rq_in, in, uid, uid);
561 	mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
562 }
563 
mlx5_core_create_rq_tracked(struct mlx5_ib_dev * dev,u32 * in,int inlen,struct mlx5_core_qp * rq)564 int mlx5_core_create_rq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
565 				struct mlx5_core_qp *rq)
566 {
567 	int err;
568 	u32 rqn;
569 
570 	err = mlx5_core_create_rq(dev->mdev, in, inlen, &rqn);
571 	if (err)
572 		return err;
573 
574 	rq->uid = MLX5_GET(create_rq_in, in, uid);
575 	rq->qpn = rqn;
576 	err = create_resource_common(dev, rq, MLX5_RES_RQ);
577 	if (err)
578 		goto err_destroy_rq;
579 
580 	return 0;
581 
582 err_destroy_rq:
583 	destroy_rq_tracked(dev, rq->qpn, rq->uid);
584 
585 	return err;
586 }
587 
mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev * dev,struct mlx5_core_qp * rq)588 int mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev *dev,
589 				 struct mlx5_core_qp *rq)
590 {
591 	destroy_resource_common(dev, rq);
592 	destroy_rq_tracked(dev, rq->qpn, rq->uid);
593 	return 0;
594 }
595 
destroy_sq_tracked(struct mlx5_ib_dev * dev,u32 sqn,u16 uid)596 static void destroy_sq_tracked(struct mlx5_ib_dev *dev, u32 sqn, u16 uid)
597 {
598 	u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {};
599 
600 	MLX5_SET(destroy_sq_in, in, opcode, MLX5_CMD_OP_DESTROY_SQ);
601 	MLX5_SET(destroy_sq_in, in, sqn, sqn);
602 	MLX5_SET(destroy_sq_in, in, uid, uid);
603 	mlx5_cmd_exec_in(dev->mdev, destroy_sq, in);
604 }
605 
mlx5_core_create_sq_tracked(struct mlx5_ib_dev * dev,u32 * in,int inlen,struct mlx5_core_qp * sq)606 int mlx5_core_create_sq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
607 				struct mlx5_core_qp *sq)
608 {
609 	u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {};
610 	int err;
611 
612 	MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
613 	err = mlx5_cmd_exec(dev->mdev, in, inlen, out, sizeof(out));
614 	if (err)
615 		return err;
616 
617 	sq->qpn = MLX5_GET(create_sq_out, out, sqn);
618 	sq->uid = MLX5_GET(create_sq_in, in, uid);
619 	err = create_resource_common(dev, sq, MLX5_RES_SQ);
620 	if (err)
621 		goto err_destroy_sq;
622 
623 	return 0;
624 
625 err_destroy_sq:
626 	destroy_sq_tracked(dev, sq->qpn, sq->uid);
627 
628 	return err;
629 }
630 
mlx5_core_destroy_sq_tracked(struct mlx5_ib_dev * dev,struct mlx5_core_qp * sq)631 void mlx5_core_destroy_sq_tracked(struct mlx5_ib_dev *dev,
632 				  struct mlx5_core_qp *sq)
633 {
634 	destroy_resource_common(dev, sq);
635 	destroy_sq_tracked(dev, sq->qpn, sq->uid);
636 }
637 
mlx5_core_res_hold(struct mlx5_ib_dev * dev,int res_num,enum mlx5_res_type res_type)638 struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_ib_dev *dev,
639 						int res_num,
640 						enum mlx5_res_type res_type)
641 {
642 	u32 rsn = res_num | (res_type << MLX5_USER_INDEX_LEN);
643 	struct mlx5_qp_table *table = &dev->qp_table;
644 
645 	return mlx5_get_rsc(table, rsn);
646 }
647 
mlx5_core_res_put(struct mlx5_core_rsc_common * res)648 void mlx5_core_res_put(struct mlx5_core_rsc_common *res)
649 {
650 	mlx5_core_put_rsc(res);
651 }
652