1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #ifdef CONFIG_RFS_ACCEL
50 #include <linux/cpu_rmap.h>
51 #endif
52 #include <linux/version.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "lib/eq.h"
56 #include "fs_core.h"
57 #include "lib/mpfs.h"
58 #include "eswitch.h"
59 #include "devlink.h"
60 #include "fw_reset.h"
61 #include "lib/mlx5.h"
62 #include "lib/tout.h"
63 #include "fpga/core.h"
64 #include "en_accel/ipsec.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "lib/geneve.h"
68 #include "lib/devcom.h"
69 #include "lib/pci_vsc.h"
70 #include "diag/fw_tracer.h"
71 #include "ecpf.h"
72 #include "lib/hv_vhca.h"
73 #include "diag/rsc_dump.h"
74 #include "sf/vhca_event.h"
75 #include "sf/dev/dev.h"
76 #include "sf/sf.h"
77 #include "mlx5_irq.h"
78
79 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
80 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
81 MODULE_LICENSE("Dual BSD/GPL");
82
83 unsigned int mlx5_core_debug_mask;
84 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
85 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
86
87 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
88 module_param_named(prof_sel, prof_sel, uint, 0444);
89 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
90
91 static u32 sw_owner_id[4];
92 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
93 static DEFINE_IDA(sw_vhca_ida);
94
95 enum {
96 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
98 };
99
100 #define LOG_MAX_SUPPORTED_QPS 0xff
101
102 static struct mlx5_profile profile[] = {
103 [0] = {
104 .mask = 0,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 },
110 [2] = {
111 .mask = MLX5_PROF_MASK_QP_SIZE |
112 MLX5_PROF_MASK_MR_CACHE,
113 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
114 .mr_cache[0] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[1] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[2] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[3] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[4] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[5] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[6] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[7] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[8] = {
147 .size = 500,
148 .limit = 250
149 },
150 .mr_cache[9] = {
151 .size = 500,
152 .limit = 250
153 },
154 .mr_cache[10] = {
155 .size = 500,
156 .limit = 250
157 },
158 .mr_cache[11] = {
159 .size = 500,
160 .limit = 250
161 },
162 .mr_cache[12] = {
163 .size = 64,
164 .limit = 32
165 },
166 .mr_cache[13] = {
167 .size = 32,
168 .limit = 16
169 },
170 .mr_cache[14] = {
171 .size = 16,
172 .limit = 8
173 },
174 .mr_cache[15] = {
175 .size = 8,
176 .limit = 4
177 },
178 },
179 };
180
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)181 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
182 u32 warn_time_mili)
183 {
184 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
185 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
186 u32 fw_initializing;
187 int err = 0;
188
189 do {
190 fw_initializing = ioread32be(&dev->iseg->initializing);
191 if (!(fw_initializing >> 31))
192 break;
193 if (time_after(jiffies, end) ||
194 test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
195 err = -EBUSY;
196 break;
197 }
198 if (warn_time_mili && time_after(jiffies, warn)) {
199 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n",
200 jiffies_to_msecs(end - warn) / 1000, fw_initializing);
201 warn = jiffies + msecs_to_jiffies(warn_time_mili);
202 }
203 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
204 } while (true);
205
206 return err;
207 }
208
mlx5_set_driver_version(struct mlx5_core_dev * dev)209 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
210 {
211 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
212 driver_version);
213 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
214 int remaining_size = driver_ver_sz;
215 char *string;
216
217 if (!MLX5_CAP_GEN(dev, driver_version))
218 return;
219
220 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
221
222 strncpy(string, "Linux", remaining_size);
223
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, ",", remaining_size);
226
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, KBUILD_MODNAME, remaining_size);
229
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, ",", remaining_size);
232
233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234
235 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
236 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
237 LINUX_VERSION_SUBLEVEL);
238
239 /*Send the command*/
240 MLX5_SET(set_driver_version_in, in, opcode,
241 MLX5_CMD_OP_SET_DRIVER_VERSION);
242
243 mlx5_cmd_exec_in(dev, set_driver_version, in);
244 }
245
set_dma_caps(struct pci_dev * pdev)246 static int set_dma_caps(struct pci_dev *pdev)
247 {
248 int err;
249
250 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
251 if (err) {
252 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
253 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
254 if (err) {
255 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
256 return err;
257 }
258 }
259
260 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
261 return err;
262 }
263
mlx5_pci_enable_device(struct mlx5_core_dev * dev)264 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
265 {
266 struct pci_dev *pdev = dev->pdev;
267 int err = 0;
268
269 mutex_lock(&dev->pci_status_mutex);
270 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
271 err = pci_enable_device(pdev);
272 if (!err)
273 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
274 }
275 mutex_unlock(&dev->pci_status_mutex);
276
277 return err;
278 }
279
mlx5_pci_disable_device(struct mlx5_core_dev * dev)280 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
281 {
282 struct pci_dev *pdev = dev->pdev;
283
284 mutex_lock(&dev->pci_status_mutex);
285 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
286 pci_disable_device(pdev);
287 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
288 }
289 mutex_unlock(&dev->pci_status_mutex);
290 }
291
request_bar(struct pci_dev * pdev)292 static int request_bar(struct pci_dev *pdev)
293 {
294 int err = 0;
295
296 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
297 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
298 return -ENODEV;
299 }
300
301 err = pci_request_regions(pdev, KBUILD_MODNAME);
302 if (err)
303 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
304
305 return err;
306 }
307
release_bar(struct pci_dev * pdev)308 static void release_bar(struct pci_dev *pdev)
309 {
310 pci_release_regions(pdev);
311 }
312
313 struct mlx5_reg_host_endianness {
314 u8 he;
315 u8 rsvd[15];
316 };
317
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)318 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
319 {
320 switch (size) {
321 case 128:
322 return 0;
323 case 256:
324 return 1;
325 case 512:
326 return 2;
327 case 1024:
328 return 3;
329 case 2048:
330 return 4;
331 case 4096:
332 return 5;
333 default:
334 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
335 return 0;
336 }
337 }
338
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)339 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
340 {
341 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
342 dev->mlx5e_res.uplink_netdev = netdev;
343 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
344 netdev);
345 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
346 }
347
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)348 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
349 {
350 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
351 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
352 dev->mlx5e_res.uplink_netdev);
353 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
354 }
355 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
356
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)357 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
358 enum mlx5_cap_type cap_type,
359 enum mlx5_cap_mode cap_mode)
360 {
361 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
362 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
363 void *out, *hca_caps;
364 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
365 int err;
366
367 memset(in, 0, sizeof(in));
368 out = kzalloc(out_sz, GFP_KERNEL);
369 if (!out)
370 return -ENOMEM;
371
372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
375 if (err) {
376 mlx5_core_warn(dev,
377 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
378 cap_type, cap_mode, err);
379 goto query_ex;
380 }
381
382 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
383
384 switch (cap_mode) {
385 case HCA_CAP_OPMOD_GET_MAX:
386 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
387 MLX5_UN_SZ_BYTES(hca_cap_union));
388 break;
389 case HCA_CAP_OPMOD_GET_CUR:
390 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 default:
394 mlx5_core_warn(dev,
395 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
396 cap_type, cap_mode);
397 err = -EINVAL;
398 break;
399 }
400 query_ex:
401 kfree(out);
402 return err;
403 }
404
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)405 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
406 {
407 int ret;
408
409 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
410 if (ret)
411 return ret;
412 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
413 }
414
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)415 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
416 {
417 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
418 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
419 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
420 }
421
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)422 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
423 {
424 void *set_hca_cap;
425 int req_endianness;
426 int err;
427
428 if (!MLX5_CAP_GEN(dev, atomic))
429 return 0;
430
431 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
432 if (err)
433 return err;
434
435 req_endianness =
436 MLX5_CAP_ATOMIC(dev,
437 supported_atomic_req_8B_endianness_mode_1);
438
439 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
440 return 0;
441
442 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
443
444 /* Set requestor to host endianness */
445 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
446 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
447
448 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
449 }
450
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)451 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
452 {
453 void *set_hca_cap;
454 bool do_set = false;
455 int err;
456
457 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
458 !MLX5_CAP_GEN(dev, pg))
459 return 0;
460
461 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
462 if (err)
463 return err;
464
465 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
466 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
467 MLX5_ST_SZ_BYTES(odp_cap));
468
469 #define ODP_CAP_SET_MAX(dev, field) \
470 do { \
471 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
472 if (_res) { \
473 do_set = true; \
474 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
475 } \
476 } while (0)
477
478 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
479 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
482 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
486 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
487 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
488 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
489 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
492
493 if (!do_set)
494 return 0;
495
496 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
497 }
498
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)499 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
500 {
501 struct devlink *devlink = priv_to_devlink(dev);
502 union devlink_param_value val;
503 int err;
504
505 err = devl_param_driverinit_value_get(devlink,
506 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
507 &val);
508 if (!err)
509 return val.vu32;
510 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
511 return err;
512 }
513
mlx5_is_roce_on(struct mlx5_core_dev * dev)514 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
515 {
516 struct devlink *devlink = priv_to_devlink(dev);
517 union devlink_param_value val;
518 int err;
519
520 err = devl_param_driverinit_value_get(devlink,
521 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
522 &val);
523
524 if (!err)
525 return val.vbool;
526
527 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
528 return MLX5_CAP_GEN(dev, roce);
529 }
530 EXPORT_SYMBOL(mlx5_is_roce_on);
531
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)532 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
533 {
534 void *set_hca_cap;
535 int err;
536
537 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
538 return 0;
539
540 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
541 if (err)
542 return err;
543
544 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
545 !(dev->priv.sw_vhca_id > 0))
546 return 0;
547
548 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
549 capability);
550 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
551 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
552 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
553
554 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
555 }
556
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)557 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
558 {
559 struct mlx5_profile *prof = &dev->profile;
560 void *set_hca_cap;
561 int max_uc_list;
562 int err;
563
564 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
565 if (err)
566 return err;
567
568 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
569 capability);
570 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
571 MLX5_ST_SZ_BYTES(cmd_hca_cap));
572
573 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
574 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
575 128);
576 /* we limit the size of the pkey table to 128 entries for now */
577 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
578 to_fw_pkey_sz(dev, 128));
579
580 /* Check log_max_qp from HCA caps to set in current profile */
581 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
582 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
583 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
584 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
585 prof->log_max_qp,
586 MLX5_CAP_GEN_MAX(dev, log_max_qp));
587 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
588 }
589 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
590 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
591 prof->log_max_qp);
592
593 /* disable cmdif checksum */
594 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
595
596 /* Enable 4K UAR only when HCA supports it and page size is bigger
597 * than 4K.
598 */
599 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
600 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
601
602 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
603
604 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
605 MLX5_SET(cmd_hca_cap,
606 set_hca_cap,
607 cache_line_128byte,
608 cache_line_size() >= 128 ? 1 : 0);
609
610 if (MLX5_CAP_GEN_MAX(dev, dct))
611 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
612
613 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
614 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
615
616 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
617 MLX5_SET(cmd_hca_cap,
618 set_hca_cap,
619 num_vhca_ports,
620 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
621
622 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
623 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
624
625 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
626 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
627
628 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
629
630 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
631 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
632 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
633
634 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
635 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
636 mlx5_is_roce_on(dev));
637
638 max_uc_list = max_uc_list_get_devlink_param(dev);
639 if (max_uc_list > 0)
640 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
641 ilog2(max_uc_list));
642
643 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
644 }
645
646 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
647 * boot process.
648 * In case RoCE cap is writable in FW and user/devlink requested to change the
649 * cap, we are yet to query the final state of the above cap.
650 * Hence, the need for this function.
651 *
652 * Returns
653 * True:
654 * 1) RoCE cap is read only in FW and already disabled
655 * OR:
656 * 2) RoCE cap is writable in FW and user/devlink requested it off.
657 *
658 * In any other case, return False.
659 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)660 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
661 {
662 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
663 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
664 }
665
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)666 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
667 {
668 void *set_hca_cap;
669 int err;
670
671 if (is_roce_fw_disabled(dev))
672 return 0;
673
674 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
675 if (err)
676 return err;
677
678 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
679 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
680 return 0;
681
682 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
683 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
684 MLX5_ST_SZ_BYTES(roce_cap));
685 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
686
687 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
688 return err;
689 }
690
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)691 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
692 void *set_ctx)
693 {
694 void *set_hca_cap;
695 int err;
696
697 if (!MLX5_CAP_GEN(dev, port_selection_cap))
698 return 0;
699
700 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
701 if (err)
702 return err;
703
704 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
705 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
706 return 0;
707
708 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
709 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
710 MLX5_ST_SZ_BYTES(port_selection_cap));
711 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
712
713 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION);
714
715 return err;
716 }
717
set_hca_cap(struct mlx5_core_dev * dev)718 static int set_hca_cap(struct mlx5_core_dev *dev)
719 {
720 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
721 void *set_ctx;
722 int err;
723
724 set_ctx = kzalloc(set_sz, GFP_KERNEL);
725 if (!set_ctx)
726 return -ENOMEM;
727
728 err = handle_hca_cap(dev, set_ctx);
729 if (err) {
730 mlx5_core_err(dev, "handle_hca_cap failed\n");
731 goto out;
732 }
733
734 memset(set_ctx, 0, set_sz);
735 err = handle_hca_cap_atomic(dev, set_ctx);
736 if (err) {
737 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
738 goto out;
739 }
740
741 memset(set_ctx, 0, set_sz);
742 err = handle_hca_cap_odp(dev, set_ctx);
743 if (err) {
744 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
745 goto out;
746 }
747
748 memset(set_ctx, 0, set_sz);
749 err = handle_hca_cap_roce(dev, set_ctx);
750 if (err) {
751 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
752 goto out;
753 }
754
755 memset(set_ctx, 0, set_sz);
756 err = handle_hca_cap_2(dev, set_ctx);
757 if (err) {
758 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
759 goto out;
760 }
761
762 memset(set_ctx, 0, set_sz);
763 err = handle_hca_cap_port_selection(dev, set_ctx);
764 if (err) {
765 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
766 goto out;
767 }
768
769 out:
770 kfree(set_ctx);
771 return err;
772 }
773
set_hca_ctrl(struct mlx5_core_dev * dev)774 static int set_hca_ctrl(struct mlx5_core_dev *dev)
775 {
776 struct mlx5_reg_host_endianness he_in;
777 struct mlx5_reg_host_endianness he_out;
778 int err;
779
780 if (!mlx5_core_is_pf(dev))
781 return 0;
782
783 memset(&he_in, 0, sizeof(he_in));
784 he_in.he = MLX5_SET_HOST_ENDIANNESS;
785 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
786 &he_out, sizeof(he_out),
787 MLX5_REG_HOST_ENDIANNESS, 0, 1);
788 return err;
789 }
790
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)791 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
792 {
793 int ret = 0;
794
795 /* Disable local_lb by default */
796 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
797 ret = mlx5_nic_vport_update_local_lb(dev, false);
798
799 return ret;
800 }
801
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)802 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
803 {
804 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
805
806 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
807 MLX5_SET(enable_hca_in, in, function_id, func_id);
808 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
809 dev->caps.embedded_cpu);
810 return mlx5_cmd_exec_in(dev, enable_hca, in);
811 }
812
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)813 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
814 {
815 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
816
817 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
818 MLX5_SET(disable_hca_in, in, function_id, func_id);
819 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
820 dev->caps.embedded_cpu);
821 return mlx5_cmd_exec_in(dev, disable_hca, in);
822 }
823
mlx5_core_set_issi(struct mlx5_core_dev * dev)824 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
825 {
826 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
827 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
828 u32 sup_issi;
829 int err;
830
831 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
832 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
833 if (err) {
834 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
835 u8 status = MLX5_GET(query_issi_out, query_out, status);
836
837 if (!status || syndrome == MLX5_DRIVER_SYND) {
838 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
839 err, status, syndrome);
840 return err;
841 }
842
843 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
844 dev->issi = 0;
845 return 0;
846 }
847
848 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
849
850 if (sup_issi & (1 << 1)) {
851 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
852
853 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
854 MLX5_SET(set_issi_in, set_in, current_issi, 1);
855 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
856 if (err) {
857 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
858 err);
859 return err;
860 }
861
862 dev->issi = 1;
863
864 return 0;
865 } else if (sup_issi & (1 << 0) || !sup_issi) {
866 return 0;
867 }
868
869 return -EOPNOTSUPP;
870 }
871
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)872 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
873 const struct pci_device_id *id)
874 {
875 int err = 0;
876
877 mutex_init(&dev->pci_status_mutex);
878 pci_set_drvdata(dev->pdev, dev);
879
880 dev->bar_addr = pci_resource_start(pdev, 0);
881
882 err = mlx5_pci_enable_device(dev);
883 if (err) {
884 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
885 return err;
886 }
887
888 err = request_bar(pdev);
889 if (err) {
890 mlx5_core_err(dev, "error requesting BARs, aborting\n");
891 goto err_disable;
892 }
893
894 pci_set_master(pdev);
895
896 err = set_dma_caps(pdev);
897 if (err) {
898 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
899 goto err_clr_master;
900 }
901
902 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
903 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
904 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
905 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
906
907 dev->iseg_base = dev->bar_addr;
908 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
909 if (!dev->iseg) {
910 err = -ENOMEM;
911 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
912 goto err_clr_master;
913 }
914
915 mlx5_pci_vsc_init(dev);
916 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
917 return 0;
918
919 err_clr_master:
920 pci_clear_master(dev->pdev);
921 release_bar(dev->pdev);
922 err_disable:
923 mlx5_pci_disable_device(dev);
924 return err;
925 }
926
mlx5_pci_close(struct mlx5_core_dev * dev)927 static void mlx5_pci_close(struct mlx5_core_dev *dev)
928 {
929 /* health work might still be active, and it needs pci bar in
930 * order to know the NIC state. Therefore, drain the health WQ
931 * before removing the pci bars
932 */
933 mlx5_drain_health_wq(dev);
934 iounmap(dev->iseg);
935 pci_clear_master(dev->pdev);
936 release_bar(dev->pdev);
937 mlx5_pci_disable_device(dev);
938 }
939
mlx5_init_once(struct mlx5_core_dev * dev)940 static int mlx5_init_once(struct mlx5_core_dev *dev)
941 {
942 int err;
943
944 dev->priv.devcom = mlx5_devcom_register_device(dev);
945 if (IS_ERR(dev->priv.devcom))
946 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
947 dev->priv.devcom);
948
949 err = mlx5_query_board_id(dev);
950 if (err) {
951 mlx5_core_err(dev, "query board id failed\n");
952 goto err_devcom;
953 }
954
955 err = mlx5_irq_table_init(dev);
956 if (err) {
957 mlx5_core_err(dev, "failed to initialize irq table\n");
958 goto err_devcom;
959 }
960
961 err = mlx5_eq_table_init(dev);
962 if (err) {
963 mlx5_core_err(dev, "failed to initialize eq\n");
964 goto err_irq_cleanup;
965 }
966
967 err = mlx5_events_init(dev);
968 if (err) {
969 mlx5_core_err(dev, "failed to initialize events\n");
970 goto err_eq_cleanup;
971 }
972
973 err = mlx5_fw_reset_init(dev);
974 if (err) {
975 mlx5_core_err(dev, "failed to initialize fw reset events\n");
976 goto err_events_cleanup;
977 }
978
979 mlx5_cq_debugfs_init(dev);
980
981 mlx5_init_reserved_gids(dev);
982
983 mlx5_init_clock(dev);
984
985 dev->vxlan = mlx5_vxlan_create(dev);
986 dev->geneve = mlx5_geneve_create(dev);
987
988 err = mlx5_init_rl_table(dev);
989 if (err) {
990 mlx5_core_err(dev, "Failed to init rate limiting\n");
991 goto err_tables_cleanup;
992 }
993
994 err = mlx5_mpfs_init(dev);
995 if (err) {
996 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
997 goto err_rl_cleanup;
998 }
999
1000 err = mlx5_sriov_init(dev);
1001 if (err) {
1002 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1003 goto err_mpfs_cleanup;
1004 }
1005
1006 err = mlx5_eswitch_init(dev);
1007 if (err) {
1008 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1009 goto err_sriov_cleanup;
1010 }
1011
1012 err = mlx5_fpga_init(dev);
1013 if (err) {
1014 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1015 goto err_eswitch_cleanup;
1016 }
1017
1018 err = mlx5_vhca_event_init(dev);
1019 if (err) {
1020 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1021 goto err_fpga_cleanup;
1022 }
1023
1024 err = mlx5_sf_hw_table_init(dev);
1025 if (err) {
1026 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1027 goto err_sf_hw_table_cleanup;
1028 }
1029
1030 err = mlx5_sf_table_init(dev);
1031 if (err) {
1032 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1033 goto err_sf_table_cleanup;
1034 }
1035
1036 err = mlx5_fs_core_alloc(dev);
1037 if (err) {
1038 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1039 goto err_fs;
1040 }
1041
1042 dev->dm = mlx5_dm_create(dev);
1043 if (IS_ERR(dev->dm))
1044 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
1045
1046 dev->tracer = mlx5_fw_tracer_create(dev);
1047 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1048 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1049
1050 return 0;
1051
1052 err_fs:
1053 mlx5_sf_table_cleanup(dev);
1054 err_sf_table_cleanup:
1055 mlx5_sf_hw_table_cleanup(dev);
1056 err_sf_hw_table_cleanup:
1057 mlx5_vhca_event_cleanup(dev);
1058 err_fpga_cleanup:
1059 mlx5_fpga_cleanup(dev);
1060 err_eswitch_cleanup:
1061 mlx5_eswitch_cleanup(dev->priv.eswitch);
1062 err_sriov_cleanup:
1063 mlx5_sriov_cleanup(dev);
1064 err_mpfs_cleanup:
1065 mlx5_mpfs_cleanup(dev);
1066 err_rl_cleanup:
1067 mlx5_cleanup_rl_table(dev);
1068 err_tables_cleanup:
1069 mlx5_geneve_destroy(dev->geneve);
1070 mlx5_vxlan_destroy(dev->vxlan);
1071 mlx5_cleanup_clock(dev);
1072 mlx5_cleanup_reserved_gids(dev);
1073 mlx5_cq_debugfs_cleanup(dev);
1074 mlx5_fw_reset_cleanup(dev);
1075 err_events_cleanup:
1076 mlx5_events_cleanup(dev);
1077 err_eq_cleanup:
1078 mlx5_eq_table_cleanup(dev);
1079 err_irq_cleanup:
1080 mlx5_irq_table_cleanup(dev);
1081 err_devcom:
1082 mlx5_devcom_unregister_device(dev->priv.devcom);
1083
1084 return err;
1085 }
1086
mlx5_cleanup_once(struct mlx5_core_dev * dev)1087 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1088 {
1089 mlx5_rsc_dump_destroy(dev);
1090 mlx5_hv_vhca_destroy(dev->hv_vhca);
1091 mlx5_fw_tracer_destroy(dev->tracer);
1092 mlx5_dm_cleanup(dev);
1093 mlx5_fs_core_free(dev);
1094 mlx5_sf_table_cleanup(dev);
1095 mlx5_sf_hw_table_cleanup(dev);
1096 mlx5_vhca_event_cleanup(dev);
1097 mlx5_fpga_cleanup(dev);
1098 mlx5_eswitch_cleanup(dev->priv.eswitch);
1099 mlx5_sriov_cleanup(dev);
1100 mlx5_mpfs_cleanup(dev);
1101 mlx5_cleanup_rl_table(dev);
1102 mlx5_geneve_destroy(dev->geneve);
1103 mlx5_vxlan_destroy(dev->vxlan);
1104 mlx5_cleanup_clock(dev);
1105 mlx5_cleanup_reserved_gids(dev);
1106 mlx5_cq_debugfs_cleanup(dev);
1107 mlx5_fw_reset_cleanup(dev);
1108 mlx5_events_cleanup(dev);
1109 mlx5_eq_table_cleanup(dev);
1110 mlx5_irq_table_cleanup(dev);
1111 mlx5_devcom_unregister_device(dev->priv.devcom);
1112 }
1113
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1114 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1115 {
1116 int err;
1117
1118 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1119 fw_rev_min(dev), fw_rev_sub(dev));
1120
1121 /* Only PFs hold the relevant PCIe information for this query */
1122 if (mlx5_core_is_pf(dev))
1123 pcie_print_link_status(dev->pdev);
1124
1125 /* wait for firmware to accept initialization segments configurations
1126 */
1127 err = wait_fw_init(dev, timeout,
1128 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1129 if (err) {
1130 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1131 timeout);
1132 return err;
1133 }
1134
1135 err = mlx5_cmd_init(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1138 return err;
1139 }
1140
1141 mlx5_tout_query_iseg(dev);
1142
1143 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1144 if (err) {
1145 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1146 mlx5_tout_ms(dev, FW_INIT));
1147 goto err_cmd_cleanup;
1148 }
1149
1150 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1151
1152 mlx5_start_health_poll(dev);
1153
1154 err = mlx5_core_enable_hca(dev, 0);
1155 if (err) {
1156 mlx5_core_err(dev, "enable hca failed\n");
1157 goto stop_health_poll;
1158 }
1159
1160 err = mlx5_core_set_issi(dev);
1161 if (err) {
1162 mlx5_core_err(dev, "failed to set issi\n");
1163 goto err_disable_hca;
1164 }
1165
1166 err = mlx5_satisfy_startup_pages(dev, 1);
1167 if (err) {
1168 mlx5_core_err(dev, "failed to allocate boot pages\n");
1169 goto err_disable_hca;
1170 }
1171
1172 err = mlx5_tout_query_dtor(dev);
1173 if (err) {
1174 mlx5_core_err(dev, "failed to read dtor\n");
1175 goto reclaim_boot_pages;
1176 }
1177
1178 err = set_hca_ctrl(dev);
1179 if (err) {
1180 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1181 goto reclaim_boot_pages;
1182 }
1183
1184 err = set_hca_cap(dev);
1185 if (err) {
1186 mlx5_core_err(dev, "set_hca_cap failed\n");
1187 goto reclaim_boot_pages;
1188 }
1189
1190 err = mlx5_satisfy_startup_pages(dev, 0);
1191 if (err) {
1192 mlx5_core_err(dev, "failed to allocate init pages\n");
1193 goto reclaim_boot_pages;
1194 }
1195
1196 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1197 if (err) {
1198 mlx5_core_err(dev, "init hca failed\n");
1199 goto reclaim_boot_pages;
1200 }
1201
1202 mlx5_set_driver_version(dev);
1203
1204 err = mlx5_query_hca_caps(dev);
1205 if (err) {
1206 mlx5_core_err(dev, "query hca failed\n");
1207 goto reclaim_boot_pages;
1208 }
1209 mlx5_start_health_fw_log_up(dev);
1210
1211 return 0;
1212
1213 reclaim_boot_pages:
1214 mlx5_reclaim_startup_pages(dev);
1215 err_disable_hca:
1216 mlx5_core_disable_hca(dev, 0);
1217 stop_health_poll:
1218 mlx5_stop_health_poll(dev, boot);
1219 err_cmd_cleanup:
1220 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1221 mlx5_cmd_cleanup(dev);
1222
1223 return err;
1224 }
1225
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1226 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1227 {
1228 int err;
1229
1230 err = mlx5_cmd_teardown_hca(dev);
1231 if (err) {
1232 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1233 return err;
1234 }
1235 mlx5_reclaim_startup_pages(dev);
1236 mlx5_core_disable_hca(dev, 0);
1237 mlx5_stop_health_poll(dev, boot);
1238 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1239 mlx5_cmd_cleanup(dev);
1240
1241 return 0;
1242 }
1243
mlx5_load(struct mlx5_core_dev * dev)1244 static int mlx5_load(struct mlx5_core_dev *dev)
1245 {
1246 int err;
1247
1248 dev->priv.uar = mlx5_get_uars_page(dev);
1249 if (IS_ERR(dev->priv.uar)) {
1250 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1251 err = PTR_ERR(dev->priv.uar);
1252 return err;
1253 }
1254
1255 mlx5_events_start(dev);
1256 mlx5_pagealloc_start(dev);
1257
1258 err = mlx5_irq_table_create(dev);
1259 if (err) {
1260 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1261 goto err_irq_table;
1262 }
1263
1264 err = mlx5_eq_table_create(dev);
1265 if (err) {
1266 mlx5_core_err(dev, "Failed to create EQs\n");
1267 goto err_eq_table;
1268 }
1269
1270 err = mlx5_fw_tracer_init(dev->tracer);
1271 if (err) {
1272 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1273 mlx5_fw_tracer_destroy(dev->tracer);
1274 dev->tracer = NULL;
1275 }
1276
1277 mlx5_fw_reset_events_start(dev);
1278 mlx5_hv_vhca_init(dev->hv_vhca);
1279
1280 err = mlx5_rsc_dump_init(dev);
1281 if (err) {
1282 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1283 mlx5_rsc_dump_destroy(dev);
1284 dev->rsc_dump = NULL;
1285 }
1286
1287 err = mlx5_fpga_device_start(dev);
1288 if (err) {
1289 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1290 goto err_fpga_start;
1291 }
1292
1293 err = mlx5_fs_core_init(dev);
1294 if (err) {
1295 mlx5_core_err(dev, "Failed to init flow steering\n");
1296 goto err_fs;
1297 }
1298
1299 err = mlx5_core_set_hca_defaults(dev);
1300 if (err) {
1301 mlx5_core_err(dev, "Failed to set hca defaults\n");
1302 goto err_set_hca;
1303 }
1304
1305 mlx5_vhca_event_start(dev);
1306
1307 err = mlx5_sf_hw_table_create(dev);
1308 if (err) {
1309 mlx5_core_err(dev, "sf table create failed %d\n", err);
1310 goto err_vhca;
1311 }
1312
1313 err = mlx5_ec_init(dev);
1314 if (err) {
1315 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1316 goto err_ec;
1317 }
1318
1319 mlx5_lag_add_mdev(dev);
1320 err = mlx5_sriov_attach(dev);
1321 if (err) {
1322 mlx5_core_err(dev, "sriov init failed %d\n", err);
1323 goto err_sriov;
1324 }
1325
1326 mlx5_sf_dev_table_create(dev);
1327
1328 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1329 if (err)
1330 goto err_traps_reg;
1331
1332 return 0;
1333
1334 err_traps_reg:
1335 mlx5_sf_dev_table_destroy(dev);
1336 mlx5_sriov_detach(dev);
1337 err_sriov:
1338 mlx5_lag_remove_mdev(dev);
1339 mlx5_ec_cleanup(dev);
1340 err_ec:
1341 mlx5_sf_hw_table_destroy(dev);
1342 err_vhca:
1343 mlx5_vhca_event_stop(dev);
1344 err_set_hca:
1345 mlx5_fs_core_cleanup(dev);
1346 err_fs:
1347 mlx5_fpga_device_stop(dev);
1348 err_fpga_start:
1349 mlx5_rsc_dump_cleanup(dev);
1350 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1351 mlx5_fw_reset_events_stop(dev);
1352 mlx5_fw_tracer_cleanup(dev->tracer);
1353 mlx5_eq_table_destroy(dev);
1354 err_eq_table:
1355 mlx5_irq_table_destroy(dev);
1356 err_irq_table:
1357 mlx5_pagealloc_stop(dev);
1358 mlx5_events_stop(dev);
1359 mlx5_put_uars_page(dev, dev->priv.uar);
1360 return err;
1361 }
1362
mlx5_unload(struct mlx5_core_dev * dev)1363 static void mlx5_unload(struct mlx5_core_dev *dev)
1364 {
1365 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1366 mlx5_sf_dev_table_destroy(dev);
1367 mlx5_sriov_detach(dev);
1368 mlx5_eswitch_disable(dev->priv.eswitch);
1369 mlx5_lag_remove_mdev(dev);
1370 mlx5_ec_cleanup(dev);
1371 mlx5_sf_hw_table_destroy(dev);
1372 mlx5_vhca_event_stop(dev);
1373 mlx5_fs_core_cleanup(dev);
1374 mlx5_fpga_device_stop(dev);
1375 mlx5_rsc_dump_cleanup(dev);
1376 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1377 mlx5_fw_reset_events_stop(dev);
1378 mlx5_fw_tracer_cleanup(dev->tracer);
1379 mlx5_eq_table_destroy(dev);
1380 mlx5_irq_table_destroy(dev);
1381 mlx5_pagealloc_stop(dev);
1382 mlx5_events_stop(dev);
1383 mlx5_put_uars_page(dev, dev->priv.uar);
1384 }
1385
mlx5_init_one(struct mlx5_core_dev * dev)1386 int mlx5_init_one(struct mlx5_core_dev *dev)
1387 {
1388 struct devlink *devlink = priv_to_devlink(dev);
1389 int err = 0;
1390
1391 devl_lock(devlink);
1392 mutex_lock(&dev->intf_state_mutex);
1393 dev->state = MLX5_DEVICE_STATE_UP;
1394
1395 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1396 if (err)
1397 goto err_function;
1398
1399 err = mlx5_init_once(dev);
1400 if (err) {
1401 mlx5_core_err(dev, "sw objs init failed\n");
1402 goto function_teardown;
1403 }
1404
1405 err = mlx5_load(dev);
1406 if (err)
1407 goto err_load;
1408
1409 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1410
1411 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1412 if (err)
1413 goto err_devlink_params_reg;
1414
1415 err = mlx5_register_device(dev);
1416 if (err)
1417 goto err_register;
1418
1419 mutex_unlock(&dev->intf_state_mutex);
1420 devl_unlock(devlink);
1421 return 0;
1422
1423 err_register:
1424 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1425 err_devlink_params_reg:
1426 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1427 mlx5_unload(dev);
1428 err_load:
1429 mlx5_cleanup_once(dev);
1430 function_teardown:
1431 mlx5_function_teardown(dev, true);
1432 err_function:
1433 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1434 mutex_unlock(&dev->intf_state_mutex);
1435 devl_unlock(devlink);
1436 return err;
1437 }
1438
mlx5_uninit_one(struct mlx5_core_dev * dev)1439 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1440 {
1441 struct devlink *devlink = priv_to_devlink(dev);
1442
1443 devl_lock(devlink);
1444 mutex_lock(&dev->intf_state_mutex);
1445
1446 mlx5_unregister_device(dev);
1447 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1448
1449 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1450 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1451 __func__);
1452 mlx5_cleanup_once(dev);
1453 goto out;
1454 }
1455
1456 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1457 mlx5_unload(dev);
1458 mlx5_cleanup_once(dev);
1459 mlx5_function_teardown(dev, true);
1460 out:
1461 mutex_unlock(&dev->intf_state_mutex);
1462 devl_unlock(devlink);
1463 }
1464
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1465 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1466 {
1467 int err = 0;
1468 u64 timeout;
1469
1470 devl_assert_locked(priv_to_devlink(dev));
1471 mutex_lock(&dev->intf_state_mutex);
1472 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1473 mlx5_core_warn(dev, "interface is up, NOP\n");
1474 goto out;
1475 }
1476 /* remove any previous indication of internal error */
1477 dev->state = MLX5_DEVICE_STATE_UP;
1478
1479 if (recovery)
1480 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1481 else
1482 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1483 err = mlx5_function_setup(dev, false, timeout);
1484 if (err)
1485 goto err_function;
1486
1487 err = mlx5_load(dev);
1488 if (err)
1489 goto err_load;
1490
1491 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1492
1493 err = mlx5_attach_device(dev);
1494 if (err)
1495 goto err_attach;
1496
1497 mutex_unlock(&dev->intf_state_mutex);
1498 return 0;
1499
1500 err_attach:
1501 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1502 mlx5_unload(dev);
1503 err_load:
1504 mlx5_function_teardown(dev, false);
1505 err_function:
1506 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1507 out:
1508 mutex_unlock(&dev->intf_state_mutex);
1509 return err;
1510 }
1511
mlx5_load_one(struct mlx5_core_dev * dev)1512 int mlx5_load_one(struct mlx5_core_dev *dev)
1513 {
1514 struct devlink *devlink = priv_to_devlink(dev);
1515 int ret;
1516
1517 devl_lock(devlink);
1518 ret = mlx5_load_one_devl_locked(dev, false);
1519 devl_unlock(devlink);
1520 return ret;
1521 }
1522
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1523 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1524 {
1525 devl_assert_locked(priv_to_devlink(dev));
1526 mutex_lock(&dev->intf_state_mutex);
1527
1528 mlx5_detach_device(dev, suspend);
1529
1530 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1531 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1532 __func__);
1533 goto out;
1534 }
1535
1536 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1537 mlx5_unload(dev);
1538 mlx5_function_teardown(dev, false);
1539 out:
1540 mutex_unlock(&dev->intf_state_mutex);
1541 }
1542
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1543 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1544 {
1545 struct devlink *devlink = priv_to_devlink(dev);
1546
1547 devl_lock(devlink);
1548 mlx5_unload_one_devl_locked(dev, suspend);
1549 devl_unlock(devlink);
1550 }
1551
1552 static const int types[] = {
1553 MLX5_CAP_GENERAL,
1554 MLX5_CAP_GENERAL_2,
1555 MLX5_CAP_ETHERNET_OFFLOADS,
1556 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1557 MLX5_CAP_ODP,
1558 MLX5_CAP_ATOMIC,
1559 MLX5_CAP_ROCE,
1560 MLX5_CAP_IPOIB_OFFLOADS,
1561 MLX5_CAP_FLOW_TABLE,
1562 MLX5_CAP_ESWITCH_FLOW_TABLE,
1563 MLX5_CAP_ESWITCH,
1564 MLX5_CAP_VECTOR_CALC,
1565 MLX5_CAP_QOS,
1566 MLX5_CAP_DEBUG,
1567 MLX5_CAP_DEV_MEM,
1568 MLX5_CAP_DEV_EVENT,
1569 MLX5_CAP_TLS,
1570 MLX5_CAP_VDPA_EMULATION,
1571 MLX5_CAP_IPSEC,
1572 MLX5_CAP_PORT_SELECTION,
1573 MLX5_CAP_DEV_SHAMPO,
1574 MLX5_CAP_MACSEC,
1575 MLX5_CAP_ADV_VIRTUALIZATION,
1576 MLX5_CAP_CRYPTO,
1577 };
1578
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1579 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1580 {
1581 int type;
1582 int i;
1583
1584 for (i = 0; i < ARRAY_SIZE(types); i++) {
1585 type = types[i];
1586 kfree(dev->caps.hca[type]);
1587 }
1588 }
1589
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1590 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1591 {
1592 struct mlx5_hca_cap *cap;
1593 int type;
1594 int i;
1595
1596 for (i = 0; i < ARRAY_SIZE(types); i++) {
1597 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1598 if (!cap)
1599 goto err;
1600 type = types[i];
1601 dev->caps.hca[type] = cap;
1602 }
1603
1604 return 0;
1605
1606 err:
1607 mlx5_hca_caps_free(dev);
1608 return -ENOMEM;
1609 }
1610
vhca_id_show(struct seq_file * file,void * priv)1611 static int vhca_id_show(struct seq_file *file, void *priv)
1612 {
1613 struct mlx5_core_dev *dev = file->private;
1614
1615 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1616 return 0;
1617 }
1618
1619 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1620
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1621 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1622 {
1623 struct mlx5_priv *priv = &dev->priv;
1624 int err;
1625
1626 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1627 lockdep_register_key(&dev->lock_key);
1628 mutex_init(&dev->intf_state_mutex);
1629 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1630 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1631
1632 mutex_init(&priv->bfregs.reg_head.lock);
1633 mutex_init(&priv->bfregs.wc_head.lock);
1634 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1635 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1636
1637 mutex_init(&priv->alloc_mutex);
1638 mutex_init(&priv->pgdir_mutex);
1639 INIT_LIST_HEAD(&priv->pgdir_list);
1640
1641 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1642 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1643 mlx5_debugfs_root);
1644 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1645 INIT_LIST_HEAD(&priv->traps);
1646
1647 err = mlx5_tout_init(dev);
1648 if (err) {
1649 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1650 goto err_timeout_init;
1651 }
1652
1653 err = mlx5_health_init(dev);
1654 if (err)
1655 goto err_health_init;
1656
1657 err = mlx5_pagealloc_init(dev);
1658 if (err)
1659 goto err_pagealloc_init;
1660
1661 err = mlx5_adev_init(dev);
1662 if (err)
1663 goto err_adev_init;
1664
1665 err = mlx5_hca_caps_alloc(dev);
1666 if (err)
1667 goto err_hca_caps;
1668
1669 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1670 * unique id per function which uses mlx5_core.
1671 * Those values are supplied to FW as part of the init HCA command to
1672 * be used by both driver and FW when it's applicable.
1673 */
1674 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1675 MAX_SW_VHCA_ID,
1676 GFP_KERNEL);
1677 if (dev->priv.sw_vhca_id < 0)
1678 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1679 dev->priv.sw_vhca_id);
1680
1681 return 0;
1682
1683 err_hca_caps:
1684 mlx5_adev_cleanup(dev);
1685 err_adev_init:
1686 mlx5_pagealloc_cleanup(dev);
1687 err_pagealloc_init:
1688 mlx5_health_cleanup(dev);
1689 err_health_init:
1690 mlx5_tout_cleanup(dev);
1691 err_timeout_init:
1692 debugfs_remove(dev->priv.dbg.dbg_root);
1693 mutex_destroy(&priv->pgdir_mutex);
1694 mutex_destroy(&priv->alloc_mutex);
1695 mutex_destroy(&priv->bfregs.wc_head.lock);
1696 mutex_destroy(&priv->bfregs.reg_head.lock);
1697 mutex_destroy(&dev->intf_state_mutex);
1698 lockdep_unregister_key(&dev->lock_key);
1699 return err;
1700 }
1701
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1702 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1703 {
1704 struct mlx5_priv *priv = &dev->priv;
1705
1706 if (priv->sw_vhca_id > 0)
1707 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1708
1709 mlx5_hca_caps_free(dev);
1710 mlx5_adev_cleanup(dev);
1711 mlx5_pagealloc_cleanup(dev);
1712 mlx5_health_cleanup(dev);
1713 mlx5_tout_cleanup(dev);
1714 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1715 mutex_destroy(&priv->pgdir_mutex);
1716 mutex_destroy(&priv->alloc_mutex);
1717 mutex_destroy(&priv->bfregs.wc_head.lock);
1718 mutex_destroy(&priv->bfregs.reg_head.lock);
1719 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1720 mutex_destroy(&dev->intf_state_mutex);
1721 lockdep_unregister_key(&dev->lock_key);
1722 }
1723
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1724 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1725 {
1726 struct mlx5_core_dev *dev;
1727 struct devlink *devlink;
1728 int err;
1729
1730 devlink = mlx5_devlink_alloc(&pdev->dev);
1731 if (!devlink) {
1732 dev_err(&pdev->dev, "devlink alloc failed\n");
1733 return -ENOMEM;
1734 }
1735
1736 dev = devlink_priv(devlink);
1737 dev->device = &pdev->dev;
1738 dev->pdev = pdev;
1739
1740 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1741 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1742
1743 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1744 if (dev->priv.adev_idx < 0) {
1745 err = dev->priv.adev_idx;
1746 goto adev_init_err;
1747 }
1748
1749 err = mlx5_mdev_init(dev, prof_sel);
1750 if (err)
1751 goto mdev_init_err;
1752
1753 err = mlx5_pci_init(dev, pdev, id);
1754 if (err) {
1755 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1756 err);
1757 goto pci_init_err;
1758 }
1759
1760 err = mlx5_init_one(dev);
1761 if (err) {
1762 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1763 err);
1764 goto err_init_one;
1765 }
1766
1767 err = mlx5_crdump_enable(dev);
1768 if (err)
1769 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1770
1771 pci_save_state(pdev);
1772 devlink_register(devlink);
1773 return 0;
1774
1775 err_init_one:
1776 mlx5_pci_close(dev);
1777 pci_init_err:
1778 mlx5_mdev_uninit(dev);
1779 mdev_init_err:
1780 mlx5_adev_idx_free(dev->priv.adev_idx);
1781 adev_init_err:
1782 mlx5_devlink_free(devlink);
1783
1784 return err;
1785 }
1786
remove_one(struct pci_dev * pdev)1787 static void remove_one(struct pci_dev *pdev)
1788 {
1789 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1790 struct devlink *devlink = priv_to_devlink(dev);
1791
1792 /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain
1793 * fw_reset before unregistering the devlink.
1794 */
1795 mlx5_drain_fw_reset(dev);
1796 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1797 devlink_unregister(devlink);
1798 mlx5_sriov_disable(pdev);
1799 mlx5_crdump_disable(dev);
1800 mlx5_drain_health_wq(dev);
1801 mlx5_uninit_one(dev);
1802 mlx5_pci_close(dev);
1803 mlx5_mdev_uninit(dev);
1804 mlx5_adev_idx_free(dev->priv.adev_idx);
1805 mlx5_devlink_free(devlink);
1806 }
1807
1808 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1809 struct mlx5_core_dev *__dev = (dev); \
1810 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1811 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1812 __dev->pci_status, ##__VA_ARGS__); \
1813 })
1814
result2str(enum pci_ers_result result)1815 static const char *result2str(enum pci_ers_result result)
1816 {
1817 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1818 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1819 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1820 "unknown";
1821 }
1822
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1823 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1824 pci_channel_state_t state)
1825 {
1826 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1827 enum pci_ers_result res;
1828
1829 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1830
1831 mlx5_enter_error_state(dev, false);
1832 mlx5_error_sw_reset(dev);
1833 mlx5_unload_one(dev, true);
1834 mlx5_drain_health_wq(dev);
1835 mlx5_pci_disable_device(dev);
1836
1837 res = state == pci_channel_io_perm_failure ?
1838 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1839
1840 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
1841 __func__, dev->state, dev->pci_status, res, result2str(res));
1842 return res;
1843 }
1844
1845 /* wait for the device to show vital signs by waiting
1846 * for the health counter to start counting.
1847 */
wait_vital(struct pci_dev * pdev)1848 static int wait_vital(struct pci_dev *pdev)
1849 {
1850 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1851 struct mlx5_core_health *health = &dev->priv.health;
1852 const int niter = 100;
1853 u32 last_count = 0;
1854 u32 count;
1855 int i;
1856
1857 for (i = 0; i < niter; i++) {
1858 count = ioread32be(health->health_counter);
1859 if (count && count != 0xffffffff) {
1860 if (last_count && last_count != count) {
1861 mlx5_core_info(dev,
1862 "wait vital counter value 0x%x after %d iterations\n",
1863 count, i);
1864 return 0;
1865 }
1866 last_count = count;
1867 }
1868 msleep(50);
1869 }
1870
1871 return -ETIMEDOUT;
1872 }
1873
mlx5_pci_slot_reset(struct pci_dev * pdev)1874 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1875 {
1876 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1877 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1878 int err;
1879
1880 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
1881 __func__, dev->state, dev->pci_status);
1882
1883 err = mlx5_pci_enable_device(dev);
1884 if (err) {
1885 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1886 __func__, err);
1887 goto out;
1888 }
1889
1890 pci_set_master(pdev);
1891 pci_restore_state(pdev);
1892 pci_save_state(pdev);
1893
1894 err = wait_vital(pdev);
1895 if (err) {
1896 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1897 __func__, err);
1898 goto out;
1899 }
1900
1901 res = PCI_ERS_RESULT_RECOVERED;
1902 out:
1903 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
1904 __func__, dev->state, dev->pci_status, err, res, result2str(res));
1905 return res;
1906 }
1907
mlx5_pci_resume(struct pci_dev * pdev)1908 static void mlx5_pci_resume(struct pci_dev *pdev)
1909 {
1910 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1911 int err;
1912
1913 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1914
1915 err = mlx5_load_one(dev);
1916 if (!err)
1917 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
1918 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
1919
1920 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1921 !err ? "recovered" : "Failed");
1922 }
1923
1924 static const struct pci_error_handlers mlx5_err_handler = {
1925 .error_detected = mlx5_pci_err_detected,
1926 .slot_reset = mlx5_pci_slot_reset,
1927 .resume = mlx5_pci_resume
1928 };
1929
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1930 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1931 {
1932 bool fast_teardown = false, force_teardown = false;
1933 int ret = 1;
1934
1935 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1936 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1937
1938 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1939 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1940
1941 if (!fast_teardown && !force_teardown)
1942 return -EOPNOTSUPP;
1943
1944 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1945 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1946 return -EAGAIN;
1947 }
1948
1949 /* Panic tear down fw command will stop the PCI bus communication
1950 * with the HCA, so the health poll is no longer needed.
1951 */
1952 mlx5_drain_health_wq(dev);
1953 mlx5_stop_health_poll(dev, false);
1954
1955 ret = mlx5_cmd_fast_teardown_hca(dev);
1956 if (!ret)
1957 goto succeed;
1958
1959 ret = mlx5_cmd_force_teardown_hca(dev);
1960 if (!ret)
1961 goto succeed;
1962
1963 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1964 mlx5_start_health_poll(dev);
1965 return ret;
1966
1967 succeed:
1968 mlx5_enter_error_state(dev, true);
1969
1970 /* Some platforms requiring freeing the IRQ's in the shutdown
1971 * flow. If they aren't freed they can't be allocated after
1972 * kexec. There is no need to cleanup the mlx5_core software
1973 * contexts.
1974 */
1975 mlx5_core_eq_free_irqs(dev);
1976
1977 return 0;
1978 }
1979
shutdown(struct pci_dev * pdev)1980 static void shutdown(struct pci_dev *pdev)
1981 {
1982 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1983 int err;
1984
1985 mlx5_core_info(dev, "Shutdown was called\n");
1986 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
1987 err = mlx5_try_fast_unload(dev);
1988 if (err)
1989 mlx5_unload_one(dev, false);
1990 mlx5_pci_disable_device(dev);
1991 }
1992
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1993 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1994 {
1995 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1996
1997 mlx5_unload_one(dev, true);
1998
1999 return 0;
2000 }
2001
mlx5_resume(struct pci_dev * pdev)2002 static int mlx5_resume(struct pci_dev *pdev)
2003 {
2004 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2005
2006 return mlx5_load_one(dev);
2007 }
2008
2009 static const struct pci_device_id mlx5_core_pci_table[] = {
2010 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2011 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2012 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2013 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2014 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2015 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2016 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2017 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2018 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2019 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2020 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2021 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2022 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2023 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2024 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2025 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2026 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2027 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2028 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2029 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2030 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2031 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2032 { 0, }
2033 };
2034
2035 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2036
mlx5_disable_device(struct mlx5_core_dev * dev)2037 void mlx5_disable_device(struct mlx5_core_dev *dev)
2038 {
2039 mlx5_error_sw_reset(dev);
2040 mlx5_unload_one_devl_locked(dev, false);
2041 }
2042
mlx5_recover_device(struct mlx5_core_dev * dev)2043 int mlx5_recover_device(struct mlx5_core_dev *dev)
2044 {
2045 if (!mlx5_core_is_sf(dev)) {
2046 mlx5_pci_disable_device(dev);
2047 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2048 return -EIO;
2049 }
2050
2051 return mlx5_load_one_devl_locked(dev, true);
2052 }
2053
2054 static struct pci_driver mlx5_core_driver = {
2055 .name = KBUILD_MODNAME,
2056 .id_table = mlx5_core_pci_table,
2057 .probe = probe_one,
2058 .remove = remove_one,
2059 .suspend = mlx5_suspend,
2060 .resume = mlx5_resume,
2061 .shutdown = shutdown,
2062 .err_handler = &mlx5_err_handler,
2063 .sriov_configure = mlx5_core_sriov_configure,
2064 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2065 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2066 };
2067
2068 /**
2069 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2070 * mlx5_core is its driver.
2071 * @pdev: The associated PCI device.
2072 *
2073 * Upon return the interface state lock stay held to let caller uses it safely.
2074 * Caller must ensure to use the returned mlx5 device for a narrow window
2075 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2076 *
2077 * Return: Pointer to the associated mlx5_core_dev or NULL.
2078 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2079 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2080 {
2081 struct mlx5_core_dev *mdev;
2082
2083 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2084 if (IS_ERR(mdev))
2085 return NULL;
2086
2087 mutex_lock(&mdev->intf_state_mutex);
2088 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2089 mutex_unlock(&mdev->intf_state_mutex);
2090 return NULL;
2091 }
2092
2093 return mdev;
2094 }
2095 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2096
2097 /**
2098 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2099 * @mdev: The mlx5 core device.
2100 *
2101 * Upon return the interface state lock is unlocked and caller should not
2102 * access the mdev any more.
2103 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2104 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2105 {
2106 mutex_unlock(&mdev->intf_state_mutex);
2107 }
2108 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2109
mlx5_core_verify_params(void)2110 static void mlx5_core_verify_params(void)
2111 {
2112 if (prof_sel >= ARRAY_SIZE(profile)) {
2113 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2114 prof_sel,
2115 ARRAY_SIZE(profile) - 1,
2116 MLX5_DEFAULT_PROF);
2117 prof_sel = MLX5_DEFAULT_PROF;
2118 }
2119 }
2120
mlx5_init(void)2121 static int __init mlx5_init(void)
2122 {
2123 int err;
2124
2125 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2126 "mlx5_core name not in sync with kernel module name");
2127
2128 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2129
2130 mlx5_core_verify_params();
2131 mlx5_register_debugfs();
2132
2133 err = mlx5e_init();
2134 if (err)
2135 goto err_debug;
2136
2137 err = mlx5_sf_driver_register();
2138 if (err)
2139 goto err_sf;
2140
2141 err = pci_register_driver(&mlx5_core_driver);
2142 if (err)
2143 goto err_pci;
2144
2145 return 0;
2146
2147 err_pci:
2148 mlx5_sf_driver_unregister();
2149 err_sf:
2150 mlx5e_cleanup();
2151 err_debug:
2152 mlx5_unregister_debugfs();
2153 return err;
2154 }
2155
mlx5_cleanup(void)2156 static void __exit mlx5_cleanup(void)
2157 {
2158 pci_unregister_driver(&mlx5_core_driver);
2159 mlx5_sf_driver_unregister();
2160 mlx5e_cleanup();
2161 mlx5_unregister_debugfs();
2162 }
2163
2164 module_init(mlx5_init);
2165 module_exit(mlx5_cleanup);
2166