1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; If not, see <http://www.gnu.org/licenses/>.
15 *
16 * Author: Allen Kay <allen.m.kay@intel.com> - adapted from linux
17 */
18
19 #define PCI_DEVICE_ID_INTEL_E7520_MCH 0x3590
20 #define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
21
22 /* ioport ends */
23 #define PCI_PROBE_BIOS 0x0001
24 #define PCI_PROBE_CONF1 0x0002
25 #define PCI_PROBE_CONF2 0x0004
26 #define PCI_PROBE_MMCONF 0x0008
27 #define PCI_PROBE_MASK 0x000f
28 #define PCI_PROBE_NOEARLY 0x0010
29
30 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
31
32 extern unsigned int pci_probe;
33
34 /*
35 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
36 * on their northbrige except through the * %eax register. As such, you MUST
37 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
38 * accessor functions.
39 * In fact just use pci_config_*, nothing else please.
40 */
mmio_config_readb(void __iomem * pos)41 static inline unsigned char mmio_config_readb(void __iomem *pos)
42 {
43 u8 val;
44 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
45 return val;
46 }
47
mmio_config_readw(void __iomem * pos)48 static inline unsigned short mmio_config_readw(void __iomem *pos)
49 {
50 u16 val;
51 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
52 return val;
53 }
54
mmio_config_readl(void __iomem * pos)55 static inline unsigned int mmio_config_readl(void __iomem *pos)
56 {
57 u32 val;
58 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
59 return val;
60 }
61
mmio_config_writeb(void __iomem * pos,u8 val)62 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
63 {
64 asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
65 }
66
mmio_config_writew(void __iomem * pos,u16 val)67 static inline void mmio_config_writew(void __iomem *pos, u16 val)
68 {
69 asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
70 }
71
mmio_config_writel(void __iomem * pos,u32 val)72 static inline void mmio_config_writel(void __iomem *pos, u32 val)
73 {
74 asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
75 }
76
77 /* external variable defines */
78 extern int pci_mmcfg_config_num;
79 extern struct acpi_mcfg_allocation *pci_mmcfg_config;
80
81 /* function prototypes */
82 int acpi_parse_mcfg(struct acpi_table_header *header);
83 int pci_mmcfg_reserved(uint64_t address, unsigned int segment,
84 unsigned int start_bus, unsigned int end_bus,
85 unsigned int flags);
86 int pci_mmcfg_arch_init(void);
87 int pci_mmcfg_arch_enable(unsigned int);
88 void pci_mmcfg_arch_disable(unsigned int);
89