1 /*
2  * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <drivers/delay_timer.h>
9 #include <lib/mmio.h>
10 
11 #include <msm8916_mmap.h>
12 #include "msm8916_pm.h"
13 
14 #define CPU_PWR_CTL			0x4
15 #define APC_PWR_GATE_CTL		0x14
16 
17 #define CPU_PWR_CTL_CLAMP		BIT_32(0)
18 #define CPU_PWR_CTL_CORE_MEM_CLAMP	BIT_32(1)
19 #define CPU_PWR_CTL_L1_RST_DIS		BIT_32(2)
20 #define CPU_PWR_CTL_CORE_MEM_HS		BIT_32(3)
21 #define CPU_PWR_CTL_CORE_RST		BIT_32(4)
22 #define CPU_PWR_CTL_COREPOR_RST		BIT_32(5)
23 #define CPU_PWR_CTL_GATE_CLK		BIT_32(6)
24 #define CPU_PWR_CTL_CORE_PWRD_UP	BIT_32(7)
25 
26 #define APC_PWR_GATE_CTL_GHDS_EN	BIT_32(0)
27 #define APC_PWR_GATE_CTL_GHDS_CNT(cnt)	((cnt) << 24)
28 
29 /* Boot a secondary CPU core for the first time. */
msm8916_cpu_boot(unsigned int core)30 void msm8916_cpu_boot(unsigned int core)
31 {
32 	uintptr_t acs = APCS_ALIAS_ACS(core);
33 	uint32_t pwr_ctl;
34 
35 	pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP |
36 		  CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST;
37 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
38 	dsb();
39 
40 	mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN |
41 		      APC_PWR_GATE_CTL_GHDS_CNT(16));
42 	dsb();
43 	udelay(2);
44 
45 	pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP;
46 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
47 	dsb();
48 
49 	pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS;
50 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
51 	dsb();
52 	udelay(2);
53 
54 	pwr_ctl &= ~CPU_PWR_CTL_CLAMP;
55 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
56 	dsb();
57 	udelay(2);
58 
59 	pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST);
60 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
61 	dsb();
62 
63 	pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP;
64 	mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
65 	dsb();
66 }
67