1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include <nvif/push006c.h>
25
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/if0020.h>
29
30 #include "nouveau_drv.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_bo.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
35 #include "nouveau_abi16.h"
36 #include "nouveau_vmm.h"
37 #include "nouveau_svm.h"
38
39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
40 int nouveau_vram_pushbuf;
41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
42
43 static int
nouveau_channel_killed(struct nvif_event * event,void * repv,u32 repc)44 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc)
45 {
46 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill);
47 struct nouveau_cli *cli = (void *)chan->user.client;
48
49 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
50 atomic_set(&chan->killed, 1);
51 if (chan->fence)
52 nouveau_fence_context_kill(chan->fence, -ENODEV);
53
54 return NVIF_EVENT_DROP;
55 }
56
57 int
nouveau_channel_idle(struct nouveau_channel * chan)58 nouveau_channel_idle(struct nouveau_channel *chan)
59 {
60 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
61 struct nouveau_cli *cli = (void *)chan->user.client;
62 struct nouveau_fence *fence = NULL;
63 int ret;
64
65 ret = nouveau_fence_new(chan, false, &fence);
66 if (!ret) {
67 ret = nouveau_fence_wait(fence, false, false);
68 nouveau_fence_unref(&fence);
69 }
70
71 if (ret) {
72 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
73 chan->chid, nvxx_client(&cli->base)->name);
74 return ret;
75 }
76 }
77 return 0;
78 }
79
80 void
nouveau_channel_del(struct nouveau_channel ** pchan)81 nouveau_channel_del(struct nouveau_channel **pchan)
82 {
83 struct nouveau_channel *chan = *pchan;
84 if (chan) {
85 struct nouveau_cli *cli = (void *)chan->user.client;
86
87 if (chan->fence)
88 nouveau_fence(chan->drm)->context_del(chan);
89
90 if (cli)
91 nouveau_svmm_part(chan->vmm->svmm, chan->inst);
92
93 nvif_object_dtor(&chan->nvsw);
94 nvif_object_dtor(&chan->gart);
95 nvif_object_dtor(&chan->vram);
96 nvif_event_dtor(&chan->kill);
97 nvif_object_dtor(&chan->user);
98 nvif_mem_dtor(&chan->mem_userd);
99 nvif_object_dtor(&chan->push.ctxdma);
100 nouveau_vma_del(&chan->push.vma);
101 nouveau_bo_unmap(chan->push.buffer);
102 if (chan->push.buffer && chan->push.buffer->bo.pin_count)
103 nouveau_bo_unpin(chan->push.buffer);
104 nouveau_bo_ref(NULL, &chan->push.buffer);
105 kfree(chan);
106 }
107 *pchan = NULL;
108 }
109
110 static void
nouveau_channel_kick(struct nvif_push * push)111 nouveau_channel_kick(struct nvif_push *push)
112 {
113 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
114 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
115 FIRE_RING(chan);
116 chan->chan._push.bgn = chan->chan._push.cur;
117 }
118
119 static int
nouveau_channel_wait(struct nvif_push * push,u32 size)120 nouveau_channel_wait(struct nvif_push *push, u32 size)
121 {
122 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
123 int ret;
124 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
125 ret = RING_SPACE(chan, size);
126 if (ret == 0) {
127 chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr;
128 chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur;
129 chan->chan._push.cur = chan->chan._push.bgn;
130 chan->chan._push.end = chan->chan._push.bgn + size;
131 }
132 return ret;
133 }
134
135 static int
nouveau_channel_prep(struct nouveau_drm * drm,struct nvif_device * device,u32 size,struct nouveau_channel ** pchan)136 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
137 u32 size, struct nouveau_channel **pchan)
138 {
139 struct nouveau_cli *cli = (void *)device->object.client;
140 struct nv_dma_v0 args = {};
141 struct nouveau_channel *chan;
142 u32 target;
143 int ret;
144
145 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
146 if (!chan)
147 return -ENOMEM;
148
149 chan->device = device;
150 chan->drm = drm;
151 chan->vmm = cli->svm.cli ? &cli->svm : &cli->vmm;
152 atomic_set(&chan->killed, 0);
153
154 /* allocate memory for dma push buffer */
155 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
156 if (nouveau_vram_pushbuf)
157 target = NOUVEAU_GEM_DOMAIN_VRAM;
158
159 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
160 &chan->push.buffer);
161 if (ret == 0) {
162 ret = nouveau_bo_pin(chan->push.buffer, target, false);
163 if (ret == 0)
164 ret = nouveau_bo_map(chan->push.buffer);
165 }
166
167 if (ret) {
168 nouveau_channel_del(pchan);
169 return ret;
170 }
171
172 chan->chan._push.mem.object.parent = cli->base.object.parent;
173 chan->chan._push.mem.object.client = &cli->base;
174 chan->chan._push.mem.object.name = "chanPush";
175 chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
176 chan->chan._push.wait = nouveau_channel_wait;
177 chan->chan._push.kick = nouveau_channel_kick;
178 chan->chan.push = &chan->chan._push;
179
180 /* create dma object covering the *entire* memory space that the
181 * pushbuf lives in, this is because the GEM code requires that
182 * we be able to call out to other (indirect) push buffers
183 */
184 chan->push.addr = chan->push.buffer->offset;
185
186 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
187 ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
188 &chan->push.vma);
189 if (ret) {
190 nouveau_channel_del(pchan);
191 return ret;
192 }
193
194 chan->push.addr = chan->push.vma->addr;
195
196 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI)
197 return 0;
198
199 args.target = NV_DMA_V0_TARGET_VM;
200 args.access = NV_DMA_V0_ACCESS_VM;
201 args.start = 0;
202 args.limit = chan->vmm->vmm.limit - 1;
203 } else
204 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) {
205 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
206 /* nv04 vram pushbuf hack, retarget to its location in
207 * the framebuffer bar rather than direct vram access..
208 * nfi why this exists, it came from the -nv ddx.
209 */
210 args.target = NV_DMA_V0_TARGET_PCI;
211 args.access = NV_DMA_V0_ACCESS_RDWR;
212 args.start = nvxx_device(device)->func->
213 resource_addr(nvxx_device(device), 1);
214 args.limit = args.start + device->info.ram_user - 1;
215 } else {
216 args.target = NV_DMA_V0_TARGET_VRAM;
217 args.access = NV_DMA_V0_ACCESS_RDWR;
218 args.start = 0;
219 args.limit = device->info.ram_user - 1;
220 }
221 } else {
222 if (chan->drm->agp.bridge) {
223 args.target = NV_DMA_V0_TARGET_AGP;
224 args.access = NV_DMA_V0_ACCESS_RDWR;
225 args.start = chan->drm->agp.base;
226 args.limit = chan->drm->agp.base +
227 chan->drm->agp.size - 1;
228 } else {
229 args.target = NV_DMA_V0_TARGET_VM;
230 args.access = NV_DMA_V0_ACCESS_RDWR;
231 args.start = 0;
232 args.limit = chan->vmm->vmm.limit - 1;
233 }
234 }
235
236 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
237 NV_DMA_FROM_MEMORY, &args, sizeof(args),
238 &chan->push.ctxdma);
239 if (ret) {
240 nouveau_channel_del(pchan);
241 return ret;
242 }
243
244 return 0;
245 }
246
247 static int
nouveau_channel_ctor(struct nouveau_drm * drm,struct nvif_device * device,bool priv,u64 runm,struct nouveau_channel ** pchan)248 nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool priv, u64 runm,
249 struct nouveau_channel **pchan)
250 {
251 static const struct {
252 s32 oclass;
253 int version;
254 } hosts[] = {
255 { AMPERE_CHANNEL_GPFIFO_B, 0 },
256 { AMPERE_CHANNEL_GPFIFO_A, 0 },
257 { TURING_CHANNEL_GPFIFO_A, 0 },
258 { VOLTA_CHANNEL_GPFIFO_A, 0 },
259 { PASCAL_CHANNEL_GPFIFO_A, 0 },
260 { MAXWELL_CHANNEL_GPFIFO_A, 0 },
261 { KEPLER_CHANNEL_GPFIFO_B, 0 },
262 { KEPLER_CHANNEL_GPFIFO_A, 0 },
263 { FERMI_CHANNEL_GPFIFO , 0 },
264 { G82_CHANNEL_GPFIFO , 0 },
265 { NV50_CHANNEL_GPFIFO , 0 },
266 { NV40_CHANNEL_DMA , 0 },
267 { NV17_CHANNEL_DMA , 0 },
268 { NV10_CHANNEL_DMA , 0 },
269 { NV03_CHANNEL_DMA , 0 },
270 {}
271 };
272 struct {
273 struct nvif_chan_v0 chan;
274 char name[TASK_COMM_LEN+16];
275 } args;
276 struct nouveau_cli *cli = (void *)device->object.client;
277 struct nouveau_channel *chan;
278 const u64 plength = 0x10000;
279 const u64 ioffset = plength;
280 const u64 ilength = 0x02000;
281 char name[TASK_COMM_LEN];
282 int cid, ret;
283 u64 size;
284
285 cid = nvif_mclass(&device->object, hosts);
286 if (cid < 0)
287 return cid;
288
289 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO)
290 size = plength;
291 else
292 size = ioffset + ilength;
293
294 /* allocate dma push buffer */
295 ret = nouveau_channel_prep(drm, device, size, &chan);
296 *pchan = chan;
297 if (ret)
298 return ret;
299
300 /* create channel object */
301 args.chan.version = 0;
302 args.chan.namelen = sizeof(args.name);
303 args.chan.runlist = __ffs64(runm);
304 args.chan.runq = 0;
305 args.chan.priv = priv;
306 args.chan.devm = BIT(0);
307 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) {
308 args.chan.vmm = 0;
309 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
310 args.chan.offset = chan->push.addr;
311 args.chan.length = 0;
312 } else {
313 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object);
314 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO)
315 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma);
316 else
317 args.chan.ctxdma = 0;
318 args.chan.offset = ioffset + chan->push.addr;
319 args.chan.length = ilength;
320 }
321 args.chan.huserd = 0;
322 args.chan.ouserd = 0;
323
324 /* allocate userd */
325 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) {
326 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100,
327 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE,
328 0, PAGE_SIZE, NULL, 0, &chan->mem_userd);
329 if (ret)
330 return ret;
331
332 args.chan.huserd = nvif_handle(&chan->mem_userd.object);
333 args.chan.ouserd = 0;
334
335 chan->userd = &chan->mem_userd.object;
336 } else {
337 chan->userd = &chan->user;
338 }
339
340 get_task_comm(name, current);
341 snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current));
342
343 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass,
344 &args, sizeof(args), &chan->user);
345 if (ret) {
346 nouveau_channel_del(pchan);
347 return ret;
348 }
349
350 chan->runlist = args.chan.runlist;
351 chan->chid = args.chan.chid;
352 chan->inst = args.chan.inst;
353 chan->token = args.chan.token;
354 return 0;
355 }
356
357 static int
nouveau_channel_init(struct nouveau_channel * chan,u32 vram,u32 gart)358 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
359 {
360 struct nvif_device *device = chan->device;
361 struct nouveau_drm *drm = chan->drm;
362 struct nv_dma_v0 args = {};
363 int ret, i;
364
365 ret = nvif_object_map(chan->userd, NULL, 0);
366 if (ret)
367 return ret;
368
369 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
370 struct {
371 struct nvif_event_v0 base;
372 struct nvif_chan_event_v0 host;
373 } args;
374
375 args.host.version = 0;
376 args.host.type = NVIF_CHAN_EVENT_V0_KILLED;
377
378 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid,
379 nouveau_channel_killed, false,
380 &args.base, sizeof(args), &chan->kill);
381 if (ret == 0)
382 ret = nvif_event_allow(&chan->kill);
383 if (ret) {
384 NV_ERROR(drm, "Failed to request channel kill "
385 "notification: %d\n", ret);
386 return ret;
387 }
388 }
389
390 /* allocate dma objects to cover all allowed vram, and gart */
391 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
392 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
393 args.target = NV_DMA_V0_TARGET_VM;
394 args.access = NV_DMA_V0_ACCESS_VM;
395 args.start = 0;
396 args.limit = chan->vmm->vmm.limit - 1;
397 } else {
398 args.target = NV_DMA_V0_TARGET_VRAM;
399 args.access = NV_DMA_V0_ACCESS_RDWR;
400 args.start = 0;
401 args.limit = device->info.ram_user - 1;
402 }
403
404 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
405 NV_DMA_IN_MEMORY, &args, sizeof(args),
406 &chan->vram);
407 if (ret)
408 return ret;
409
410 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
411 args.target = NV_DMA_V0_TARGET_VM;
412 args.access = NV_DMA_V0_ACCESS_VM;
413 args.start = 0;
414 args.limit = chan->vmm->vmm.limit - 1;
415 } else
416 if (chan->drm->agp.bridge) {
417 args.target = NV_DMA_V0_TARGET_AGP;
418 args.access = NV_DMA_V0_ACCESS_RDWR;
419 args.start = chan->drm->agp.base;
420 args.limit = chan->drm->agp.base +
421 chan->drm->agp.size - 1;
422 } else {
423 args.target = NV_DMA_V0_TARGET_VM;
424 args.access = NV_DMA_V0_ACCESS_RDWR;
425 args.start = 0;
426 args.limit = chan->vmm->vmm.limit - 1;
427 }
428
429 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
430 NV_DMA_IN_MEMORY, &args, sizeof(args),
431 &chan->gart);
432 if (ret)
433 return ret;
434 }
435
436 /* initialise dma tracking parameters */
437 switch (chan->user.oclass & 0x00ff) {
438 case 0x006b:
439 case 0x006e:
440 chan->user_put = 0x40;
441 chan->user_get = 0x44;
442 chan->dma.max = (0x10000 / 4) - 2;
443 break;
444 default:
445 chan->user_put = 0x40;
446 chan->user_get = 0x44;
447 chan->user_get_hi = 0x60;
448 chan->dma.ib_base = 0x10000 / 4;
449 chan->dma.ib_max = (0x02000 / 8) - 1;
450 chan->dma.ib_put = 0;
451 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
452 chan->dma.max = chan->dma.ib_base;
453 break;
454 }
455
456 chan->dma.put = 0;
457 chan->dma.cur = chan->dma.put;
458 chan->dma.free = chan->dma.max - chan->dma.cur;
459
460 ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS);
461 if (ret)
462 return ret;
463
464 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
465 PUSH_DATA(chan->chan.push, 0x00000000);
466
467 /* allocate software object class (used for fences on <= nv05) */
468 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
469 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
470 NVIF_CLASS_SW_NV04,
471 NULL, 0, &chan->nvsw);
472 if (ret)
473 return ret;
474
475 ret = PUSH_WAIT(chan->chan.push, 2);
476 if (ret)
477 return ret;
478
479 PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
480 PUSH_KICK(chan->chan.push);
481 }
482
483 /* initialise synchronisation */
484 return nouveau_fence(chan->drm)->context_new(chan);
485 }
486
487 int
nouveau_channel_new(struct nouveau_drm * drm,struct nvif_device * device,bool priv,u64 runm,u32 vram,u32 gart,struct nouveau_channel ** pchan)488 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
489 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan)
490 {
491 struct nouveau_cli *cli = (void *)device->object.client;
492 int ret;
493
494 ret = nouveau_channel_ctor(drm, device, priv, runm, pchan);
495 if (ret) {
496 NV_PRINTK(dbg, cli, "channel create, %d\n", ret);
497 return ret;
498 }
499
500 ret = nouveau_channel_init(*pchan, vram, gart);
501 if (ret) {
502 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
503 nouveau_channel_del(pchan);
504 return ret;
505 }
506
507 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
508 if (ret)
509 nouveau_channel_del(pchan);
510
511 return ret;
512 }
513
514 void
nouveau_channels_fini(struct nouveau_drm * drm)515 nouveau_channels_fini(struct nouveau_drm *drm)
516 {
517 kfree(drm->runl);
518 }
519
520 int
nouveau_channels_init(struct nouveau_drm * drm)521 nouveau_channels_init(struct nouveau_drm *drm)
522 {
523 struct {
524 struct nv_device_info_v1 m;
525 struct {
526 struct nv_device_info_v1_data channels;
527 struct nv_device_info_v1_data runlists;
528 } v;
529 } args = {
530 .m.version = 1,
531 .m.count = sizeof(args.v) / sizeof(args.v.channels),
532 .v.channels.mthd = NV_DEVICE_HOST_CHANNELS,
533 .v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS,
534 };
535 struct nvif_object *device = &drm->client.device.object;
536 int ret, i;
537
538 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
539 if (ret ||
540 args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data ||
541 args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
542 return -ENODEV;
543
544 drm->chan_nr = drm->chan_total = args.v.channels.data;
545 drm->runl_nr = fls64(args.v.runlists.data);
546 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL);
547 if (!drm->runl)
548 return -ENOMEM;
549
550 if (drm->chan_nr == 0) {
551 for (i = 0; i < drm->runl_nr; i++) {
552 if (!(args.v.runlists.data & BIT(i)))
553 continue;
554
555 args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS;
556 args.v.channels.data = i;
557
558 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
559 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
560 return -ENODEV;
561
562 drm->runl[i].chan_nr = args.v.channels.data;
563 drm->runl[i].chan_id_base = drm->chan_total;
564 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr);
565
566 drm->chan_total += drm->runl[i].chan_nr;
567 }
568 } else {
569 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr);
570 for (i = 1; i < drm->runl_nr; i++)
571 drm->runl[i].context_base = drm->runl[0].context_base;
572
573 }
574
575 return 0;
576 }
577