1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/display/drm_dsc_helper.h>
27
28 #include "reg_helper.h"
29 #include "dcn20_dsc.h"
30 #include "dsc/dscc_types.h"
31 #include "dsc/rc_calc.h"
32
33 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
34 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
35 struct dsc_optc_config *dsc_optc_cfg);
36 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
37 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
38 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
39 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple);
40 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth);
41
42 /* Object I/F functions */
43 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
44 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
45 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
46 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
47 struct dsc_optc_config *dsc_optc_cfg);
48 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
49 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
50 static void dsc2_disable(struct display_stream_compressor *dsc);
51 static void dsc2_disconnect(struct display_stream_compressor *dsc);
52
53 const struct dsc_funcs dcn20_dsc_funcs = {
54 .dsc_get_enc_caps = dsc2_get_enc_caps,
55 .dsc_read_state = dsc2_read_state,
56 .dsc_validate_stream = dsc2_validate_stream,
57 .dsc_set_config = dsc2_set_config,
58 .dsc_get_packed_pps = dsc2_get_packed_pps,
59 .dsc_enable = dsc2_enable,
60 .dsc_disable = dsc2_disable,
61 .dsc_disconnect = dsc2_disconnect,
62 };
63
64 /* Macro definitios for REG_SET macros*/
65 #define CTX \
66 dsc20->base.ctx
67
68 #define REG(reg)\
69 dsc20->dsc_regs->reg
70
71 #undef FN
72 #define FN(reg_name, field_name) \
73 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
74 #define DC_LOGGER \
75 dsc->ctx->logger
76
77 enum dsc_bits_per_comp {
78 DSC_BPC_8 = 8,
79 DSC_BPC_10 = 10,
80 DSC_BPC_12 = 12,
81 DSC_BPC_UNKNOWN
82 };
83
84 /* API functions (external or via structure->function_pointer) */
85
dsc2_construct(struct dcn20_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn20_dsc_registers * dsc_regs,const struct dcn20_dsc_shift * dsc_shift,const struct dcn20_dsc_mask * dsc_mask)86 void dsc2_construct(struct dcn20_dsc *dsc,
87 struct dc_context *ctx,
88 int inst,
89 const struct dcn20_dsc_registers *dsc_regs,
90 const struct dcn20_dsc_shift *dsc_shift,
91 const struct dcn20_dsc_mask *dsc_mask)
92 {
93 dsc->base.ctx = ctx;
94 dsc->base.inst = inst;
95 dsc->base.funcs = &dcn20_dsc_funcs;
96
97 dsc->dsc_regs = dsc_regs;
98 dsc->dsc_shift = dsc_shift;
99 dsc->dsc_mask = dsc_mask;
100
101 dsc->max_image_width = 5184;
102 }
103
104
105 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188
106 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200
107
108 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
109 * can be doubled, tripled etc. by using additional DSC engines.
110 */
dsc2_get_enc_caps(struct dsc_enc_caps * dsc_enc_caps,int pixel_clock_100Hz)111 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
112 {
113 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
114
115 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
116 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
117 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
118 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
119
120 dsc_enc_caps->lb_bit_depth = 13;
121 dsc_enc_caps->is_block_pred_supported = true;
122
123 dsc_enc_caps->color_formats.bits.RGB = 1;
124 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
125 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
126 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
127 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
128
129 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
130 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
131 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
132
133 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
134 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
135 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
136 * be sufficient to process the input pixel rate fed into a single DSC engine.
137 */
138 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
139
140 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
141 * throughput and number of slices, but also introduces a lower limit of 2 slices
142 */
143 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
144 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
145 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
146 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
147 }
148
149 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM.
150 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
151 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
152 }
153
154
155 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
156 * into a dcn_dsc_state struct.
157 */
dsc2_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)158 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
159 {
160 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
161
162 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
163 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
164 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
165 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
166 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
167 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
168 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
169 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
170 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
171 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
172 }
173
174
dsc2_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)175 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
176 {
177 struct dsc_optc_config dsc_optc_cfg;
178 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
179
180 if (dsc_cfg->pic_width > dsc20->max_image_width)
181 return false;
182
183 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
184 }
185
186
dsc_config_log(struct display_stream_compressor * dsc,const struct dsc_config * config)187 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
188 {
189 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
190 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
191 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
192 config->dc_dsc_cfg.bits_per_pixel,
193 config->dc_dsc_cfg.bits_per_pixel / 16,
194 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
195 DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
196 }
197
dsc2_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)198 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
199 struct dsc_optc_config *dsc_optc_cfg)
200 {
201 bool is_config_ok;
202 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
203
204 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
205 dsc_config_log(dsc, dsc_cfg);
206 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
207 ASSERT(is_config_ok);
208 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
209 dsc_log_pps(dsc, &dsc20->reg_vals.pps);
210 dsc_write_to_registers(dsc, &dsc20->reg_vals);
211 }
212
213
dsc2_get_packed_pps(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,uint8_t * dsc_packed_pps)214 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
215 {
216 bool is_config_ok;
217 struct dsc_reg_values dsc_reg_vals;
218 struct dsc_optc_config dsc_optc_cfg;
219
220 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
221 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
222
223 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
224 dsc_config_log(dsc, dsc_cfg);
225 DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
226 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
227 ASSERT(is_config_ok);
228 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
229 dsc_log_pps(dsc, &dsc_reg_vals.pps);
230
231 return is_config_ok;
232 }
233
234
dsc2_enable(struct display_stream_compressor * dsc,int opp_pipe)235 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
236 {
237 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
238 int dsc_clock_en;
239 int dsc_fw_config;
240 int enabled_opp_pipe;
241
242 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
243
244 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
245 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
246 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
247 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
248 ASSERT(0);
249 }
250
251 REG_UPDATE(DSC_TOP_CONTROL,
252 DSC_CLOCK_EN, 1);
253
254 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
255 DSCRM_DSC_FORWARD_EN, 1,
256 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
257 }
258
259
dsc2_disable(struct display_stream_compressor * dsc)260 static void dsc2_disable(struct display_stream_compressor *dsc)
261 {
262 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
263 int dsc_clock_en;
264 int dsc_fw_config;
265 int enabled_opp_pipe;
266
267 DC_LOG_DSC("disable DSC %d", dsc->inst);
268
269 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
270 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
271 if (!dsc_clock_en || !dsc_fw_config) {
272 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe);
273 ASSERT(0);
274 }
275
276 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
277 DSCRM_DSC_FORWARD_EN, 0);
278
279 REG_UPDATE(DSC_TOP_CONTROL,
280 DSC_CLOCK_EN, 0);
281 }
282
dsc2_disconnect(struct display_stream_compressor * dsc)283 static void dsc2_disconnect(struct display_stream_compressor *dsc)
284 {
285 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
286
287 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
288
289 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
290 DSCRM_DSC_FORWARD_EN, 0);
291 }
292
293 /* This module's internal functions */
dsc_log_pps(struct display_stream_compressor * dsc,struct drm_dsc_config * pps)294 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
295 {
296 int i;
297 int bits_per_pixel = pps->bits_per_pixel;
298
299 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
300 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
301 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
302 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
303 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
304 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
305 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
306 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
307 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
308 DC_LOG_DSC("\tpic_height %d", pps->pic_height);
309 DC_LOG_DSC("\tpic_width %d", pps->pic_width);
310 DC_LOG_DSC("\tslice_height %d", pps->slice_height);
311 DC_LOG_DSC("\tslice_width %d", pps->slice_width);
312 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
313 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
314 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
315 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
316 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
317 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
318 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
319 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
320 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
321 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
322 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
323 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
324 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
325 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
326 DC_LOG_DSC("\tnative_420 %d", pps->native_420);
327 DC_LOG_DSC("\tnative_422 %d", pps->native_422);
328 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
329 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
330 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
331 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
332 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
333 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
334 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
335 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
336 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
337
338 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
339 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
340
341 for (i = 0; i < NUM_BUF_RANGES; i++) {
342 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
343 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
344 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
345 }
346 }
347
dsc_override_rc_params(struct rc_params * rc,const struct dc_dsc_rc_params_override * override)348 static void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override)
349 {
350 uint8_t i;
351
352 rc->rc_model_size = override->rc_model_size;
353 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++)
354 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i];
355 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) {
356 rc->qp_min[i] = override->rc_minqp[i];
357 rc->qp_max[i] = override->rc_maxqp[i];
358 rc->ofs[i] = override->rc_offset[i];
359 }
360
361 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi;
362 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo;
363 rc->rc_edge_factor = override->rc_edge_factor;
364 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0;
365 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1;
366
367 rc->initial_fullness_offset = override->initial_fullness_offset;
368 rc->initial_xmit_delay = override->initial_delay;
369
370 rc->flatness_min_qp = override->flatness_min_qp;
371 rc->flatness_max_qp = override->flatness_max_qp;
372 rc->flatness_det_thresh = override->flatness_det_thresh;
373 }
374
dsc_prepare_config(const struct dsc_config * dsc_cfg,struct dsc_reg_values * dsc_reg_vals,struct dsc_optc_config * dsc_optc_cfg)375 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
376 struct dsc_optc_config *dsc_optc_cfg)
377 {
378 struct dsc_parameters dsc_params;
379 struct rc_params rc;
380
381 /* Validate input parameters */
382 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
383 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
384 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
385 ASSERT(dsc_cfg->pic_width);
386 ASSERT(dsc_cfg->pic_height);
387 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
388 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
389 (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
390 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
391 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
392 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
393
394 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
395 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
396 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
397 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
398 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
399 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
400 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
401 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
402 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
403 dm_output_to_console("%s: Invalid parameters\n", __func__);
404 return false;
405 }
406
407 dsc_init_reg_values(dsc_reg_vals);
408
409 /* Copy input config */
410 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
411 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
412 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
413 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
414 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
415 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
416 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
417 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
418 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
419 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
420 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
421
422 // TODO: in addition to validating slice height (pic height must be divisible by slice height),
423 // see what happens when the same condition doesn't apply for slice_width/pic_width.
424 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
425 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
426
427 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
428 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
429 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
430 return false;
431 }
432
433 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
434 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
435 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
436 else
437 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
438
439 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
440 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
441 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
442 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
443
444 calc_rc_params(&rc, &dsc_reg_vals->pps);
445
446 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd)
447 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd);
448
449 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {
450 dm_output_to_console("%s: DSC config failed\n", __func__);
451 return false;
452 }
453
454 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
455
456 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
457 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
458 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
459 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
460 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
461
462 return true;
463 }
464
465
dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc,bool is_ycbcr422_simple)466 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
467 {
468 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
469
470 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
471
472 switch (dc_pix_enc) {
473 case PIXEL_ENCODING_RGB:
474 dsc_pix_fmt = DSC_PIXFMT_RGB;
475 break;
476 case PIXEL_ENCODING_YCBCR422:
477 if (is_ycbcr422_simple)
478 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
479 else
480 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
481 break;
482 case PIXEL_ENCODING_YCBCR444:
483 dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
484 break;
485 case PIXEL_ENCODING_YCBCR420:
486 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
487 break;
488 default:
489 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
490 break;
491 }
492
493 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
494 return dsc_pix_fmt;
495 }
496
497
dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)498 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
499 {
500 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
501
502 switch (dc_color_depth) {
503 case COLOR_DEPTH_888:
504 bpc = DSC_BPC_8;
505 break;
506 case COLOR_DEPTH_101010:
507 bpc = DSC_BPC_10;
508 break;
509 case COLOR_DEPTH_121212:
510 bpc = DSC_BPC_12;
511 break;
512 default:
513 bpc = DSC_BPC_UNKNOWN;
514 break;
515 }
516
517 return bpc;
518 }
519
520
dsc_init_reg_values(struct dsc_reg_values * reg_vals)521 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
522 {
523 int i;
524
525 memset(reg_vals, 0, sizeof(struct dsc_reg_values));
526
527 /* Non-PPS values */
528 reg_vals->dsc_clock_enable = 1;
529 reg_vals->dsc_clock_gating_disable = 0;
530 reg_vals->underflow_recovery_en = 0;
531 reg_vals->underflow_occurred_int_en = 0;
532 reg_vals->underflow_occurred_status = 0;
533 reg_vals->ich_reset_at_eol = 0;
534 reg_vals->alternate_ich_encoding_en = 0;
535 reg_vals->rc_buffer_model_size = 0;
536 /*reg_vals->disable_ich = 0;*/
537 reg_vals->dsc_dbg_en = 0;
538
539 for (i = 0; i < 4; i++)
540 reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
541
542 /* PPS values */
543 reg_vals->pps.dsc_version_minor = 2;
544 reg_vals->pps.dsc_version_major = 1;
545 reg_vals->pps.line_buf_depth = 9;
546 reg_vals->pps.bits_per_component = 8;
547 reg_vals->pps.block_pred_enable = 1;
548 reg_vals->pps.slice_chunk_size = 0;
549 reg_vals->pps.pic_width = 0;
550 reg_vals->pps.pic_height = 0;
551 reg_vals->pps.slice_width = 0;
552 reg_vals->pps.slice_height = 0;
553 reg_vals->pps.initial_xmit_delay = 170;
554 reg_vals->pps.initial_dec_delay = 0;
555 reg_vals->pps.initial_scale_value = 0;
556 reg_vals->pps.scale_increment_interval = 0;
557 reg_vals->pps.scale_decrement_interval = 0;
558 reg_vals->pps.nfl_bpg_offset = 0;
559 reg_vals->pps.slice_bpg_offset = 0;
560 reg_vals->pps.nsl_bpg_offset = 0;
561 reg_vals->pps.initial_offset = 6144;
562 reg_vals->pps.final_offset = 0;
563 reg_vals->pps.flatness_min_qp = 3;
564 reg_vals->pps.flatness_max_qp = 12;
565 reg_vals->pps.rc_model_size = 8192;
566 reg_vals->pps.rc_edge_factor = 6;
567 reg_vals->pps.rc_quant_incr_limit0 = 11;
568 reg_vals->pps.rc_quant_incr_limit1 = 11;
569 reg_vals->pps.rc_tgt_offset_low = 3;
570 reg_vals->pps.rc_tgt_offset_high = 3;
571 }
572
573 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
574 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
575 * affects non-PPS register values.
576 */
dsc_update_from_dsc_parameters(struct dsc_reg_values * reg_vals,const struct dsc_parameters * dsc_params)577 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
578 {
579 int i;
580
581 reg_vals->pps = dsc_params->pps;
582
583 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
584 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
585 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
586
587 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
588 }
589
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)590 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
591 {
592 uint32_t temp_int;
593 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
594
595 REG_SET(DSC_DEBUG_CONTROL, 0,
596 DSC_DBG_EN, reg_vals->dsc_dbg_en);
597
598 // dsccif registers
599 REG_SET_5(DSCCIF_CONFIG0, 0,
600 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
601 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
602 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
603 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
604 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
605
606 REG_SET_2(DSCCIF_CONFIG1, 0,
607 PIC_WIDTH, reg_vals->pps.pic_width,
608 PIC_HEIGHT, reg_vals->pps.pic_height);
609
610 // dscc registers
611 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
612 REG_SET_3(DSCC_CONFIG0, 0,
613 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
614 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
615 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
616 } else {
617 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
618 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
619 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
620 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
621 reg_vals->num_slices_v - 1);
622 }
623
624 REG_SET(DSCC_CONFIG1, 0,
625 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
626 /*REG_SET_2(DSCC_CONFIG1, 0,
627 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
628 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
629
630 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
631 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
632 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
633 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
634 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
635
636 REG_SET_3(DSCC_PPS_CONFIG0, 0,
637 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
638 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
639 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
640
641 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
642 temp_int = reg_vals->bpp_x32;
643 else
644 temp_int = reg_vals->bpp_x32 >> 1;
645
646 REG_SET_7(DSCC_PPS_CONFIG1, 0,
647 BITS_PER_PIXEL, temp_int,
648 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
649 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
650 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
651 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
652 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
653 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
654
655 REG_SET_2(DSCC_PPS_CONFIG2, 0,
656 PIC_WIDTH, reg_vals->pps.pic_width,
657 PIC_HEIGHT, reg_vals->pps.pic_height);
658
659 REG_SET_2(DSCC_PPS_CONFIG3, 0,
660 SLICE_WIDTH, reg_vals->pps.slice_width,
661 SLICE_HEIGHT, reg_vals->pps.slice_height);
662
663 REG_SET(DSCC_PPS_CONFIG4, 0,
664 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
665
666 REG_SET_2(DSCC_PPS_CONFIG5, 0,
667 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
668 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
669
670 REG_SET_3(DSCC_PPS_CONFIG6, 0,
671 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
672 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
673 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
674
675 REG_SET_2(DSCC_PPS_CONFIG7, 0,
676 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
677 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
678
679 REG_SET_2(DSCC_PPS_CONFIG8, 0,
680 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
681 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
682
683 REG_SET_2(DSCC_PPS_CONFIG9, 0,
684 INITIAL_OFFSET, reg_vals->pps.initial_offset,
685 FINAL_OFFSET, reg_vals->pps.final_offset);
686
687 REG_SET_3(DSCC_PPS_CONFIG10, 0,
688 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
689 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
690 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
691
692 REG_SET_5(DSCC_PPS_CONFIG11, 0,
693 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
694 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
695 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
696 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
697 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
698
699 REG_SET_4(DSCC_PPS_CONFIG12, 0,
700 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
701 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
702 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
703 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
704
705 REG_SET_4(DSCC_PPS_CONFIG13, 0,
706 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
707 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
708 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
709 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
710
711 REG_SET_4(DSCC_PPS_CONFIG14, 0,
712 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
713 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
714 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
715 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
716
717 REG_SET_5(DSCC_PPS_CONFIG15, 0,
718 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
719 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
720 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
721 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
722 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
723
724 REG_SET_6(DSCC_PPS_CONFIG16, 0,
725 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
726 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
727 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
728 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
729 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
730 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
731
732 REG_SET_6(DSCC_PPS_CONFIG17, 0,
733 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
734 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
735 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
736 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
737 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
738 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
739
740 REG_SET_6(DSCC_PPS_CONFIG18, 0,
741 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
742 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
743 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
744 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
745 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
746 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
747
748 REG_SET_6(DSCC_PPS_CONFIG19, 0,
749 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
750 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
751 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
752 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
753 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
754 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
755
756 REG_SET_6(DSCC_PPS_CONFIG20, 0,
757 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
758 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
759 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
760 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
761 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
762 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
763
764 REG_SET_6(DSCC_PPS_CONFIG21, 0,
765 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
766 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
767 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
768 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
769 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
770 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
771
772 REG_SET_6(DSCC_PPS_CONFIG22, 0,
773 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
774 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
775 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
776 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
777 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
778 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
779
780 }
781
782