1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
29 #include "dc.h"
30 #include "dc_trace.h"
31
32 #define REG(reg)\
33 optc1->tg_regs->reg
34
35 #define CTX \
36 optc1->base.ctx
37
38 #undef FN
39 #define FN(reg_name, field_name) \
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
41
42 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
43
44 /**
45 * apply_front_porch_workaround TODO FPGA still need?
46 *
47 * This is a workaround for a bug that has existed since R5xx and has not been
48 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
49 */
apply_front_porch_workaround(struct dc_crtc_timing * timing)50 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
51 {
52 if (timing->flags.INTERLACE == 1) {
53 if (timing->v_front_porch < 2)
54 timing->v_front_porch = 2;
55 } else {
56 if (timing->v_front_porch < 1)
57 timing->v_front_porch = 1;
58 }
59 }
60
optc1_program_global_sync(struct timing_generator * optc,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width)61 void optc1_program_global_sync(
62 struct timing_generator *optc,
63 int vready_offset,
64 int vstartup_start,
65 int vupdate_offset,
66 int vupdate_width)
67 {
68 struct optc *optc1 = DCN10TG_FROM_TG(optc);
69
70 optc1->vready_offset = vready_offset;
71 optc1->vstartup_start = vstartup_start;
72 optc1->vupdate_offset = vupdate_offset;
73 optc1->vupdate_width = vupdate_width;
74
75 if (optc1->vstartup_start == 0) {
76 BREAK_TO_DEBUGGER();
77 return;
78 }
79
80 REG_SET(OTG_VSTARTUP_PARAM, 0,
81 VSTARTUP_START, optc1->vstartup_start);
82
83 REG_SET_2(OTG_VUPDATE_PARAM, 0,
84 VUPDATE_OFFSET, optc1->vupdate_offset,
85 VUPDATE_WIDTH, optc1->vupdate_width);
86
87 REG_SET(OTG_VREADY_PARAM, 0,
88 VREADY_OFFSET, optc1->vready_offset);
89 }
90
optc1_disable_stereo(struct timing_generator * optc)91 static void optc1_disable_stereo(struct timing_generator *optc)
92 {
93 struct optc *optc1 = DCN10TG_FROM_TG(optc);
94
95 REG_SET(OTG_STEREO_CONTROL, 0,
96 OTG_STEREO_EN, 0);
97
98 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
99 OTG_3D_STRUCTURE_EN, 0,
100 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
101 }
102
optc1_setup_vertical_interrupt0(struct timing_generator * optc,uint32_t start_line,uint32_t end_line)103 void optc1_setup_vertical_interrupt0(
104 struct timing_generator *optc,
105 uint32_t start_line,
106 uint32_t end_line)
107 {
108 struct optc *optc1 = DCN10TG_FROM_TG(optc);
109
110 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
111 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
112 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
113 }
114
optc1_setup_vertical_interrupt1(struct timing_generator * optc,uint32_t start_line)115 void optc1_setup_vertical_interrupt1(
116 struct timing_generator *optc,
117 uint32_t start_line)
118 {
119 struct optc *optc1 = DCN10TG_FROM_TG(optc);
120
121 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
122 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
123 }
124
optc1_setup_vertical_interrupt2(struct timing_generator * optc,uint32_t start_line)125 void optc1_setup_vertical_interrupt2(
126 struct timing_generator *optc,
127 uint32_t start_line)
128 {
129 struct optc *optc1 = DCN10TG_FROM_TG(optc);
130
131 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
132 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
133 }
134
135 /**
136 * program_timing_generator used by mode timing set
137 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
138 * Including SYNC. Call BIOS command table to program Timings.
139 */
optc1_program_timing(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,const enum signal_type signal,bool use_vbios)140 void optc1_program_timing(
141 struct timing_generator *optc,
142 const struct dc_crtc_timing *dc_crtc_timing,
143 int vready_offset,
144 int vstartup_start,
145 int vupdate_offset,
146 int vupdate_width,
147 const enum signal_type signal,
148 bool use_vbios)
149 {
150 struct dc_crtc_timing patched_crtc_timing;
151 uint32_t asic_blank_end;
152 uint32_t asic_blank_start;
153 uint32_t v_total;
154 uint32_t v_sync_end;
155 uint32_t h_sync_polarity, v_sync_polarity;
156 uint32_t start_point = 0;
157 uint32_t field_num = 0;
158 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
159
160 struct optc *optc1 = DCN10TG_FROM_TG(optc);
161
162 optc1->signal = signal;
163 optc1->vready_offset = vready_offset;
164 optc1->vstartup_start = vstartup_start;
165 optc1->vupdate_offset = vupdate_offset;
166 optc1->vupdate_width = vupdate_width;
167 patched_crtc_timing = *dc_crtc_timing;
168 apply_front_porch_workaround(&patched_crtc_timing);
169 optc1->orginal_patched_timing = patched_crtc_timing;
170
171 /* Load horizontal timing */
172
173 /* CRTC_H_TOTAL = vesa.h_total - 1 */
174 REG_SET(OTG_H_TOTAL, 0,
175 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
176
177 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
178 REG_UPDATE_2(OTG_H_SYNC_A,
179 OTG_H_SYNC_A_START, 0,
180 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
181
182 /* blank_start = line end - front porch */
183 asic_blank_start = patched_crtc_timing.h_total -
184 patched_crtc_timing.h_front_porch;
185
186 /* blank_end = blank_start - active */
187 asic_blank_end = asic_blank_start -
188 patched_crtc_timing.h_border_right -
189 patched_crtc_timing.h_addressable -
190 patched_crtc_timing.h_border_left;
191
192 REG_UPDATE_2(OTG_H_BLANK_START_END,
193 OTG_H_BLANK_START, asic_blank_start,
194 OTG_H_BLANK_END, asic_blank_end);
195
196 /* h_sync polarity */
197 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
198 0 : 1;
199
200 REG_UPDATE(OTG_H_SYNC_A_CNTL,
201 OTG_H_SYNC_A_POL, h_sync_polarity);
202
203 v_total = patched_crtc_timing.v_total - 1;
204
205 REG_SET(OTG_V_TOTAL, 0,
206 OTG_V_TOTAL, v_total);
207
208 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
209 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
210 */
211 optc->funcs->set_vtotal_min_max(optc, v_total, v_total);
212
213 /* v_sync_start = 0, v_sync_end = v_sync_width */
214 v_sync_end = patched_crtc_timing.v_sync_width;
215
216 REG_UPDATE_2(OTG_V_SYNC_A,
217 OTG_V_SYNC_A_START, 0,
218 OTG_V_SYNC_A_END, v_sync_end);
219
220 /* blank_start = frame end - front porch */
221 asic_blank_start = patched_crtc_timing.v_total -
222 patched_crtc_timing.v_front_porch;
223
224 /* blank_end = blank_start - active */
225 asic_blank_end = asic_blank_start -
226 patched_crtc_timing.v_border_bottom -
227 patched_crtc_timing.v_addressable -
228 patched_crtc_timing.v_border_top;
229
230 REG_UPDATE_2(OTG_V_BLANK_START_END,
231 OTG_V_BLANK_START, asic_blank_start,
232 OTG_V_BLANK_END, asic_blank_end);
233
234 /* v_sync polarity */
235 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
236 0 : 1;
237
238 REG_UPDATE(OTG_V_SYNC_A_CNTL,
239 OTG_V_SYNC_A_POL, v_sync_polarity);
240
241 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
242 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
243 optc1->signal == SIGNAL_TYPE_EDP) {
244 start_point = 1;
245 if (patched_crtc_timing.flags.INTERLACE == 1)
246 field_num = 1;
247 }
248
249 /* Interlace */
250 if (REG(OTG_INTERLACE_CONTROL)) {
251 if (patched_crtc_timing.flags.INTERLACE == 1)
252 REG_UPDATE(OTG_INTERLACE_CONTROL,
253 OTG_INTERLACE_ENABLE, 1);
254 else
255 REG_UPDATE(OTG_INTERLACE_CONTROL,
256 OTG_INTERLACE_ENABLE, 0);
257 }
258
259 /* VTG enable set to 0 first VInit */
260 REG_UPDATE(CONTROL,
261 VTG0_ENABLE, 0);
262
263 /* original code is using VTG offset to address OTG reg, seems wrong */
264 REG_UPDATE_2(OTG_CONTROL,
265 OTG_START_POINT_CNTL, start_point,
266 OTG_FIELD_NUMBER_CNTL, field_num);
267
268 optc->funcs->program_global_sync(optc,
269 vready_offset,
270 vstartup_start,
271 vupdate_offset,
272 vupdate_width);
273
274 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
275
276 /* TODO
277 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
278 * program_horz_count_by_2
279 * for DVI 30bpp mode, 0 otherwise
280 * program_horz_count_by_2(optc, &patched_crtc_timing);
281 */
282
283 /* Enable stereo - only when we need to pack 3D frame. Other types
284 * of stereo handled in explicit call
285 */
286
287 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
288 h_div = H_TIMING_DIV_BY2;
289
290 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
291 uint32_t data_fmt = 0;
292
293 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
294 data_fmt = 1;
295 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
296 data_fmt = 2;
297
298 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
299 }
300
301 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
302 if (optc1->opp_count == 4)
303 h_div = H_TIMING_DIV_BY4;
304
305 REG_UPDATE(OTG_H_TIMING_CNTL,
306 OTG_H_TIMING_DIV_MODE, h_div);
307 } else {
308 REG_UPDATE(OTG_H_TIMING_CNTL,
309 OTG_H_TIMING_DIV_BY2, h_div);
310 }
311 }
312
313 /**
314 * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters
315 *
316 * @optc: timing_generator struct used to extract the optc parameters
317 * @dc_crtc_timing: Timing parameters configured
318 * @program_fp2: Boolean value indicating if FP2 will be programmed or not
319 *
320 * OTG is responsible for generating the global sync signals, including
321 * vertical timing information for each HUBP in the dcfclk domain. Each VTG is
322 * associated with one OTG that provides HUBP with vertical timing information
323 * (i.e., there is 1:1 correspondence between OTG and VTG). This function is
324 * responsible for setting the OTG parameters to the VTG during the pipe
325 * programming.
326 */
optc1_set_vtg_params(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,bool program_fp2)327 void optc1_set_vtg_params(struct timing_generator *optc,
328 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
329 {
330 struct dc_crtc_timing patched_crtc_timing;
331 uint32_t asic_blank_end;
332 uint32_t v_init;
333 uint32_t v_fp2 = 0;
334 int32_t vertical_line_start;
335
336 struct optc *optc1 = DCN10TG_FROM_TG(optc);
337
338 patched_crtc_timing = *dc_crtc_timing;
339 apply_front_porch_workaround(&patched_crtc_timing);
340
341 /* VCOUNT_INIT is the start of blank */
342 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
343
344 /* end of blank = v_init - active */
345 asic_blank_end = v_init -
346 patched_crtc_timing.v_border_bottom -
347 patched_crtc_timing.v_addressable -
348 patched_crtc_timing.v_border_top;
349
350 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
351 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
352 if (vertical_line_start < 0)
353 v_fp2 = -vertical_line_start;
354
355 /* Interlace */
356 if (REG(OTG_INTERLACE_CONTROL)) {
357 if (patched_crtc_timing.flags.INTERLACE == 1) {
358 v_init = v_init / 2;
359 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
360 v_fp2 = v_fp2 / 2;
361 }
362 }
363
364 if (program_fp2)
365 REG_UPDATE_2(CONTROL,
366 VTG0_FP2, v_fp2,
367 VTG0_VCOUNT_INIT, v_init);
368 else
369 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
370 }
371
optc1_set_blank_data_double_buffer(struct timing_generator * optc,bool enable)372 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
373 {
374 struct optc *optc1 = DCN10TG_FROM_TG(optc);
375
376 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
377
378 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
379 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
380 }
381
382 /**
383 * optc1_set_timing_double_buffer() - DRR double buffering control
384 *
385 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
386 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
387 *
388 * Options: any time, start of frame, dp start of frame (range timing)
389 */
optc1_set_timing_double_buffer(struct timing_generator * optc,bool enable)390 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
391 {
392 struct optc *optc1 = DCN10TG_FROM_TG(optc);
393 uint32_t mode = enable ? 2 : 0;
394
395 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
396 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
397 }
398
399 /**
400 * unblank_crtc
401 * Call ASIC Control Object to UnBlank CRTC.
402 */
optc1_unblank_crtc(struct timing_generator * optc)403 static void optc1_unblank_crtc(struct timing_generator *optc)
404 {
405 struct optc *optc1 = DCN10TG_FROM_TG(optc);
406
407 REG_UPDATE_2(OTG_BLANK_CONTROL,
408 OTG_BLANK_DATA_EN, 0,
409 OTG_BLANK_DE_MODE, 0);
410
411 /* W/A for automated testing
412 * Automated testing will fail underflow test as there
413 * sporadic underflows which occur during the optc blank
414 * sequence. As a w/a, clear underflow on unblank.
415 * This prevents the failure, but will not mask actual
416 * underflow that affect real use cases.
417 */
418 optc1_clear_optc_underflow(optc);
419 }
420
421 /**
422 * blank_crtc
423 * Call ASIC Control Object to Blank CRTC.
424 */
425
optc1_blank_crtc(struct timing_generator * optc)426 static void optc1_blank_crtc(struct timing_generator *optc)
427 {
428 struct optc *optc1 = DCN10TG_FROM_TG(optc);
429
430 REG_UPDATE_2(OTG_BLANK_CONTROL,
431 OTG_BLANK_DATA_EN, 1,
432 OTG_BLANK_DE_MODE, 0);
433
434 optc1_set_blank_data_double_buffer(optc, false);
435 }
436
optc1_set_blank(struct timing_generator * optc,bool enable_blanking)437 void optc1_set_blank(struct timing_generator *optc,
438 bool enable_blanking)
439 {
440 if (enable_blanking)
441 optc1_blank_crtc(optc);
442 else
443 optc1_unblank_crtc(optc);
444 }
445
optc1_is_blanked(struct timing_generator * optc)446 bool optc1_is_blanked(struct timing_generator *optc)
447 {
448 struct optc *optc1 = DCN10TG_FROM_TG(optc);
449 uint32_t blank_en;
450 uint32_t blank_state;
451
452 REG_GET_2(OTG_BLANK_CONTROL,
453 OTG_BLANK_DATA_EN, &blank_en,
454 OTG_CURRENT_BLANK_STATE, &blank_state);
455
456 return blank_en && blank_state;
457 }
458
optc1_enable_optc_clock(struct timing_generator * optc,bool enable)459 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
460 {
461 struct optc *optc1 = DCN10TG_FROM_TG(optc);
462
463 if (enable) {
464 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
465 OPTC_INPUT_CLK_EN, 1,
466 OPTC_INPUT_CLK_GATE_DIS, 1);
467
468 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
469 OPTC_INPUT_CLK_ON, 1,
470 1, 1000);
471
472 /* Enable clock */
473 REG_UPDATE_2(OTG_CLOCK_CONTROL,
474 OTG_CLOCK_EN, 1,
475 OTG_CLOCK_GATE_DIS, 1);
476 REG_WAIT(OTG_CLOCK_CONTROL,
477 OTG_CLOCK_ON, 1,
478 1, 1000);
479 } else {
480
481 //last chance to clear underflow, otherwise, it will always there due to clock is off.
482 if (optc->funcs->is_optc_underflow_occurred(optc) == true)
483 optc->funcs->clear_optc_underflow(optc);
484
485 REG_UPDATE_2(OTG_CLOCK_CONTROL,
486 OTG_CLOCK_GATE_DIS, 0,
487 OTG_CLOCK_EN, 0);
488
489 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
490 OPTC_INPUT_CLK_GATE_DIS, 0,
491 OPTC_INPUT_CLK_EN, 0);
492 }
493 }
494
495 /**
496 * Enable CRTC
497 * Enable CRTC - call ASIC Control Object to enable Timing generator.
498 */
optc1_enable_crtc(struct timing_generator * optc)499 static bool optc1_enable_crtc(struct timing_generator *optc)
500 {
501 /* TODO FPGA wait for answer
502 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
503 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
504 */
505 struct optc *optc1 = DCN10TG_FROM_TG(optc);
506
507 /* opp instance for OTG. For DCN1.0, ODM is remoed.
508 * OPP and OPTC should 1:1 mapping
509 */
510 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
511 OPTC_SRC_SEL, optc->inst);
512
513 /* VTG enable first is for HW workaround */
514 REG_UPDATE(CONTROL,
515 VTG0_ENABLE, 1);
516
517 REG_SEQ_START();
518
519 /* Enable CRTC */
520 REG_UPDATE_2(OTG_CONTROL,
521 OTG_DISABLE_POINT_CNTL, 3,
522 OTG_MASTER_EN, 1);
523
524 REG_SEQ_SUBMIT();
525 REG_SEQ_WAIT_DONE();
526
527 return true;
528 }
529
530 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
optc1_disable_crtc(struct timing_generator * optc)531 bool optc1_disable_crtc(struct timing_generator *optc)
532 {
533 struct optc *optc1 = DCN10TG_FROM_TG(optc);
534
535 /* disable otg request until end of the first line
536 * in the vertical blank region
537 */
538 REG_UPDATE_2(OTG_CONTROL,
539 OTG_DISABLE_POINT_CNTL, 3,
540 OTG_MASTER_EN, 0);
541
542 REG_UPDATE(CONTROL,
543 VTG0_ENABLE, 0);
544
545 /* CRTC disabled, so disable clock. */
546 REG_WAIT(OTG_CLOCK_CONTROL,
547 OTG_BUSY, 0,
548 1, 100000);
549
550 return true;
551 }
552
553
optc1_program_blank_color(struct timing_generator * optc,const struct tg_color * black_color)554 void optc1_program_blank_color(
555 struct timing_generator *optc,
556 const struct tg_color *black_color)
557 {
558 struct optc *optc1 = DCN10TG_FROM_TG(optc);
559
560 REG_SET_3(OTG_BLACK_COLOR, 0,
561 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
562 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
563 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
564 }
565
optc1_validate_timing(struct timing_generator * optc,const struct dc_crtc_timing * timing)566 bool optc1_validate_timing(
567 struct timing_generator *optc,
568 const struct dc_crtc_timing *timing)
569 {
570 uint32_t v_blank;
571 uint32_t h_blank;
572 uint32_t min_v_blank;
573 struct optc *optc1 = DCN10TG_FROM_TG(optc);
574
575 ASSERT(timing != NULL);
576
577 v_blank = (timing->v_total - timing->v_addressable -
578 timing->v_border_top - timing->v_border_bottom);
579
580 h_blank = (timing->h_total - timing->h_addressable -
581 timing->h_border_right -
582 timing->h_border_left);
583
584 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
585 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
586 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
587 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
588 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
589 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
590 return false;
591
592 /* Temporarily blocking interlacing mode until it's supported */
593 if (timing->flags.INTERLACE == 1)
594 return false;
595
596 /* Check maximum number of pixels supported by Timing Generator
597 * (Currently will never fail, in order to fail needs display which
598 * needs more than 8192 horizontal and
599 * more than 8192 vertical total pixels)
600 */
601 if (timing->h_total > optc1->max_h_total ||
602 timing->v_total > optc1->max_v_total)
603 return false;
604
605
606 if (h_blank < optc1->min_h_blank)
607 return false;
608
609 if (timing->h_sync_width < optc1->min_h_sync_width ||
610 timing->v_sync_width < optc1->min_v_sync_width)
611 return false;
612
613 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
614
615 if (v_blank < min_v_blank)
616 return false;
617
618 return true;
619
620 }
621
622 /*
623 * get_vblank_counter
624 *
625 * @brief
626 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
627 * holds the counter of frames.
628 *
629 * @param
630 * struct timing_generator *optc - [in] timing generator which controls the
631 * desired CRTC
632 *
633 * @return
634 * Counter of frames, which should equal to number of vblanks.
635 */
optc1_get_vblank_counter(struct timing_generator * optc)636 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
637 {
638 struct optc *optc1 = DCN10TG_FROM_TG(optc);
639 uint32_t frame_count;
640
641 REG_GET(OTG_STATUS_FRAME_COUNT,
642 OTG_FRAME_COUNT, &frame_count);
643
644 return frame_count;
645 }
646
optc1_lock(struct timing_generator * optc)647 void optc1_lock(struct timing_generator *optc)
648 {
649 struct optc *optc1 = DCN10TG_FROM_TG(optc);
650
651 REG_SET(OTG_GLOBAL_CONTROL0, 0,
652 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
653 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
654 OTG_MASTER_UPDATE_LOCK, 1);
655
656 /* Should be fast, status does not update on maximus */
657 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
658 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
659 UPDATE_LOCK_STATUS, 1,
660 1, 10);
661
662 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
663 }
664
optc1_unlock(struct timing_generator * optc)665 void optc1_unlock(struct timing_generator *optc)
666 {
667 struct optc *optc1 = DCN10TG_FROM_TG(optc);
668
669 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
670 OTG_MASTER_UPDATE_LOCK, 0);
671
672 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
673 }
674
optc1_get_position(struct timing_generator * optc,struct crtc_position * position)675 void optc1_get_position(struct timing_generator *optc,
676 struct crtc_position *position)
677 {
678 struct optc *optc1 = DCN10TG_FROM_TG(optc);
679
680 REG_GET_2(OTG_STATUS_POSITION,
681 OTG_HORZ_COUNT, &position->horizontal_count,
682 OTG_VERT_COUNT, &position->vertical_count);
683
684 REG_GET(OTG_NOM_VERT_POSITION,
685 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
686 }
687
optc1_is_counter_moving(struct timing_generator * optc)688 bool optc1_is_counter_moving(struct timing_generator *optc)
689 {
690 struct crtc_position position1, position2;
691
692 optc->funcs->get_position(optc, &position1);
693 optc->funcs->get_position(optc, &position2);
694
695 if (position1.horizontal_count == position2.horizontal_count &&
696 position1.vertical_count == position2.vertical_count)
697 return false;
698 else
699 return true;
700 }
701
optc1_did_triggered_reset_occur(struct timing_generator * optc)702 bool optc1_did_triggered_reset_occur(
703 struct timing_generator *optc)
704 {
705 struct optc *optc1 = DCN10TG_FROM_TG(optc);
706 uint32_t occurred_force, occurred_vsync;
707
708 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
709 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
710
711 REG_GET(OTG_VERT_SYNC_CONTROL,
712 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
713
714 return occurred_vsync != 0 || occurred_force != 0;
715 }
716
optc1_disable_reset_trigger(struct timing_generator * optc)717 void optc1_disable_reset_trigger(struct timing_generator *optc)
718 {
719 struct optc *optc1 = DCN10TG_FROM_TG(optc);
720
721 REG_WRITE(OTG_TRIGA_CNTL, 0);
722
723 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
724 OTG_FORCE_COUNT_NOW_CLEAR, 1);
725
726 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
727 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
728 }
729
optc1_enable_reset_trigger(struct timing_generator * optc,int source_tg_inst)730 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
731 {
732 struct optc *optc1 = DCN10TG_FROM_TG(optc);
733 uint32_t falling_edge;
734
735 REG_GET(OTG_V_SYNC_A_CNTL,
736 OTG_V_SYNC_A_POL, &falling_edge);
737
738 if (falling_edge)
739 REG_SET_3(OTG_TRIGA_CNTL, 0,
740 /* vsync signal from selected OTG pipe based
741 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
742 */
743 OTG_TRIGA_SOURCE_SELECT, 20,
744 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
745 /* always detect falling edge */
746 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
747 else
748 REG_SET_3(OTG_TRIGA_CNTL, 0,
749 /* vsync signal from selected OTG pipe based
750 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
751 */
752 OTG_TRIGA_SOURCE_SELECT, 20,
753 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
754 /* always detect rising edge */
755 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
756
757 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
758 /* force H count to H_TOTAL and V count to V_TOTAL in
759 * progressive mode and V_TOTAL-1 in interlaced mode
760 */
761 OTG_FORCE_COUNT_NOW_MODE, 2);
762 }
763
optc1_enable_crtc_reset(struct timing_generator * optc,int source_tg_inst,struct crtc_trigger_info * crtc_tp)764 void optc1_enable_crtc_reset(
765 struct timing_generator *optc,
766 int source_tg_inst,
767 struct crtc_trigger_info *crtc_tp)
768 {
769 struct optc *optc1 = DCN10TG_FROM_TG(optc);
770 uint32_t falling_edge = 0;
771 uint32_t rising_edge = 0;
772
773 switch (crtc_tp->event) {
774
775 case CRTC_EVENT_VSYNC_RISING:
776 rising_edge = 1;
777 break;
778
779 case CRTC_EVENT_VSYNC_FALLING:
780 falling_edge = 1;
781 break;
782 }
783
784 REG_SET_4(OTG_TRIGA_CNTL, 0,
785 /* vsync signal from selected OTG pipe based
786 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
787 */
788 OTG_TRIGA_SOURCE_SELECT, 20,
789 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
790 /* always detect falling edge */
791 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
792 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
793
794 switch (crtc_tp->delay) {
795 case TRIGGER_DELAY_NEXT_LINE:
796 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
797 OTG_AUTO_FORCE_VSYNC_MODE, 1);
798 break;
799 case TRIGGER_DELAY_NEXT_PIXEL:
800 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
801 /* force H count to H_TOTAL and V count to V_TOTAL in
802 * progressive mode and V_TOTAL-1 in interlaced mode
803 */
804 OTG_FORCE_COUNT_NOW_MODE, 2);
805 break;
806 }
807 }
808
optc1_wait_for_state(struct timing_generator * optc,enum crtc_state state)809 void optc1_wait_for_state(struct timing_generator *optc,
810 enum crtc_state state)
811 {
812 struct optc *optc1 = DCN10TG_FROM_TG(optc);
813
814 switch (state) {
815 case CRTC_STATE_VBLANK:
816 REG_WAIT(OTG_STATUS,
817 OTG_V_BLANK, 1,
818 1, 100000); /* 1 vupdate at 10hz */
819 break;
820
821 case CRTC_STATE_VACTIVE:
822 REG_WAIT(OTG_STATUS,
823 OTG_V_ACTIVE_DISP, 1,
824 1, 100000); /* 1 vupdate at 10hz */
825 break;
826
827 default:
828 break;
829 }
830 }
831
optc1_set_early_control(struct timing_generator * optc,uint32_t early_cntl)832 void optc1_set_early_control(
833 struct timing_generator *optc,
834 uint32_t early_cntl)
835 {
836 /* asic design change, do not need this control
837 * empty for share caller logic
838 */
839 }
840
841
optc1_set_static_screen_control(struct timing_generator * optc,uint32_t event_triggers,uint32_t num_frames)842 void optc1_set_static_screen_control(
843 struct timing_generator *optc,
844 uint32_t event_triggers,
845 uint32_t num_frames)
846 {
847 struct optc *optc1 = DCN10TG_FROM_TG(optc);
848
849 // By register spec, it only takes 8 bit value
850 if (num_frames > 0xFF)
851 num_frames = 0xFF;
852
853 /* Bit 8 is no longer applicable in RV for PSR case,
854 * set bit 8 to 0 if given
855 */
856 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
857 != 0)
858 event_triggers = event_triggers &
859 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
860
861 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
862 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
863 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
864 }
865
optc1_setup_manual_trigger(struct timing_generator * optc)866 static void optc1_setup_manual_trigger(struct timing_generator *optc)
867 {
868 struct optc *optc1 = DCN10TG_FROM_TG(optc);
869
870 REG_SET(OTG_GLOBAL_CONTROL2, 0,
871 MANUAL_FLOW_CONTROL_SEL, optc->inst);
872
873 REG_SET_8(OTG_TRIGA_CNTL, 0,
874 OTG_TRIGA_SOURCE_SELECT, 22,
875 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
876 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
877 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
878 OTG_TRIGA_POLARITY_SELECT, 0,
879 OTG_TRIGA_FREQUENCY_SELECT, 0,
880 OTG_TRIGA_DELAY, 0,
881 OTG_TRIGA_CLEAR, 1);
882 }
883
optc1_program_manual_trigger(struct timing_generator * optc)884 static void optc1_program_manual_trigger(struct timing_generator *optc)
885 {
886 struct optc *optc1 = DCN10TG_FROM_TG(optc);
887
888 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
889 MANUAL_FLOW_CONTROL, 1);
890
891 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
892 MANUAL_FLOW_CONTROL, 0);
893 }
894
895
896 /**
897 *****************************************************************************
898 * Function: set_drr
899 *
900 * @brief
901 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
902 *
903 *****************************************************************************
904 */
optc1_set_drr(struct timing_generator * optc,const struct drr_params * params)905 void optc1_set_drr(
906 struct timing_generator *optc,
907 const struct drr_params *params)
908 {
909 struct optc *optc1 = DCN10TG_FROM_TG(optc);
910
911 if (params != NULL &&
912 params->vertical_total_max > 0 &&
913 params->vertical_total_min > 0) {
914
915 if (params->vertical_total_mid != 0) {
916
917 REG_SET(OTG_V_TOTAL_MID, 0,
918 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
919
920 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
921 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
922 OTG_VTOTAL_MID_FRAME_NUM,
923 (uint8_t)params->vertical_total_mid_frame_num);
924
925 }
926
927 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
928
929 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
930 OTG_V_TOTAL_MIN_SEL, 1,
931 OTG_V_TOTAL_MAX_SEL, 1,
932 OTG_FORCE_LOCK_ON_EVENT, 0,
933 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
934 OTG_SET_V_TOTAL_MIN_MASK, 0);
935
936 // Setup manual flow control for EOF via TRIG_A
937 optc->funcs->setup_manual_trigger(optc);
938
939 } else {
940 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
941 OTG_SET_V_TOTAL_MIN_MASK, 0,
942 OTG_V_TOTAL_MIN_SEL, 0,
943 OTG_V_TOTAL_MAX_SEL, 0,
944 OTG_FORCE_LOCK_ON_EVENT, 0);
945
946 optc->funcs->set_vtotal_min_max(optc, 0, 0);
947 }
948 }
949
optc1_set_vtotal_min_max(struct timing_generator * optc,int vtotal_min,int vtotal_max)950 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
951 {
952 struct optc *optc1 = DCN10TG_FROM_TG(optc);
953
954 REG_SET(OTG_V_TOTAL_MAX, 0,
955 OTG_V_TOTAL_MAX, vtotal_max);
956
957 REG_SET(OTG_V_TOTAL_MIN, 0,
958 OTG_V_TOTAL_MIN, vtotal_min);
959 }
960
optc1_set_test_pattern(struct timing_generator * optc,enum controller_dp_test_pattern test_pattern,enum dc_color_depth color_depth)961 static void optc1_set_test_pattern(
962 struct timing_generator *optc,
963 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
964 * because this is not DP-specific (which is probably somewhere in DP
965 * encoder) */
966 enum controller_dp_test_pattern test_pattern,
967 enum dc_color_depth color_depth)
968 {
969 struct optc *optc1 = DCN10TG_FROM_TG(optc);
970 enum test_pattern_color_format bit_depth;
971 enum test_pattern_dyn_range dyn_range;
972 enum test_pattern_mode mode;
973 uint32_t pattern_mask;
974 uint32_t pattern_data;
975 /* color ramp generator mixes 16-bits color */
976 uint32_t src_bpc = 16;
977 /* requested bpc */
978 uint32_t dst_bpc;
979 uint32_t index;
980 /* RGB values of the color bars.
981 * Produce two RGB colors: RGB0 - white (all Fs)
982 * and RGB1 - black (all 0s)
983 * (three RGB components for two colors)
984 */
985 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
986 0x0000, 0x0000};
987 /* dest color (converted to the specified color format) */
988 uint16_t dst_color[6];
989 uint32_t inc_base;
990
991 /* translate to bit depth */
992 switch (color_depth) {
993 case COLOR_DEPTH_666:
994 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
995 break;
996 case COLOR_DEPTH_888:
997 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
998 break;
999 case COLOR_DEPTH_101010:
1000 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
1001 break;
1002 case COLOR_DEPTH_121212:
1003 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
1004 break;
1005 default:
1006 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1007 break;
1008 }
1009
1010 switch (test_pattern) {
1011 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
1012 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
1013 {
1014 dyn_range = (test_pattern ==
1015 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
1016 TEST_PATTERN_DYN_RANGE_CEA :
1017 TEST_PATTERN_DYN_RANGE_VESA);
1018 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
1019
1020 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
1021 OTG_TEST_PATTERN_VRES, 6,
1022 OTG_TEST_PATTERN_HRES, 6);
1023
1024 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1025 OTG_TEST_PATTERN_EN, 1,
1026 OTG_TEST_PATTERN_MODE, mode,
1027 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1028 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1029 }
1030 break;
1031
1032 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1033 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1034 {
1035 mode = (test_pattern ==
1036 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1037 TEST_PATTERN_MODE_VERTICALBARS :
1038 TEST_PATTERN_MODE_HORIZONTALBARS);
1039
1040 switch (bit_depth) {
1041 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1042 dst_bpc = 6;
1043 break;
1044 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1045 dst_bpc = 8;
1046 break;
1047 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1048 dst_bpc = 10;
1049 break;
1050 default:
1051 dst_bpc = 8;
1052 break;
1053 }
1054
1055 /* adjust color to the required colorFormat */
1056 for (index = 0; index < 6; index++) {
1057 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1058 * (srcBpc - dstBpc);
1059 */
1060 dst_color[index] =
1061 src_color[index] >> (src_bpc - dst_bpc);
1062 /* CRTC_TEST_PATTERN_DATA has 16 bits,
1063 * lowest 6 are hardwired to ZERO
1064 * color bits should be left aligned to MSB
1065 * XXXXXXXXXX000000 for 10 bit,
1066 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1067 */
1068 dst_color[index] <<= (16 - dst_bpc);
1069 }
1070
1071 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1072
1073 /* We have to write the mask before data, similar to pipeline.
1074 * For example, for 8 bpc, if we want RGB0 to be magenta,
1075 * and RGB1 to be cyan,
1076 * we need to make 7 writes:
1077 * MASK DATA
1078 * 000001 00000000 00000000 set mask to R0
1079 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
1080 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
1081 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
1082 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
1083 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
1084 * 100000 11111111 00000000 B1 255, 0xFF00
1085 *
1086 * we will make a loop of 6 in which we prepare the mask,
1087 * then write, then prepare the color for next write.
1088 * first iteration will write mask only,
1089 * but each next iteration color prepared in
1090 * previous iteration will be written within new mask,
1091 * the last component will written separately,
1092 * mask is not changing between 6th and 7th write
1093 * and color will be prepared by last iteration
1094 */
1095
1096 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1097 * is B1, G1, R1, B0, G0, R0
1098 */
1099 pattern_data = 0;
1100 for (index = 0; index < 6; index++) {
1101 /* prepare color mask, first write PATTERN_DATA
1102 * will have all zeros
1103 */
1104 pattern_mask = (1 << index);
1105
1106 /* write color component */
1107 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1108 OTG_TEST_PATTERN_MASK, pattern_mask,
1109 OTG_TEST_PATTERN_DATA, pattern_data);
1110
1111 /* prepare next color component,
1112 * will be written in the next iteration
1113 */
1114 pattern_data = dst_color[index];
1115 }
1116 /* write last color component,
1117 * it's been already prepared in the loop
1118 */
1119 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1120 OTG_TEST_PATTERN_MASK, pattern_mask,
1121 OTG_TEST_PATTERN_DATA, pattern_data);
1122
1123 /* enable test pattern */
1124 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1125 OTG_TEST_PATTERN_EN, 1,
1126 OTG_TEST_PATTERN_MODE, mode,
1127 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1128 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1129 }
1130 break;
1131
1132 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1133 {
1134 mode = (bit_depth ==
1135 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1136 TEST_PATTERN_MODE_DUALRAMP_RGB :
1137 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1138
1139 switch (bit_depth) {
1140 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1141 dst_bpc = 6;
1142 break;
1143 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1144 dst_bpc = 8;
1145 break;
1146 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1147 dst_bpc = 10;
1148 break;
1149 default:
1150 dst_bpc = 8;
1151 break;
1152 }
1153
1154 /* increment for the first ramp for one color gradation
1155 * 1 gradation for 6-bit color is 2^10
1156 * gradations in 16-bit color
1157 */
1158 inc_base = (src_bpc - dst_bpc);
1159
1160 switch (bit_depth) {
1161 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1162 {
1163 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1164 OTG_TEST_PATTERN_INC0, inc_base,
1165 OTG_TEST_PATTERN_INC1, 0,
1166 OTG_TEST_PATTERN_HRES, 6,
1167 OTG_TEST_PATTERN_VRES, 6,
1168 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1169 }
1170 break;
1171 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1172 {
1173 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1174 OTG_TEST_PATTERN_INC0, inc_base,
1175 OTG_TEST_PATTERN_INC1, 0,
1176 OTG_TEST_PATTERN_HRES, 8,
1177 OTG_TEST_PATTERN_VRES, 6,
1178 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1179 }
1180 break;
1181 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1182 {
1183 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1184 OTG_TEST_PATTERN_INC0, inc_base,
1185 OTG_TEST_PATTERN_INC1, inc_base + 2,
1186 OTG_TEST_PATTERN_HRES, 8,
1187 OTG_TEST_PATTERN_VRES, 5,
1188 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1189 }
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1196
1197 /* enable test pattern */
1198 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1199
1200 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1201 OTG_TEST_PATTERN_EN, 1,
1202 OTG_TEST_PATTERN_MODE, mode,
1203 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1204 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1205 }
1206 break;
1207 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1208 {
1209 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1210 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1211 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1212 }
1213 break;
1214 default:
1215 break;
1216
1217 }
1218 }
1219
optc1_get_crtc_scanoutpos(struct timing_generator * optc,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)1220 void optc1_get_crtc_scanoutpos(
1221 struct timing_generator *optc,
1222 uint32_t *v_blank_start,
1223 uint32_t *v_blank_end,
1224 uint32_t *h_position,
1225 uint32_t *v_position)
1226 {
1227 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1228 struct crtc_position position;
1229
1230 REG_GET_2(OTG_V_BLANK_START_END,
1231 OTG_V_BLANK_START, v_blank_start,
1232 OTG_V_BLANK_END, v_blank_end);
1233
1234 optc1_get_position(optc, &position);
1235
1236 *h_position = position.horizontal_count;
1237 *v_position = position.vertical_count;
1238 }
1239
optc1_enable_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1240 static void optc1_enable_stereo(struct timing_generator *optc,
1241 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1242 {
1243 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1244
1245 if (flags) {
1246 uint32_t stereo_en;
1247 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1248
1249 if (flags->PROGRAM_STEREO)
1250 REG_UPDATE_3(OTG_STEREO_CONTROL,
1251 OTG_STEREO_EN, stereo_en,
1252 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1253 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1254
1255 if (flags->PROGRAM_POLARITY)
1256 REG_UPDATE(OTG_STEREO_CONTROL,
1257 OTG_STEREO_EYE_FLAG_POLARITY,
1258 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1259
1260 if (flags->DISABLE_STEREO_DP_SYNC)
1261 REG_UPDATE(OTG_STEREO_CONTROL,
1262 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1263
1264 if (flags->PROGRAM_STEREO)
1265 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1266 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1267 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1268
1269 }
1270 }
1271
optc1_program_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1272 void optc1_program_stereo(struct timing_generator *optc,
1273 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1274 {
1275 if (flags->PROGRAM_STEREO)
1276 optc1_enable_stereo(optc, timing, flags);
1277 else
1278 optc1_disable_stereo(optc);
1279 }
1280
1281
optc1_is_stereo_left_eye(struct timing_generator * optc)1282 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1283 {
1284 bool ret = false;
1285 uint32_t left_eye = 0;
1286 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1287
1288 REG_GET(OTG_STEREO_STATUS,
1289 OTG_STEREO_CURRENT_EYE, &left_eye);
1290 if (left_eye == 1)
1291 ret = true;
1292 else
1293 ret = false;
1294
1295 return ret;
1296 }
1297
optc1_get_hw_timing(struct timing_generator * tg,struct dc_crtc_timing * hw_crtc_timing)1298 bool optc1_get_hw_timing(struct timing_generator *tg,
1299 struct dc_crtc_timing *hw_crtc_timing)
1300 {
1301 struct dcn_otg_state s = {0};
1302
1303 if (tg == NULL || hw_crtc_timing == NULL)
1304 return false;
1305
1306 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1307
1308 hw_crtc_timing->h_total = s.h_total + 1;
1309 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1310 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1311 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1312
1313 hw_crtc_timing->v_total = s.v_total + 1;
1314 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1315 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1316 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1317
1318 return true;
1319 }
1320
1321
optc1_read_otg_state(struct optc * optc1,struct dcn_otg_state * s)1322 void optc1_read_otg_state(struct optc *optc1,
1323 struct dcn_otg_state *s)
1324 {
1325 REG_GET(OTG_CONTROL,
1326 OTG_MASTER_EN, &s->otg_enabled);
1327
1328 REG_GET_2(OTG_V_BLANK_START_END,
1329 OTG_V_BLANK_START, &s->v_blank_start,
1330 OTG_V_BLANK_END, &s->v_blank_end);
1331
1332 REG_GET(OTG_V_SYNC_A_CNTL,
1333 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1334
1335 REG_GET(OTG_V_TOTAL,
1336 OTG_V_TOTAL, &s->v_total);
1337
1338 REG_GET(OTG_V_TOTAL_MAX,
1339 OTG_V_TOTAL_MAX, &s->v_total_max);
1340
1341 REG_GET(OTG_V_TOTAL_MIN,
1342 OTG_V_TOTAL_MIN, &s->v_total_min);
1343
1344 REG_GET(OTG_V_TOTAL_CONTROL,
1345 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1346
1347 REG_GET(OTG_V_TOTAL_CONTROL,
1348 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1349
1350 REG_GET_2(OTG_V_SYNC_A,
1351 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1352 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1353
1354 REG_GET_2(OTG_H_BLANK_START_END,
1355 OTG_H_BLANK_START, &s->h_blank_start,
1356 OTG_H_BLANK_END, &s->h_blank_end);
1357
1358 REG_GET_2(OTG_H_SYNC_A,
1359 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1360 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1361
1362 REG_GET(OTG_H_SYNC_A_CNTL,
1363 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1364
1365 REG_GET(OTG_H_TOTAL,
1366 OTG_H_TOTAL, &s->h_total);
1367
1368 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1369 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1370
1371 REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
1372 OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en);
1373
1374 REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
1375 OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line);
1376
1377 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
1378 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
1379
1380 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
1381 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
1382 }
1383
optc1_get_otg_active_size(struct timing_generator * optc,uint32_t * otg_active_width,uint32_t * otg_active_height)1384 bool optc1_get_otg_active_size(struct timing_generator *optc,
1385 uint32_t *otg_active_width,
1386 uint32_t *otg_active_height)
1387 {
1388 uint32_t otg_enabled;
1389 uint32_t v_blank_start;
1390 uint32_t v_blank_end;
1391 uint32_t h_blank_start;
1392 uint32_t h_blank_end;
1393 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1394
1395
1396 REG_GET(OTG_CONTROL,
1397 OTG_MASTER_EN, &otg_enabled);
1398
1399 if (otg_enabled == 0)
1400 return false;
1401
1402 REG_GET_2(OTG_V_BLANK_START_END,
1403 OTG_V_BLANK_START, &v_blank_start,
1404 OTG_V_BLANK_END, &v_blank_end);
1405
1406 REG_GET_2(OTG_H_BLANK_START_END,
1407 OTG_H_BLANK_START, &h_blank_start,
1408 OTG_H_BLANK_END, &h_blank_end);
1409
1410 *otg_active_width = v_blank_start - v_blank_end;
1411 *otg_active_height = h_blank_start - h_blank_end;
1412 return true;
1413 }
1414
optc1_clear_optc_underflow(struct timing_generator * optc)1415 void optc1_clear_optc_underflow(struct timing_generator *optc)
1416 {
1417 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1418
1419 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1420 }
1421
optc1_tg_init(struct timing_generator * optc)1422 void optc1_tg_init(struct timing_generator *optc)
1423 {
1424 optc1_set_blank_data_double_buffer(optc, true);
1425 optc1_set_timing_double_buffer(optc, true);
1426 optc1_clear_optc_underflow(optc);
1427 }
1428
optc1_is_tg_enabled(struct timing_generator * optc)1429 bool optc1_is_tg_enabled(struct timing_generator *optc)
1430 {
1431 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1432 uint32_t otg_enabled = 0;
1433
1434 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1435
1436 return (otg_enabled != 0);
1437
1438 }
1439
optc1_is_optc_underflow_occurred(struct timing_generator * optc)1440 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1441 {
1442 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1443 uint32_t underflow_occurred = 0;
1444
1445 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1446 OPTC_UNDERFLOW_OCCURRED_STATUS,
1447 &underflow_occurred);
1448
1449 return (underflow_occurred == 1);
1450 }
1451
optc1_configure_crc(struct timing_generator * optc,const struct crc_params * params)1452 bool optc1_configure_crc(struct timing_generator *optc,
1453 const struct crc_params *params)
1454 {
1455 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1456
1457 /* Cannot configure crc on a CRTC that is disabled */
1458 if (!optc1_is_tg_enabled(optc))
1459 return false;
1460
1461 REG_WRITE(OTG_CRC_CNTL, 0);
1462
1463 if (!params->enable)
1464 return true;
1465
1466 /* Program frame boundaries */
1467 /* Window A x axis start and end. */
1468 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1469 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1470 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1471
1472 /* Window A y axis start and end. */
1473 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1474 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1475 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1476
1477 /* Window B x axis start and end. */
1478 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1479 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1480 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1481
1482 /* Window B y axis start and end. */
1483 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1484 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1485 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1486
1487 /* Set crc mode and selection, and enable. Only using CRC0*/
1488 REG_UPDATE_3(OTG_CRC_CNTL,
1489 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1490 OTG_CRC0_SELECT, params->selection,
1491 OTG_CRC_EN, 1);
1492
1493 return true;
1494 }
1495
1496 /**
1497 * optc1_get_crc - Capture CRC result per component
1498 *
1499 * @optc: timing_generator instance.
1500 * @r_cr: 16-bit primary CRC signature for red data.
1501 * @g_y: 16-bit primary CRC signature for green data.
1502 * @b_cb: 16-bit primary CRC signature for blue data.
1503 *
1504 * This function reads the CRC signature from the OPTC registers. Notice that
1505 * we have three registers to keep the CRC result per color component (RGB).
1506 *
1507 * Returns:
1508 * If CRC is disabled, return false; otherwise, return true, and the CRC
1509 * results in the parameters.
1510 */
optc1_get_crc(struct timing_generator * optc,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)1511 bool optc1_get_crc(struct timing_generator *optc,
1512 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1513 {
1514 uint32_t field = 0;
1515 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1516
1517 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1518
1519 /* Early return if CRC is not enabled for this CRTC */
1520 if (!field)
1521 return false;
1522
1523 /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
1524 REG_GET_2(OTG_CRC0_DATA_RG,
1525 CRC0_R_CR, r_cr,
1526 CRC0_G_Y, g_y);
1527
1528 /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
1529 REG_GET(OTG_CRC0_DATA_B,
1530 CRC0_B_CB, b_cb);
1531
1532 return true;
1533 }
1534
1535 static const struct timing_generator_funcs dcn10_tg_funcs = {
1536 .validate_timing = optc1_validate_timing,
1537 .program_timing = optc1_program_timing,
1538 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1539 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1540 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1541 .program_global_sync = optc1_program_global_sync,
1542 .enable_crtc = optc1_enable_crtc,
1543 .disable_crtc = optc1_disable_crtc,
1544 /* used by enable_timing_synchronization. Not need for FPGA */
1545 .is_counter_moving = optc1_is_counter_moving,
1546 .get_position = optc1_get_position,
1547 .get_frame_count = optc1_get_vblank_counter,
1548 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1549 .get_otg_active_size = optc1_get_otg_active_size,
1550 .set_early_control = optc1_set_early_control,
1551 /* used by enable_timing_synchronization. Not need for FPGA */
1552 .wait_for_state = optc1_wait_for_state,
1553 .set_blank = optc1_set_blank,
1554 .is_blanked = optc1_is_blanked,
1555 .set_blank_color = optc1_program_blank_color,
1556 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1557 .enable_reset_trigger = optc1_enable_reset_trigger,
1558 .enable_crtc_reset = optc1_enable_crtc_reset,
1559 .disable_reset_trigger = optc1_disable_reset_trigger,
1560 .lock = optc1_lock,
1561 .unlock = optc1_unlock,
1562 .enable_optc_clock = optc1_enable_optc_clock,
1563 .set_drr = optc1_set_drr,
1564 .get_last_used_drr_vtotal = NULL,
1565 .set_vtotal_min_max = optc1_set_vtotal_min_max,
1566 .set_static_screen_control = optc1_set_static_screen_control,
1567 .set_test_pattern = optc1_set_test_pattern,
1568 .program_stereo = optc1_program_stereo,
1569 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1570 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1571 .tg_init = optc1_tg_init,
1572 .is_tg_enabled = optc1_is_tg_enabled,
1573 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1574 .clear_optc_underflow = optc1_clear_optc_underflow,
1575 .get_crc = optc1_get_crc,
1576 .configure_crc = optc1_configure_crc,
1577 .set_vtg_params = optc1_set_vtg_params,
1578 .program_manual_trigger = optc1_program_manual_trigger,
1579 .setup_manual_trigger = optc1_setup_manual_trigger,
1580 .get_hw_timing = optc1_get_hw_timing,
1581 };
1582
dcn10_timing_generator_init(struct optc * optc1)1583 void dcn10_timing_generator_init(struct optc *optc1)
1584 {
1585 optc1->base.funcs = &dcn10_tg_funcs;
1586
1587 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1588 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1589
1590 optc1->min_h_blank = 32;
1591 optc1->min_v_blank = 3;
1592 optc1->min_v_blank_interlace = 5;
1593 optc1->min_h_sync_width = 4;
1594 optc1->min_v_sync_width = 1;
1595 }
1596
1597 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1598 *
1599 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1600 * containter rate.
1601 *
1602 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1603 * halved to maintain the correct pixel rate.
1604 *
1605 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1606 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1607 *
1608 */
optc1_is_two_pixels_per_containter(const struct dc_crtc_timing * timing)1609 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1610 {
1611 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1612
1613 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1614 && !timing->dsc_cfg.ycbcr422_simple);
1615 return two_pix;
1616 }
1617
1618