1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 *
4 * Authors: Phil Blundell <philb@gnu.org>
5 * Tim Waugh <tim@cyberelk.demon.co.uk>
6 * Jose Renau <renau@acm.org>
7 * David Campbell
8 * Andrea Arcangeli
9 *
10 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 *
12 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
13 * DMA support - Bert De Jonghe <bert@sophis.be>
14 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
15 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
16 * Various hacks, Fred Barnes, 04/2001
17 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
18 */
19
20 /* This driver should work with any hardware that is broadly compatible
21 * with that in the IBM PC. This applies to the majority of integrated
22 * I/O chipsets that are commonly available. The expected register
23 * layout is:
24 *
25 * base+0 data
26 * base+1 status
27 * base+2 control
28 *
29 * In addition, there are some optional registers:
30 *
31 * base+3 EPP address
32 * base+4 EPP data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
36 *
37 * All registers are 8 bits wide and read/write. If your hardware differs
38 * only in register addresses (eg because your registers are on 32-bit
39 * word boundaries) then you can alter the constants in parport_pc.h to
40 * accommodate this.
41 *
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
43 * but rather will start at port->base_hi.
44 */
45
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched/signal.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/pci.h>
57 #include <linux/pnp.h>
58 #include <linux/platform_device.h>
59 #include <linux/sysctl.h>
60 #include <linux/io.h>
61 #include <linux/uaccess.h>
62
63 #include <asm/dma.h>
64
65 #include <linux/parport.h>
66 #include <linux/parport_pc.h>
67 #include <linux/via.h>
68 #include <asm/parport.h>
69
70 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
71
72 #ifdef CONFIG_ISA_DMA_API
73 #define HAS_DMA
74 #endif
75
76 /* ECR modes */
77 #define ECR_SPP 00
78 #define ECR_PS2 01
79 #define ECR_PPF 02
80 #define ECR_ECP 03
81 #define ECR_EPP 04
82 #define ECR_VND 05
83 #define ECR_TST 06
84 #define ECR_CNF 07
85 #define ECR_MODE_MASK 0xe0
86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
87
88 #undef DEBUG
89
90 #define NR_SUPERIOS 3
91 static struct superio_struct { /* For Super-IO chips autodetection */
92 int io;
93 int irq;
94 int dma;
95 } superios[NR_SUPERIOS] = { {0,},};
96
97 static int user_specified;
98 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100 static int verbose_probing;
101 #endif
102 static int pci_registered_parport;
103 static int pnp_registered_parport;
104
105 /* frob_control, but for ECR */
frob_econtrol(struct parport * pb,unsigned char m,unsigned char v)106 static void frob_econtrol(struct parport *pb, unsigned char m,
107 unsigned char v)
108 {
109 const struct parport_pc_private *priv = pb->physport->private_data;
110 unsigned char ecr_writable = priv->ecr_writable;
111 unsigned char ectr = 0;
112 unsigned char new;
113
114 if (m != 0xff)
115 ectr = inb(ECONTROL(pb));
116
117 new = (ectr & ~m) ^ v;
118 if (ecr_writable)
119 /* All known users of the ECR mask require bit 0 to be set. */
120 new = (new & ecr_writable) | 1;
121
122 pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new);
123
124 outb(new, ECONTROL(pb));
125 }
126
frob_set_mode(struct parport * p,int mode)127 static inline void frob_set_mode(struct parport *p, int mode)
128 {
129 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
130 }
131
132 #ifdef CONFIG_PARPORT_PC_FIFO
133 /* Safely change the mode bits in the ECR
134 Returns:
135 0 : Success
136 -EBUSY: Could not drain FIFO in some finite amount of time,
137 mode not changed!
138 */
change_mode(struct parport * p,int m)139 static int change_mode(struct parport *p, int m)
140 {
141 const struct parport_pc_private *priv = p->physport->private_data;
142 unsigned char oecr;
143 int mode;
144
145 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m);
146
147 if (!priv->ecr) {
148 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
149 return 0;
150 }
151
152 /* Bits <7:5> contain the mode. */
153 oecr = inb(ECONTROL(p));
154 mode = (oecr >> 5) & 0x7;
155 if (mode == m)
156 return 0;
157
158 if (mode >= 2 && !(priv->ctr & 0x20)) {
159 /* This mode resets the FIFO, so we may
160 * have to wait for it to drain first. */
161 unsigned long expire = jiffies + p->physport->cad->timeout;
162 int counter;
163 switch (mode) {
164 case ECR_PPF: /* Parallel Port FIFO mode */
165 case ECR_ECP: /* ECP Parallel Port mode */
166 /* Busy wait for 200us */
167 for (counter = 0; counter < 40; counter++) {
168 if (inb(ECONTROL(p)) & 0x01)
169 break;
170 if (signal_pending(current))
171 break;
172 udelay(5);
173 }
174
175 /* Poll slowly. */
176 while (!(inb(ECONTROL(p)) & 0x01)) {
177 if (time_after_eq(jiffies, expire))
178 /* The FIFO is stuck. */
179 return -EBUSY;
180 schedule_timeout_interruptible(
181 msecs_to_jiffies(10));
182 if (signal_pending(current))
183 break;
184 }
185 }
186 }
187
188 if (mode >= 2 && m >= 2) {
189 /* We have to go through mode 001 */
190 oecr &= ~(7 << 5);
191 oecr |= ECR_PS2 << 5;
192 ECR_WRITE(p, oecr);
193 }
194
195 /* Set the mode. */
196 oecr &= ~(7 << 5);
197 oecr |= m << 5;
198 ECR_WRITE(p, oecr);
199 return 0;
200 }
201 #endif /* FIFO support */
202
203 /*
204 * Clear TIMEOUT BIT in EPP MODE
205 *
206 * This is also used in SPP detection.
207 */
clear_epp_timeout(struct parport * pb)208 static int clear_epp_timeout(struct parport *pb)
209 {
210 unsigned char r;
211
212 if (!(parport_pc_read_status(pb) & 0x01))
213 return 1;
214
215 /* To clear timeout some chips require double read */
216 parport_pc_read_status(pb);
217 r = parport_pc_read_status(pb);
218 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
219 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
220 r = parport_pc_read_status(pb);
221
222 return !(r & 0x01);
223 }
224
225 /*
226 * Access functions.
227 *
228 * Most of these aren't static because they may be used by the
229 * parport_xxx_yyy macros. extern __inline__ versions of several
230 * of these are in parport_pc.h.
231 */
232
parport_pc_init_state(struct pardevice * dev,struct parport_state * s)233 static void parport_pc_init_state(struct pardevice *dev,
234 struct parport_state *s)
235 {
236 s->u.pc.ctr = 0xc;
237 if (dev->irq_func &&
238 dev->port->irq != PARPORT_IRQ_NONE)
239 /* Set ackIntEn */
240 s->u.pc.ctr |= 0x10;
241
242 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
243 * D.Gruszka VScom */
244 }
245
parport_pc_save_state(struct parport * p,struct parport_state * s)246 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
247 {
248 const struct parport_pc_private *priv = p->physport->private_data;
249 s->u.pc.ctr = priv->ctr;
250 if (priv->ecr)
251 s->u.pc.ecr = inb(ECONTROL(p));
252 }
253
parport_pc_restore_state(struct parport * p,struct parport_state * s)254 static void parport_pc_restore_state(struct parport *p,
255 struct parport_state *s)
256 {
257 struct parport_pc_private *priv = p->physport->private_data;
258 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
259 outb(c, CONTROL(p));
260 priv->ctr = c;
261 if (priv->ecr)
262 ECR_WRITE(p, s->u.pc.ecr);
263 }
264
265 #ifdef CONFIG_PARPORT_1284
parport_pc_epp_read_data(struct parport * port,void * buf,size_t length,int flags)266 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
267 size_t length, int flags)
268 {
269 size_t got = 0;
270
271 if (flags & PARPORT_W91284PIC) {
272 unsigned char status;
273 size_t left = length;
274
275 /* use knowledge about data lines..:
276 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
277 * pError is 1 if there are 16 bytes in the Warp's FIFO
278 */
279 status = inb(STATUS(port));
280
281 while (!(status & 0x08) && got < length) {
282 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
283 /* can grab 16 bytes from warp fifo */
284 if (!((long)buf & 0x03))
285 insl(EPPDATA(port), buf, 4);
286 else
287 insb(EPPDATA(port), buf, 16);
288 buf += 16;
289 got += 16;
290 left -= 16;
291 } else {
292 /* grab single byte from the warp fifo */
293 *((char *)buf) = inb(EPPDATA(port));
294 buf++;
295 got++;
296 left--;
297 }
298 status = inb(STATUS(port));
299 if (status & 0x01) {
300 /* EPP timeout should never occur... */
301 printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n",
302 port->name);
303 clear_epp_timeout(port);
304 }
305 }
306 return got;
307 }
308 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
309 if (!(((long)buf | length) & 0x03))
310 insl(EPPDATA(port), buf, (length >> 2));
311 else
312 insb(EPPDATA(port), buf, length);
313 if (inb(STATUS(port)) & 0x01) {
314 clear_epp_timeout(port);
315 return -EIO;
316 }
317 return length;
318 }
319 for (; got < length; got++) {
320 *((char *)buf) = inb(EPPDATA(port));
321 buf++;
322 if (inb(STATUS(port)) & 0x01) {
323 /* EPP timeout */
324 clear_epp_timeout(port);
325 break;
326 }
327 }
328
329 return got;
330 }
331
parport_pc_epp_write_data(struct parport * port,const void * buf,size_t length,int flags)332 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
333 size_t length, int flags)
334 {
335 size_t written = 0;
336
337 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
338 if (!(((long)buf | length) & 0x03))
339 outsl(EPPDATA(port), buf, (length >> 2));
340 else
341 outsb(EPPDATA(port), buf, length);
342 if (inb(STATUS(port)) & 0x01) {
343 clear_epp_timeout(port);
344 return -EIO;
345 }
346 return length;
347 }
348 for (; written < length; written++) {
349 outb(*((char *)buf), EPPDATA(port));
350 buf++;
351 if (inb(STATUS(port)) & 0x01) {
352 clear_epp_timeout(port);
353 break;
354 }
355 }
356
357 return written;
358 }
359
parport_pc_epp_read_addr(struct parport * port,void * buf,size_t length,int flags)360 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
361 size_t length, int flags)
362 {
363 size_t got = 0;
364
365 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
366 insb(EPPADDR(port), buf, length);
367 if (inb(STATUS(port)) & 0x01) {
368 clear_epp_timeout(port);
369 return -EIO;
370 }
371 return length;
372 }
373 for (; got < length; got++) {
374 *((char *)buf) = inb(EPPADDR(port));
375 buf++;
376 if (inb(STATUS(port)) & 0x01) {
377 clear_epp_timeout(port);
378 break;
379 }
380 }
381
382 return got;
383 }
384
parport_pc_epp_write_addr(struct parport * port,const void * buf,size_t length,int flags)385 static size_t parport_pc_epp_write_addr(struct parport *port,
386 const void *buf, size_t length,
387 int flags)
388 {
389 size_t written = 0;
390
391 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
392 outsb(EPPADDR(port), buf, length);
393 if (inb(STATUS(port)) & 0x01) {
394 clear_epp_timeout(port);
395 return -EIO;
396 }
397 return length;
398 }
399 for (; written < length; written++) {
400 outb(*((char *)buf), EPPADDR(port));
401 buf++;
402 if (inb(STATUS(port)) & 0x01) {
403 clear_epp_timeout(port);
404 break;
405 }
406 }
407
408 return written;
409 }
410
parport_pc_ecpepp_read_data(struct parport * port,void * buf,size_t length,int flags)411 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
412 size_t length, int flags)
413 {
414 size_t got;
415
416 frob_set_mode(port, ECR_EPP);
417 parport_pc_data_reverse(port);
418 parport_pc_write_control(port, 0x4);
419 got = parport_pc_epp_read_data(port, buf, length, flags);
420 frob_set_mode(port, ECR_PS2);
421
422 return got;
423 }
424
parport_pc_ecpepp_write_data(struct parport * port,const void * buf,size_t length,int flags)425 static size_t parport_pc_ecpepp_write_data(struct parport *port,
426 const void *buf, size_t length,
427 int flags)
428 {
429 size_t written;
430
431 frob_set_mode(port, ECR_EPP);
432 parport_pc_write_control(port, 0x4);
433 parport_pc_data_forward(port);
434 written = parport_pc_epp_write_data(port, buf, length, flags);
435 frob_set_mode(port, ECR_PS2);
436
437 return written;
438 }
439
parport_pc_ecpepp_read_addr(struct parport * port,void * buf,size_t length,int flags)440 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
441 size_t length, int flags)
442 {
443 size_t got;
444
445 frob_set_mode(port, ECR_EPP);
446 parport_pc_data_reverse(port);
447 parport_pc_write_control(port, 0x4);
448 got = parport_pc_epp_read_addr(port, buf, length, flags);
449 frob_set_mode(port, ECR_PS2);
450
451 return got;
452 }
453
parport_pc_ecpepp_write_addr(struct parport * port,const void * buf,size_t length,int flags)454 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
455 const void *buf, size_t length,
456 int flags)
457 {
458 size_t written;
459
460 frob_set_mode(port, ECR_EPP);
461 parport_pc_write_control(port, 0x4);
462 parport_pc_data_forward(port);
463 written = parport_pc_epp_write_addr(port, buf, length, flags);
464 frob_set_mode(port, ECR_PS2);
465
466 return written;
467 }
468 #endif /* IEEE 1284 support */
469
470 #ifdef CONFIG_PARPORT_PC_FIFO
parport_pc_fifo_write_block_pio(struct parport * port,const void * buf,size_t length)471 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
472 const void *buf, size_t length)
473 {
474 int ret = 0;
475 const unsigned char *bufp = buf;
476 size_t left = length;
477 unsigned long expire = jiffies + port->physport->cad->timeout;
478 const unsigned long fifo = FIFO(port);
479 int poll_for = 8; /* 80 usecs */
480 const struct parport_pc_private *priv = port->physport->private_data;
481 const int fifo_depth = priv->fifo_depth;
482
483 port = port->physport;
484
485 /* We don't want to be interrupted every character. */
486 parport_pc_disable_irq(port);
487 /* set nErrIntrEn and serviceIntr */
488 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
489
490 /* Forward mode. */
491 parport_pc_data_forward(port); /* Must be in PS2 mode */
492
493 while (left) {
494 unsigned char byte;
495 unsigned char ecrval = inb(ECONTROL(port));
496 int i = 0;
497
498 if (need_resched() && time_before(jiffies, expire))
499 /* Can't yield the port. */
500 schedule();
501
502 /* Anyone else waiting for the port? */
503 if (port->waithead) {
504 printk(KERN_DEBUG "Somebody wants the port\n");
505 break;
506 }
507
508 if (ecrval & 0x02) {
509 /* FIFO is full. Wait for interrupt. */
510
511 /* Clear serviceIntr */
512 ECR_WRITE(port, ecrval & ~(1<<2));
513 false_alarm:
514 ret = parport_wait_event(port, HZ);
515 if (ret < 0)
516 break;
517 ret = 0;
518 if (!time_before(jiffies, expire)) {
519 /* Timed out. */
520 printk(KERN_DEBUG "FIFO write timed out\n");
521 break;
522 }
523 ecrval = inb(ECONTROL(port));
524 if (!(ecrval & (1<<2))) {
525 if (need_resched() &&
526 time_before(jiffies, expire))
527 schedule();
528
529 goto false_alarm;
530 }
531
532 continue;
533 }
534
535 /* Can't fail now. */
536 expire = jiffies + port->cad->timeout;
537
538 poll:
539 if (signal_pending(current))
540 break;
541
542 if (ecrval & 0x01) {
543 /* FIFO is empty. Blast it full. */
544 const int n = left < fifo_depth ? left : fifo_depth;
545 outsb(fifo, bufp, n);
546 bufp += n;
547 left -= n;
548
549 /* Adjust the poll time. */
550 if (i < (poll_for - 2))
551 poll_for--;
552 continue;
553 } else if (i++ < poll_for) {
554 udelay(10);
555 ecrval = inb(ECONTROL(port));
556 goto poll;
557 }
558
559 /* Half-full(call me an optimist) */
560 byte = *bufp++;
561 outb(byte, fifo);
562 left--;
563 }
564 dump_parport_state("leave fifo_write_block_pio", port);
565 return length - left;
566 }
567
568 #ifdef HAS_DMA
parport_pc_fifo_write_block_dma(struct parport * port,const void * buf,size_t length)569 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
570 const void *buf, size_t length)
571 {
572 int ret = 0;
573 unsigned long dmaflag;
574 size_t left = length;
575 const struct parport_pc_private *priv = port->physport->private_data;
576 struct device *dev = port->physport->dev;
577 dma_addr_t dma_addr, dma_handle;
578 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
579 unsigned long start = (unsigned long) buf;
580 unsigned long end = (unsigned long) buf + length - 1;
581
582 dump_parport_state("enter fifo_write_block_dma", port);
583 if (end < MAX_DMA_ADDRESS) {
584 /* If it would cross a 64k boundary, cap it at the end. */
585 if ((start ^ end) & ~0xffffUL)
586 maxlen = 0x10000 - (start & 0xffff);
587
588 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
589 DMA_TO_DEVICE);
590 } else {
591 /* above 16 MB we use a bounce buffer as ISA-DMA
592 is not possible */
593 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
594 dma_addr = priv->dma_handle;
595 dma_handle = 0;
596 }
597
598 port = port->physport;
599
600 /* We don't want to be interrupted every character. */
601 parport_pc_disable_irq(port);
602 /* set nErrIntrEn and serviceIntr */
603 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
604
605 /* Forward mode. */
606 parport_pc_data_forward(port); /* Must be in PS2 mode */
607
608 while (left) {
609 unsigned long expire = jiffies + port->physport->cad->timeout;
610
611 size_t count = left;
612
613 if (count > maxlen)
614 count = maxlen;
615
616 if (!dma_handle) /* bounce buffer ! */
617 memcpy(priv->dma_buf, buf, count);
618
619 dmaflag = claim_dma_lock();
620 disable_dma(port->dma);
621 clear_dma_ff(port->dma);
622 set_dma_mode(port->dma, DMA_MODE_WRITE);
623 set_dma_addr(port->dma, dma_addr);
624 set_dma_count(port->dma, count);
625
626 /* Set DMA mode */
627 frob_econtrol(port, 1<<3, 1<<3);
628
629 /* Clear serviceIntr */
630 frob_econtrol(port, 1<<2, 0);
631
632 enable_dma(port->dma);
633 release_dma_lock(dmaflag);
634
635 /* assume DMA will be successful */
636 left -= count;
637 buf += count;
638 if (dma_handle)
639 dma_addr += count;
640
641 /* Wait for interrupt. */
642 false_alarm:
643 ret = parport_wait_event(port, HZ);
644 if (ret < 0)
645 break;
646 ret = 0;
647 if (!time_before(jiffies, expire)) {
648 /* Timed out. */
649 printk(KERN_DEBUG "DMA write timed out\n");
650 break;
651 }
652 /* Is serviceIntr set? */
653 if (!(inb(ECONTROL(port)) & (1<<2))) {
654 cond_resched();
655
656 goto false_alarm;
657 }
658
659 dmaflag = claim_dma_lock();
660 disable_dma(port->dma);
661 clear_dma_ff(port->dma);
662 count = get_dma_residue(port->dma);
663 release_dma_lock(dmaflag);
664
665 cond_resched(); /* Can't yield the port. */
666
667 /* Anyone else waiting for the port? */
668 if (port->waithead) {
669 printk(KERN_DEBUG "Somebody wants the port\n");
670 break;
671 }
672
673 /* update for possible DMA residue ! */
674 buf -= count;
675 left += count;
676 if (dma_handle)
677 dma_addr -= count;
678 }
679
680 /* Maybe got here through break, so adjust for DMA residue! */
681 dmaflag = claim_dma_lock();
682 disable_dma(port->dma);
683 clear_dma_ff(port->dma);
684 left += get_dma_residue(port->dma);
685 release_dma_lock(dmaflag);
686
687 /* Turn off DMA mode */
688 frob_econtrol(port, 1<<3, 0);
689
690 if (dma_handle)
691 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
692
693 dump_parport_state("leave fifo_write_block_dma", port);
694 return length - left;
695 }
696 #endif
697
parport_pc_fifo_write_block(struct parport * port,const void * buf,size_t length)698 static inline size_t parport_pc_fifo_write_block(struct parport *port,
699 const void *buf, size_t length)
700 {
701 #ifdef HAS_DMA
702 if (port->dma != PARPORT_DMA_NONE)
703 return parport_pc_fifo_write_block_dma(port, buf, length);
704 #endif
705 return parport_pc_fifo_write_block_pio(port, buf, length);
706 }
707
708 /* Parallel Port FIFO mode (ECP chipsets) */
parport_pc_compat_write_block_pio(struct parport * port,const void * buf,size_t length,int flags)709 static size_t parport_pc_compat_write_block_pio(struct parport *port,
710 const void *buf, size_t length,
711 int flags)
712 {
713 size_t written;
714 int r;
715 unsigned long expire;
716 const struct parport_pc_private *priv = port->physport->private_data;
717
718 /* Special case: a timeout of zero means we cannot call schedule().
719 * Also if O_NONBLOCK is set then use the default implementation. */
720 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
721 return parport_ieee1284_write_compat(port, buf,
722 length, flags);
723
724 /* Set up parallel port FIFO mode.*/
725 parport_pc_data_forward(port); /* Must be in PS2 mode */
726 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
727 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
728 if (r)
729 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
730 port->name);
731
732 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
733
734 /* Write the data to the FIFO. */
735 written = parport_pc_fifo_write_block(port, buf, length);
736
737 /* Finish up. */
738 /* For some hardware we don't want to touch the mode until
739 * the FIFO is empty, so allow 4 seconds for each position
740 * in the fifo.
741 */
742 expire = jiffies + (priv->fifo_depth * HZ * 4);
743 do {
744 /* Wait for the FIFO to empty */
745 r = change_mode(port, ECR_PS2);
746 if (r != -EBUSY)
747 break;
748 } while (time_before(jiffies, expire));
749 if (r == -EBUSY) {
750
751 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
752
753 /* Prevent further data transfer. */
754 frob_set_mode(port, ECR_TST);
755
756 /* Adjust for the contents of the FIFO. */
757 for (written -= priv->fifo_depth; ; written++) {
758 if (inb(ECONTROL(port)) & 0x2) {
759 /* Full up. */
760 break;
761 }
762 outb(0, FIFO(port));
763 }
764
765 /* Reset the FIFO and return to PS2 mode. */
766 frob_set_mode(port, ECR_PS2);
767 }
768
769 r = parport_wait_peripheral(port,
770 PARPORT_STATUS_BUSY,
771 PARPORT_STATUS_BUSY);
772 if (r)
773 printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n",
774 port->name, r);
775
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778 return written;
779 }
780
781 /* ECP */
782 #ifdef CONFIG_PARPORT_1284
parport_pc_ecp_write_block_pio(struct parport * port,const void * buf,size_t length,int flags)783 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
784 const void *buf, size_t length,
785 int flags)
786 {
787 size_t written;
788 int r;
789 unsigned long expire;
790 const struct parport_pc_private *priv = port->physport->private_data;
791
792 /* Special case: a timeout of zero means we cannot call schedule().
793 * Also if O_NONBLOCK is set then use the default implementation. */
794 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
795 return parport_ieee1284_ecp_write_data(port, buf,
796 length, flags);
797
798 /* Switch to forward mode if necessary. */
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800 /* Event 47: Set nInit high. */
801 parport_frob_control(port,
802 PARPORT_CONTROL_INIT
803 | PARPORT_CONTROL_AUTOFD,
804 PARPORT_CONTROL_INIT
805 | PARPORT_CONTROL_AUTOFD);
806
807 /* Event 49: PError goes high. */
808 r = parport_wait_peripheral(port,
809 PARPORT_STATUS_PAPEROUT,
810 PARPORT_STATUS_PAPEROUT);
811 if (r) {
812 printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n",
813 port->name, r);
814 }
815 }
816
817 /* Set up ECP parallel port mode.*/
818 parport_pc_data_forward(port); /* Must be in PS2 mode */
819 parport_pc_frob_control(port,
820 PARPORT_CONTROL_STROBE |
821 PARPORT_CONTROL_AUTOFD,
822 0);
823 r = change_mode(port, ECR_ECP); /* ECP FIFO */
824 if (r)
825 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826 port->name);
827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829 /* Write the data to the FIFO. */
830 written = parport_pc_fifo_write_block(port, buf, length);
831
832 /* Finish up. */
833 /* For some hardware we don't want to touch the mode until
834 * the FIFO is empty, so allow 4 seconds for each position
835 * in the fifo.
836 */
837 expire = jiffies + (priv->fifo_depth * (HZ * 4));
838 do {
839 /* Wait for the FIFO to empty */
840 r = change_mode(port, ECR_PS2);
841 if (r != -EBUSY)
842 break;
843 } while (time_before(jiffies, expire));
844 if (r == -EBUSY) {
845
846 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
847
848 /* Prevent further data transfer. */
849 frob_set_mode(port, ECR_TST);
850
851 /* Adjust for the contents of the FIFO. */
852 for (written -= priv->fifo_depth; ; written++) {
853 if (inb(ECONTROL(port)) & 0x2) {
854 /* Full up. */
855 break;
856 }
857 outb(0, FIFO(port));
858 }
859
860 /* Reset the FIFO and return to PS2 mode. */
861 frob_set_mode(port, ECR_PS2);
862
863 /* Host transfer recovery. */
864 parport_pc_data_reverse(port); /* Must be in PS2 mode */
865 udelay(5);
866 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
868 if (r)
869 printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n",
870 port->name, r);
871
872 parport_frob_control(port,
873 PARPORT_CONTROL_INIT,
874 PARPORT_CONTROL_INIT);
875 r = parport_wait_peripheral(port,
876 PARPORT_STATUS_PAPEROUT,
877 PARPORT_STATUS_PAPEROUT);
878 if (r)
879 printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n",
880 port->name, r);
881 }
882
883 r = parport_wait_peripheral(port,
884 PARPORT_STATUS_BUSY,
885 PARPORT_STATUS_BUSY);
886 if (r)
887 printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
888 port->name, r);
889
890 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
891
892 return written;
893 }
894 #endif /* IEEE 1284 support */
895 #endif /* Allowed to use FIFO/DMA */
896
897
898 /*
899 * ******************************************
900 * INITIALISATION AND MODULE STUFF BELOW HERE
901 * ******************************************
902 */
903
904 /* GCC is not inlining extern inline function later overwritten to non-inline,
905 so we use outlined_ variants here. */
906 static const struct parport_operations parport_pc_ops = {
907 .write_data = parport_pc_write_data,
908 .read_data = parport_pc_read_data,
909
910 .write_control = parport_pc_write_control,
911 .read_control = parport_pc_read_control,
912 .frob_control = parport_pc_frob_control,
913
914 .read_status = parport_pc_read_status,
915
916 .enable_irq = parport_pc_enable_irq,
917 .disable_irq = parport_pc_disable_irq,
918
919 .data_forward = parport_pc_data_forward,
920 .data_reverse = parport_pc_data_reverse,
921
922 .init_state = parport_pc_init_state,
923 .save_state = parport_pc_save_state,
924 .restore_state = parport_pc_restore_state,
925
926 .epp_write_data = parport_ieee1284_epp_write_data,
927 .epp_read_data = parport_ieee1284_epp_read_data,
928 .epp_write_addr = parport_ieee1284_epp_write_addr,
929 .epp_read_addr = parport_ieee1284_epp_read_addr,
930
931 .ecp_write_data = parport_ieee1284_ecp_write_data,
932 .ecp_read_data = parport_ieee1284_ecp_read_data,
933 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
934
935 .compat_write_data = parport_ieee1284_write_compat,
936 .nibble_read_data = parport_ieee1284_read_nibble,
937 .byte_read_data = parport_ieee1284_read_byte,
938
939 .owner = THIS_MODULE,
940 };
941
942 #ifdef CONFIG_PARPORT_PC_SUPERIO
943
find_free_superio(void)944 static struct superio_struct *find_free_superio(void)
945 {
946 int i;
947 for (i = 0; i < NR_SUPERIOS; i++)
948 if (superios[i].io == 0)
949 return &superios[i];
950 return NULL;
951 }
952
953
954 /* Super-IO chipset detection, Winbond, SMSC */
show_parconfig_smsc37c669(int io,int key)955 static void show_parconfig_smsc37c669(int io, int key)
956 {
957 int cr1, cr4, cra, cr23, cr26, cr27;
958 struct superio_struct *s;
959
960 static const char *const modes[] = {
961 "SPP and Bidirectional (PS/2)",
962 "EPP and SPP",
963 "ECP",
964 "ECP and EPP" };
965
966 outb(key, io);
967 outb(key, io);
968 outb(1, io);
969 cr1 = inb(io + 1);
970 outb(4, io);
971 cr4 = inb(io + 1);
972 outb(0x0a, io);
973 cra = inb(io + 1);
974 outb(0x23, io);
975 cr23 = inb(io + 1);
976 outb(0x26, io);
977 cr26 = inb(io + 1);
978 outb(0x27, io);
979 cr27 = inb(io + 1);
980 outb(0xaa, io);
981
982 if (verbose_probing) {
983 pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
984 cr1, cr4, cra, cr23, cr26, cr27);
985
986 /* The documentation calls DMA and IRQ-Lines by letters, so
987 the board maker can/will wire them
988 appropriately/randomly... G=reserved H=IDE-irq, */
989 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
990 cr23 * 4,
991 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
992 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
993 cra & 0x0f);
994 pr_info("SMSC LPT Config: enabled=%s power=%s\n",
995 (cr23 * 4 >= 0x100) ? "yes" : "no",
996 (cr1 & 4) ? "yes" : "no");
997 pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n",
998 (cr1 & 0x08) ? "Standard mode only (SPP)"
999 : modes[cr4 & 0x03],
1000 (cr4 & 0x40) ? "1.7" : "1.9");
1001 }
1002
1003 /* Heuristics ! BIOS setup for this mainboard device limits
1004 the choices to standard settings, i.e. io-address and IRQ
1005 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1006 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1007 if (cr23 * 4 >= 0x100) { /* if active */
1008 s = find_free_superio();
1009 if (s == NULL)
1010 pr_info("Super-IO: too many chips!\n");
1011 else {
1012 int d;
1013 switch (cr23 * 4) {
1014 case 0x3bc:
1015 s->io = 0x3bc;
1016 s->irq = 7;
1017 break;
1018 case 0x378:
1019 s->io = 0x378;
1020 s->irq = 7;
1021 break;
1022 case 0x278:
1023 s->io = 0x278;
1024 s->irq = 5;
1025 }
1026 d = (cr26 & 0x0f);
1027 if (d == 1 || d == 3)
1028 s->dma = d;
1029 else
1030 s->dma = PARPORT_DMA_NONE;
1031 }
1032 }
1033 }
1034
1035
show_parconfig_winbond(int io,int key)1036 static void show_parconfig_winbond(int io, int key)
1037 {
1038 int cr30, cr60, cr61, cr70, cr74, crf0;
1039 struct superio_struct *s;
1040 static const char *const modes[] = {
1041 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1042 "EPP-1.9 and SPP",
1043 "ECP",
1044 "ECP and EPP-1.9",
1045 "Standard (SPP)",
1046 "EPP-1.7 and SPP", /* 5 */
1047 "undefined!",
1048 "ECP and EPP-1.7" };
1049 static char *const irqtypes[] = {
1050 "pulsed low, high-Z",
1051 "follows nACK" };
1052
1053 /* The registers are called compatible-PnP because the
1054 register layout is modelled after ISA-PnP, the access
1055 method is just another ... */
1056 outb(key, io);
1057 outb(key, io);
1058 outb(0x07, io); /* Register 7: Select Logical Device */
1059 outb(0x01, io + 1); /* LD1 is Parallel Port */
1060 outb(0x30, io);
1061 cr30 = inb(io + 1);
1062 outb(0x60, io);
1063 cr60 = inb(io + 1);
1064 outb(0x61, io);
1065 cr61 = inb(io + 1);
1066 outb(0x70, io);
1067 cr70 = inb(io + 1);
1068 outb(0x74, io);
1069 cr74 = inb(io + 1);
1070 outb(0xf0, io);
1071 crf0 = inb(io + 1);
1072 outb(0xaa, io);
1073
1074 if (verbose_probing) {
1075 pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1076 cr30, cr60, cr61, cr70, cr74, crf0);
1077 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1078 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1079 if ((cr74 & 0x07) > 3)
1080 pr_cont("dma=none\n");
1081 else
1082 pr_cont("dma=%d\n", cr74 & 0x07);
1083 pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1084 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f);
1085 pr_info("Winbond LPT Config: Port mode=%s\n",
1086 modes[crf0 & 0x07]);
1087 }
1088
1089 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1090 s = find_free_superio();
1091 if (s == NULL)
1092 pr_info("Super-IO: too many chips!\n");
1093 else {
1094 s->io = (cr60 << 8) | cr61;
1095 s->irq = cr70 & 0x0f;
1096 s->dma = (((cr74 & 0x07) > 3) ?
1097 PARPORT_DMA_NONE : (cr74 & 0x07));
1098 }
1099 }
1100 }
1101
decode_winbond(int efer,int key,int devid,int devrev,int oldid)1102 static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1103 {
1104 const char *type = "unknown";
1105 int id, progif = 2;
1106
1107 if (devid == devrev)
1108 /* simple heuristics, we happened to read some
1109 non-winbond register */
1110 return;
1111
1112 id = (devid << 8) | devrev;
1113
1114 /* Values are from public data sheets pdf files, I can just
1115 confirm 83977TF is correct :-) */
1116 if (id == 0x9771)
1117 type = "83977F/AF";
1118 else if (id == 0x9773)
1119 type = "83977TF / SMSC 97w33x/97w34x";
1120 else if (id == 0x9774)
1121 type = "83977ATF";
1122 else if ((id & ~0x0f) == 0x5270)
1123 type = "83977CTF / SMSC 97w36x";
1124 else if ((id & ~0x0f) == 0x52f0)
1125 type = "83977EF / SMSC 97w35x";
1126 else if ((id & ~0x0f) == 0x5210)
1127 type = "83627";
1128 else if ((id & ~0x0f) == 0x6010)
1129 type = "83697HF";
1130 else if ((oldid & 0x0f) == 0x0a) {
1131 type = "83877F";
1132 progif = 1;
1133 } else if ((oldid & 0x0f) == 0x0b) {
1134 type = "83877AF";
1135 progif = 1;
1136 } else if ((oldid & 0x0f) == 0x0c) {
1137 type = "83877TF";
1138 progif = 1;
1139 } else if ((oldid & 0x0f) == 0x0d) {
1140 type = "83877ATF";
1141 progif = 1;
1142 } else
1143 progif = 0;
1144
1145 if (verbose_probing)
1146 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n",
1147 efer, key, devid, devrev, oldid, type);
1148
1149 if (progif == 2)
1150 show_parconfig_winbond(efer, key);
1151 }
1152
decode_smsc(int efer,int key,int devid,int devrev)1153 static void decode_smsc(int efer, int key, int devid, int devrev)
1154 {
1155 const char *type = "unknown";
1156 void (*func)(int io, int key);
1157 int id;
1158
1159 if (devid == devrev)
1160 /* simple heuristics, we happened to read some
1161 non-smsc register */
1162 return;
1163
1164 func = NULL;
1165 id = (devid << 8) | devrev;
1166
1167 if (id == 0x0302) {
1168 type = "37c669";
1169 func = show_parconfig_smsc37c669;
1170 } else if (id == 0x6582)
1171 type = "37c665IR";
1172 else if (devid == 0x65)
1173 type = "37c665GT";
1174 else if (devid == 0x66)
1175 type = "37c666GT";
1176
1177 if (verbose_probing)
1178 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n",
1179 efer, key, devid, devrev, type);
1180
1181 if (func)
1182 func(efer, key);
1183 }
1184
1185
winbond_check(int io,int key)1186 static void winbond_check(int io, int key)
1187 {
1188 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1189
1190 if (!request_region(io, 3, __func__))
1191 return;
1192
1193 origval = inb(io); /* Save original value */
1194
1195 /* First probe without key */
1196 outb(0x20, io);
1197 x_devid = inb(io + 1);
1198 outb(0x21, io);
1199 x_devrev = inb(io + 1);
1200 outb(0x09, io);
1201 x_oldid = inb(io + 1);
1202
1203 outb(key, io);
1204 outb(key, io); /* Write Magic Sequence to EFER, extended
1205 function enable register */
1206 outb(0x20, io); /* Write EFIR, extended function index register */
1207 devid = inb(io + 1); /* Read EFDR, extended function data register */
1208 outb(0x21, io);
1209 devrev = inb(io + 1);
1210 outb(0x09, io);
1211 oldid = inb(io + 1);
1212 outb(0xaa, io); /* Magic Seal */
1213
1214 outb(origval, io); /* in case we poked some entirely different hardware */
1215
1216 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1217 goto out; /* protection against false positives */
1218
1219 decode_winbond(io, key, devid, devrev, oldid);
1220 out:
1221 release_region(io, 3);
1222 }
1223
winbond_check2(int io,int key)1224 static void winbond_check2(int io, int key)
1225 {
1226 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1227
1228 if (!request_region(io, 3, __func__))
1229 return;
1230
1231 origval[0] = inb(io); /* Save original values */
1232 origval[1] = inb(io + 1);
1233 origval[2] = inb(io + 2);
1234
1235 /* First probe without the key */
1236 outb(0x20, io + 2);
1237 x_devid = inb(io + 2);
1238 outb(0x21, io + 1);
1239 x_devrev = inb(io + 2);
1240 outb(0x09, io + 1);
1241 x_oldid = inb(io + 2);
1242
1243 outb(key, io); /* Write Magic Byte to EFER, extended
1244 function enable register */
1245 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1246 devid = inb(io + 2); /* Read EFDR, extended function data register */
1247 outb(0x21, io + 1);
1248 devrev = inb(io + 2);
1249 outb(0x09, io + 1);
1250 oldid = inb(io + 2);
1251 outb(0xaa, io); /* Magic Seal */
1252
1253 outb(origval[0], io); /* in case we poked some entirely different hardware */
1254 outb(origval[1], io + 1);
1255 outb(origval[2], io + 2);
1256
1257 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1258 goto out; /* protection against false positives */
1259
1260 decode_winbond(io, key, devid, devrev, oldid);
1261 out:
1262 release_region(io, 3);
1263 }
1264
smsc_check(int io,int key)1265 static void smsc_check(int io, int key)
1266 {
1267 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1268
1269 if (!request_region(io, 3, __func__))
1270 return;
1271
1272 origval = inb(io); /* Save original value */
1273
1274 /* First probe without the key */
1275 outb(0x0d, io);
1276 x_oldid = inb(io + 1);
1277 outb(0x0e, io);
1278 x_oldrev = inb(io + 1);
1279 outb(0x20, io);
1280 x_id = inb(io + 1);
1281 outb(0x21, io);
1282 x_rev = inb(io + 1);
1283
1284 outb(key, io);
1285 outb(key, io); /* Write Magic Sequence to EFER, extended
1286 function enable register */
1287 outb(0x0d, io); /* Write EFIR, extended function index register */
1288 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1289 outb(0x0e, io);
1290 oldrev = inb(io + 1);
1291 outb(0x20, io);
1292 id = inb(io + 1);
1293 outb(0x21, io);
1294 rev = inb(io + 1);
1295 outb(0xaa, io); /* Magic Seal */
1296
1297 outb(origval, io); /* in case we poked some entirely different hardware */
1298
1299 if (x_id == id && x_oldrev == oldrev &&
1300 x_oldid == oldid && x_rev == rev)
1301 goto out; /* protection against false positives */
1302
1303 decode_smsc(io, key, oldid, oldrev);
1304 out:
1305 release_region(io, 3);
1306 }
1307
1308
detect_and_report_winbond(void)1309 static void detect_and_report_winbond(void)
1310 {
1311 if (verbose_probing)
1312 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1313 winbond_check(0x3f0, 0x87);
1314 winbond_check(0x370, 0x87);
1315 winbond_check(0x2e , 0x87);
1316 winbond_check(0x4e , 0x87);
1317 winbond_check(0x3f0, 0x86);
1318 winbond_check2(0x250, 0x88);
1319 winbond_check2(0x250, 0x89);
1320 }
1321
detect_and_report_smsc(void)1322 static void detect_and_report_smsc(void)
1323 {
1324 if (verbose_probing)
1325 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1326 smsc_check(0x3f0, 0x55);
1327 smsc_check(0x370, 0x55);
1328 smsc_check(0x3f0, 0x44);
1329 smsc_check(0x370, 0x44);
1330 }
1331
detect_and_report_it87(void)1332 static void detect_and_report_it87(void)
1333 {
1334 u16 dev;
1335 u8 origval, r;
1336 if (verbose_probing)
1337 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1338 if (!request_muxed_region(0x2e, 2, __func__))
1339 return;
1340 origval = inb(0x2e); /* Save original value */
1341 outb(0x87, 0x2e);
1342 outb(0x01, 0x2e);
1343 outb(0x55, 0x2e);
1344 outb(0x55, 0x2e);
1345 outb(0x20, 0x2e);
1346 dev = inb(0x2f) << 8;
1347 outb(0x21, 0x2e);
1348 dev |= inb(0x2f);
1349 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1350 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1351 pr_info("IT%04X SuperIO detected\n", dev);
1352 outb(0x07, 0x2E); /* Parallel Port */
1353 outb(0x03, 0x2F);
1354 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1355 r = inb(0x2f);
1356 outb(0xF0, 0x2E);
1357 outb(r | 8, 0x2F);
1358 outb(0x02, 0x2E); /* Lock */
1359 outb(0x02, 0x2F);
1360 } else {
1361 outb(origval, 0x2e); /* Oops, sorry to disturb */
1362 }
1363 release_region(0x2e, 2);
1364 }
1365 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1366
find_superio(struct parport * p)1367 static struct superio_struct *find_superio(struct parport *p)
1368 {
1369 int i;
1370 for (i = 0; i < NR_SUPERIOS; i++)
1371 if (superios[i].io == p->base)
1372 return &superios[i];
1373 return NULL;
1374 }
1375
get_superio_dma(struct parport * p)1376 static int get_superio_dma(struct parport *p)
1377 {
1378 struct superio_struct *s = find_superio(p);
1379 if (s)
1380 return s->dma;
1381 return PARPORT_DMA_NONE;
1382 }
1383
get_superio_irq(struct parport * p)1384 static int get_superio_irq(struct parport *p)
1385 {
1386 struct superio_struct *s = find_superio(p);
1387 if (s)
1388 return s->irq;
1389 return PARPORT_IRQ_NONE;
1390 }
1391
1392
1393 /* --- Mode detection ------------------------------------- */
1394
1395 /*
1396 * Checks for port existence, all ports support SPP MODE
1397 * Returns:
1398 * 0 : No parallel port at this address
1399 * PARPORT_MODE_PCSPP : SPP port detected
1400 * (if the user specified an ioport himself,
1401 * this shall always be the case!)
1402 *
1403 */
parport_SPP_supported(struct parport * pb)1404 static int parport_SPP_supported(struct parport *pb)
1405 {
1406 unsigned char r, w;
1407
1408 /*
1409 * first clear an eventually pending EPP timeout
1410 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1411 * that does not even respond to SPP cycles if an EPP
1412 * timeout is pending
1413 */
1414 clear_epp_timeout(pb);
1415
1416 /* Do a simple read-write test to make sure the port exists. */
1417 w = 0xc;
1418 outb(w, CONTROL(pb));
1419
1420 /* Is there a control register that we can read from? Some
1421 * ports don't allow reads, so read_control just returns a
1422 * software copy. Some ports _do_ allow reads, so bypass the
1423 * software copy here. In addition, some bits aren't
1424 * writable. */
1425 r = inb(CONTROL(pb));
1426 if ((r & 0xf) == w) {
1427 w = 0xe;
1428 outb(w, CONTROL(pb));
1429 r = inb(CONTROL(pb));
1430 outb(0xc, CONTROL(pb));
1431 if ((r & 0xf) == w)
1432 return PARPORT_MODE_PCSPP;
1433 }
1434
1435 if (user_specified)
1436 /* That didn't work, but the user thinks there's a
1437 * port here. */
1438 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n",
1439 pb->base, w, r);
1440
1441 /* Try the data register. The data lines aren't tri-stated at
1442 * this stage, so we expect back what we wrote. */
1443 w = 0xaa;
1444 parport_pc_write_data(pb, w);
1445 r = parport_pc_read_data(pb);
1446 if (r == w) {
1447 w = 0x55;
1448 parport_pc_write_data(pb, w);
1449 r = parport_pc_read_data(pb);
1450 if (r == w)
1451 return PARPORT_MODE_PCSPP;
1452 }
1453
1454 if (user_specified) {
1455 /* Didn't work, but the user is convinced this is the
1456 * place. */
1457 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n",
1458 pb->base, w, r);
1459 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1460 pb->base);
1461 }
1462
1463 /* It's possible that we can't read the control register or
1464 * the data register. In that case just believe the user. */
1465 if (user_specified)
1466 return PARPORT_MODE_PCSPP;
1467
1468 return 0;
1469 }
1470
1471 /* Check for ECR
1472 *
1473 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1474 * on these cards actually accesses the CTR.
1475 *
1476 * Modern cards don't do this but reading from ECR will return 0xff
1477 * regardless of what is written here if the card does NOT support
1478 * ECP.
1479 *
1480 * We first check to see if ECR is the same as CTR. If not, the low
1481 * two bits of ECR aren't writable, so we check by writing ECR and
1482 * reading it back to see if it's what we expect.
1483 */
parport_ECR_present(struct parport * pb)1484 static int parport_ECR_present(struct parport *pb)
1485 {
1486 struct parport_pc_private *priv = pb->private_data;
1487 unsigned char r = 0xc;
1488
1489 if (!priv->ecr_writable) {
1490 outb(r, CONTROL(pb));
1491 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1492 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1493
1494 r = inb(CONTROL(pb));
1495 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1496 /* Sure that no ECR register exists */
1497 goto no_reg;
1498 }
1499
1500 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1501 goto no_reg;
1502
1503 ECR_WRITE(pb, 0x34);
1504 if (inb(ECONTROL(pb)) != 0x35)
1505 goto no_reg;
1506 }
1507
1508 priv->ecr = 1;
1509 outb(0xc, CONTROL(pb));
1510
1511 /* Go to mode 000 */
1512 frob_set_mode(pb, ECR_SPP);
1513
1514 return 1;
1515
1516 no_reg:
1517 outb(0xc, CONTROL(pb));
1518 return 0;
1519 }
1520
1521 #ifdef CONFIG_PARPORT_1284
1522 /* Detect PS/2 support.
1523 *
1524 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1525 * allows us to read data from the data lines. In theory we would get back
1526 * 0xff but any peripheral attached to the port may drag some or all of the
1527 * lines down to zero. So if we get back anything that isn't the contents
1528 * of the data register we deem PS/2 support to be present.
1529 *
1530 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1531 * drivers, but an external peripheral with sufficiently beefy drivers of
1532 * its own can overpower them and assert its own levels onto the bus, from
1533 * where they can then be read back as normal. Ports with this property
1534 * and the right type of device attached are likely to fail the SPP test,
1535 * (as they will appear to have stuck bits) and so the fact that they might
1536 * be misdetected here is rather academic.
1537 */
1538
parport_PS2_supported(struct parport * pb)1539 static int parport_PS2_supported(struct parport *pb)
1540 {
1541 int ok = 0;
1542
1543 clear_epp_timeout(pb);
1544
1545 /* try to tri-state the buffer */
1546 parport_pc_data_reverse(pb);
1547
1548 parport_pc_write_data(pb, 0x55);
1549 if (parport_pc_read_data(pb) != 0x55)
1550 ok++;
1551
1552 parport_pc_write_data(pb, 0xaa);
1553 if (parport_pc_read_data(pb) != 0xaa)
1554 ok++;
1555
1556 /* cancel input mode */
1557 parport_pc_data_forward(pb);
1558
1559 if (ok) {
1560 pb->modes |= PARPORT_MODE_TRISTATE;
1561 } else {
1562 struct parport_pc_private *priv = pb->private_data;
1563 priv->ctr_writable &= ~0x20;
1564 }
1565
1566 return ok;
1567 }
1568
1569 #ifdef CONFIG_PARPORT_PC_FIFO
parport_ECP_supported(struct parport * pb)1570 static int parport_ECP_supported(struct parport *pb)
1571 {
1572 int i;
1573 int config, configb;
1574 int pword;
1575 struct parport_pc_private *priv = pb->private_data;
1576 /* Translate ECP intrLine to ISA irq value */
1577 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1578
1579 /* If there is no ECR, we have no hope of supporting ECP. */
1580 if (!priv->ecr)
1581 return 0;
1582
1583 /* Find out FIFO depth */
1584 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1585 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1586 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1587 outb(0xaa, FIFO(pb));
1588
1589 /*
1590 * Using LGS chipset it uses ECR register, but
1591 * it doesn't support ECP or FIFO MODE
1592 */
1593 if (i == 1024) {
1594 ECR_WRITE(pb, ECR_SPP << 5);
1595 return 0;
1596 }
1597
1598 priv->fifo_depth = i;
1599 if (verbose_probing)
1600 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1601
1602 /* Find out writeIntrThreshold */
1603 frob_econtrol(pb, 1<<2, 1<<2);
1604 frob_econtrol(pb, 1<<2, 0);
1605 for (i = 1; i <= priv->fifo_depth; i++) {
1606 inb(FIFO(pb));
1607 udelay(50);
1608 if (inb(ECONTROL(pb)) & (1<<2))
1609 break;
1610 }
1611
1612 if (i <= priv->fifo_depth) {
1613 if (verbose_probing)
1614 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1615 pb->base, i);
1616 } else
1617 /* Number of bytes we know we can write if we get an
1618 interrupt. */
1619 i = 0;
1620
1621 priv->writeIntrThreshold = i;
1622
1623 /* Find out readIntrThreshold */
1624 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1625 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1626 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1627 frob_econtrol(pb, 1<<2, 1<<2);
1628 frob_econtrol(pb, 1<<2, 0);
1629 for (i = 1; i <= priv->fifo_depth; i++) {
1630 outb(0xaa, FIFO(pb));
1631 if (inb(ECONTROL(pb)) & (1<<2))
1632 break;
1633 }
1634
1635 if (i <= priv->fifo_depth) {
1636 if (verbose_probing)
1637 pr_info("0x%lx: readIntrThreshold is %d\n",
1638 pb->base, i);
1639 } else
1640 /* Number of bytes we can read if we get an interrupt. */
1641 i = 0;
1642
1643 priv->readIntrThreshold = i;
1644
1645 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1646 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1647 config = inb(CONFIGA(pb));
1648 pword = (config >> 4) & 0x7;
1649 switch (pword) {
1650 case 0:
1651 pword = 2;
1652 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1653 break;
1654 case 2:
1655 pword = 4;
1656 pr_warn("0x%lx: Unsupported pword size!\n", pb->base);
1657 break;
1658 default:
1659 pr_warn("0x%lx: Unknown implementation ID\n", pb->base);
1660 fallthrough; /* Assume 1 */
1661 case 1:
1662 pword = 1;
1663 }
1664 priv->pword = pword;
1665
1666 if (verbose_probing) {
1667 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1668 pb->base, 8 * pword);
1669
1670 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n",
1671 pb->base, config & 0x80 ? "Level" : "Pulses");
1672
1673 configb = inb(CONFIGB(pb));
1674 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1675 pb->base, config, configb);
1676 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1677 if ((configb >> 3) & 0x07)
1678 pr_cont("%d", intrline[(configb >> 3) & 0x07]);
1679 else
1680 pr_cont("<none or set by other means>");
1681 pr_cont(" dma=");
1682 if ((configb & 0x03) == 0x00)
1683 pr_cont("<none or set by other means>\n");
1684 else
1685 pr_cont("%d\n", configb & 0x07);
1686 }
1687
1688 /* Go back to mode 000 */
1689 frob_set_mode(pb, ECR_SPP);
1690
1691 return 1;
1692 }
1693 #endif
1694
1695 #ifdef CONFIG_X86_32
intel_bug_present_check_epp(struct parport * pb)1696 static int intel_bug_present_check_epp(struct parport *pb)
1697 {
1698 const struct parport_pc_private *priv = pb->private_data;
1699 int bug_present = 0;
1700
1701 if (priv->ecr) {
1702 /* store value of ECR */
1703 unsigned char ecr = inb(ECONTROL(pb));
1704 unsigned char i;
1705 for (i = 0x00; i < 0x80; i += 0x20) {
1706 ECR_WRITE(pb, i);
1707 if (clear_epp_timeout(pb)) {
1708 /* Phony EPP in ECP. */
1709 bug_present = 1;
1710 break;
1711 }
1712 }
1713 /* return ECR into the inital state */
1714 ECR_WRITE(pb, ecr);
1715 }
1716
1717 return bug_present;
1718 }
intel_bug_present(struct parport * pb)1719 static int intel_bug_present(struct parport *pb)
1720 {
1721 /* Check whether the device is legacy, not PCI or PCMCIA. Only legacy is known to be affected. */
1722 if (pb->dev != NULL) {
1723 return 0;
1724 }
1725
1726 return intel_bug_present_check_epp(pb);
1727 }
1728 #else
intel_bug_present(struct parport * pb)1729 static int intel_bug_present(struct parport *pb)
1730 {
1731 return 0;
1732 }
1733 #endif /* CONFIG_X86_32 */
1734
parport_ECPPS2_supported(struct parport * pb)1735 static int parport_ECPPS2_supported(struct parport *pb)
1736 {
1737 const struct parport_pc_private *priv = pb->private_data;
1738 int result;
1739 unsigned char oecr;
1740
1741 if (!priv->ecr)
1742 return 0;
1743
1744 oecr = inb(ECONTROL(pb));
1745 ECR_WRITE(pb, ECR_PS2 << 5);
1746 result = parport_PS2_supported(pb);
1747 ECR_WRITE(pb, oecr);
1748 return result;
1749 }
1750
1751 /* EPP mode detection */
1752
parport_EPP_supported(struct parport * pb)1753 static int parport_EPP_supported(struct parport *pb)
1754 {
1755 /*
1756 * Theory:
1757 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1758 * when EPP is possible and is set high when an EPP timeout
1759 * occurs (EPP uses the HALT line to stop the CPU while it does
1760 * the byte transfer, an EPP timeout occurs if the attached
1761 * device fails to respond after 10 micro seconds).
1762 *
1763 * This bit is cleared by either reading it (National Semi)
1764 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1765 * This bit is always high in non EPP modes.
1766 */
1767
1768 /* If EPP timeout bit clear then EPP available */
1769 if (!clear_epp_timeout(pb))
1770 return 0; /* No way to clear timeout */
1771
1772 /* Check for Intel bug. */
1773 if (intel_bug_present(pb))
1774 return 0;
1775
1776 pb->modes |= PARPORT_MODE_EPP;
1777
1778 /* Set up access functions to use EPP hardware. */
1779 pb->ops->epp_read_data = parport_pc_epp_read_data;
1780 pb->ops->epp_write_data = parport_pc_epp_write_data;
1781 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1782 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1783
1784 return 1;
1785 }
1786
parport_ECPEPP_supported(struct parport * pb)1787 static int parport_ECPEPP_supported(struct parport *pb)
1788 {
1789 struct parport_pc_private *priv = pb->private_data;
1790 int result;
1791 unsigned char oecr;
1792
1793 if (!priv->ecr)
1794 return 0;
1795
1796 oecr = inb(ECONTROL(pb));
1797 /* Search for SMC style EPP+ECP mode */
1798 ECR_WRITE(pb, 0x80);
1799 outb(0x04, CONTROL(pb));
1800 result = parport_EPP_supported(pb);
1801
1802 ECR_WRITE(pb, oecr);
1803
1804 if (result) {
1805 /* Set up access functions to use ECP+EPP hardware. */
1806 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1807 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1808 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1809 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1810 }
1811
1812 return result;
1813 }
1814
1815 #else /* No IEEE 1284 support */
1816
1817 /* Don't bother probing for modes we know we won't use. */
parport_PS2_supported(struct parport * pb)1818 static int parport_PS2_supported(struct parport *pb) { return 0; }
1819 #ifdef CONFIG_PARPORT_PC_FIFO
parport_ECP_supported(struct parport * pb)1820 static int parport_ECP_supported(struct parport *pb)
1821 {
1822 return 0;
1823 }
1824 #endif
parport_EPP_supported(struct parport * pb)1825 static int parport_EPP_supported(struct parport *pb)
1826 {
1827 return 0;
1828 }
1829
parport_ECPEPP_supported(struct parport * pb)1830 static int parport_ECPEPP_supported(struct parport *pb)
1831 {
1832 return 0;
1833 }
1834
parport_ECPPS2_supported(struct parport * pb)1835 static int parport_ECPPS2_supported(struct parport *pb)
1836 {
1837 return 0;
1838 }
1839
1840 #endif /* No IEEE 1284 support */
1841
1842 /* --- IRQ detection -------------------------------------- */
1843
1844 /* Only if supports ECP mode */
programmable_irq_support(struct parport * pb)1845 static int programmable_irq_support(struct parport *pb)
1846 {
1847 int irq, intrLine;
1848 unsigned char oecr = inb(ECONTROL(pb));
1849 static const int lookup[8] = {
1850 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1851 };
1852
1853 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1854
1855 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1856 irq = lookup[intrLine];
1857
1858 ECR_WRITE(pb, oecr);
1859 return irq;
1860 }
1861
irq_probe_ECP(struct parport * pb)1862 static int irq_probe_ECP(struct parport *pb)
1863 {
1864 int i;
1865 unsigned long irqs;
1866
1867 irqs = probe_irq_on();
1868
1869 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1870 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1871 ECR_WRITE(pb, ECR_TST << 5);
1872
1873 /* If Full FIFO sure that writeIntrThreshold is generated */
1874 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1875 outb(0xaa, FIFO(pb));
1876
1877 pb->irq = probe_irq_off(irqs);
1878 ECR_WRITE(pb, ECR_SPP << 5);
1879
1880 if (pb->irq <= 0)
1881 pb->irq = PARPORT_IRQ_NONE;
1882
1883 return pb->irq;
1884 }
1885
1886 /*
1887 * This detection seems that only works in National Semiconductors
1888 * This doesn't work in SMC, LGS, and Winbond
1889 */
irq_probe_EPP(struct parport * pb)1890 static int irq_probe_EPP(struct parport *pb)
1891 {
1892 #ifndef ADVANCED_DETECT
1893 return PARPORT_IRQ_NONE;
1894 #else
1895 int irqs;
1896 unsigned char oecr;
1897
1898 if (pb->modes & PARPORT_MODE_PCECR)
1899 oecr = inb(ECONTROL(pb));
1900
1901 irqs = probe_irq_on();
1902
1903 if (pb->modes & PARPORT_MODE_PCECR)
1904 frob_econtrol(pb, 0x10, 0x10);
1905
1906 clear_epp_timeout(pb);
1907 parport_pc_frob_control(pb, 0x20, 0x20);
1908 parport_pc_frob_control(pb, 0x10, 0x10);
1909 clear_epp_timeout(pb);
1910
1911 /* Device isn't expecting an EPP read
1912 * and generates an IRQ.
1913 */
1914 parport_pc_read_epp(pb);
1915 udelay(20);
1916
1917 pb->irq = probe_irq_off(irqs);
1918 if (pb->modes & PARPORT_MODE_PCECR)
1919 ECR_WRITE(pb, oecr);
1920 parport_pc_write_control(pb, 0xc);
1921
1922 if (pb->irq <= 0)
1923 pb->irq = PARPORT_IRQ_NONE;
1924
1925 return pb->irq;
1926 #endif /* Advanced detection */
1927 }
1928
irq_probe_SPP(struct parport * pb)1929 static int irq_probe_SPP(struct parport *pb)
1930 {
1931 /* Don't even try to do this. */
1932 return PARPORT_IRQ_NONE;
1933 }
1934
1935 /* We will attempt to share interrupt requests since other devices
1936 * such as sound cards and network cards seem to like using the
1937 * printer IRQs.
1938 *
1939 * When ECP is available we can autoprobe for IRQs.
1940 * NOTE: If we can autoprobe it, we can register the IRQ.
1941 */
parport_irq_probe(struct parport * pb)1942 static int parport_irq_probe(struct parport *pb)
1943 {
1944 struct parport_pc_private *priv = pb->private_data;
1945
1946 if (priv->ecr) {
1947 pb->irq = programmable_irq_support(pb);
1948
1949 if (pb->irq == PARPORT_IRQ_NONE)
1950 pb->irq = irq_probe_ECP(pb);
1951 }
1952
1953 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1954 (pb->modes & PARPORT_MODE_EPP))
1955 pb->irq = irq_probe_EPP(pb);
1956
1957 clear_epp_timeout(pb);
1958
1959 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1960 pb->irq = irq_probe_EPP(pb);
1961
1962 clear_epp_timeout(pb);
1963
1964 if (pb->irq == PARPORT_IRQ_NONE)
1965 pb->irq = irq_probe_SPP(pb);
1966
1967 if (pb->irq == PARPORT_IRQ_NONE)
1968 pb->irq = get_superio_irq(pb);
1969
1970 return pb->irq;
1971 }
1972
1973 /* --- DMA detection -------------------------------------- */
1974
1975 /* Only if chipset conforms to ECP ISA Interface Standard */
programmable_dma_support(struct parport * p)1976 static int programmable_dma_support(struct parport *p)
1977 {
1978 unsigned char oecr = inb(ECONTROL(p));
1979 int dma;
1980
1981 frob_set_mode(p, ECR_CNF);
1982
1983 dma = inb(CONFIGB(p)) & 0x07;
1984 /* 000: Indicates jumpered 8-bit DMA if read-only.
1985 100: Indicates jumpered 16-bit DMA if read-only. */
1986 if ((dma & 0x03) == 0)
1987 dma = PARPORT_DMA_NONE;
1988
1989 ECR_WRITE(p, oecr);
1990 return dma;
1991 }
1992
parport_dma_probe(struct parport * p)1993 static int parport_dma_probe(struct parport *p)
1994 {
1995 const struct parport_pc_private *priv = p->private_data;
1996 if (priv->ecr) /* ask ECP chipset first */
1997 p->dma = programmable_dma_support(p);
1998 if (p->dma == PARPORT_DMA_NONE) {
1999 /* ask known Super-IO chips proper, although these
2000 claim ECP compatible, some don't report their DMA
2001 conforming to ECP standards */
2002 p->dma = get_superio_dma(p);
2003 }
2004
2005 return p->dma;
2006 }
2007
2008 /* --- Initialisation code -------------------------------- */
2009
2010 static LIST_HEAD(ports_list);
2011 static DEFINE_SPINLOCK(ports_lock);
2012
__parport_pc_probe_port(unsigned long int base,unsigned long int base_hi,int irq,int dma,struct device * dev,int irqflags,unsigned int mode_mask,unsigned char ecr_writable)2013 static struct parport *__parport_pc_probe_port(unsigned long int base,
2014 unsigned long int base_hi,
2015 int irq, int dma,
2016 struct device *dev,
2017 int irqflags,
2018 unsigned int mode_mask,
2019 unsigned char ecr_writable)
2020 {
2021 struct parport_pc_private *priv;
2022 struct parport_operations *ops;
2023 struct parport *p;
2024 int probedirq = PARPORT_IRQ_NONE;
2025 struct resource *base_res;
2026 struct resource *ECR_res = NULL;
2027 struct resource *EPP_res = NULL;
2028 struct platform_device *pdev = NULL;
2029 int ret;
2030
2031 if (!dev) {
2032 /* We need a physical device to attach to, but none was
2033 * provided. Create our own. */
2034 pdev = platform_device_register_simple("parport_pc",
2035 base, NULL, 0);
2036 if (IS_ERR(pdev))
2037 return NULL;
2038 dev = &pdev->dev;
2039
2040 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2041 if (ret) {
2042 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2043 dma = PARPORT_DMA_NONE;
2044 }
2045 }
2046
2047 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2048 if (!ops)
2049 goto out1;
2050
2051 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2052 if (!priv)
2053 goto out2;
2054
2055 /* a misnomer, actually - it's allocate and reserve parport number */
2056 p = parport_register_port(base, irq, dma, ops);
2057 if (!p)
2058 goto out3;
2059
2060 base_res = request_region(base, 3, p->name);
2061 if (!base_res)
2062 goto out4;
2063
2064 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2065 priv->ctr = 0xc;
2066 priv->ctr_writable = ~0x10;
2067 priv->ecr = 0;
2068 priv->ecr_writable = ecr_writable;
2069 priv->fifo_depth = 0;
2070 priv->dma_buf = NULL;
2071 priv->dma_handle = 0;
2072 INIT_LIST_HEAD(&priv->list);
2073 priv->port = p;
2074
2075 p->dev = dev;
2076 p->base_hi = base_hi;
2077 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2078 p->private_data = priv;
2079
2080 if (base_hi) {
2081 ECR_res = request_region(base_hi, 3, p->name);
2082 if (ECR_res)
2083 parport_ECR_present(p);
2084 }
2085
2086 if (base != 0x3bc) {
2087 EPP_res = request_region(base+0x3, 5, p->name);
2088 if (EPP_res)
2089 if (!parport_EPP_supported(p))
2090 parport_ECPEPP_supported(p);
2091 }
2092 if (!parport_SPP_supported(p))
2093 /* No port. */
2094 goto out5;
2095 if (priv->ecr)
2096 parport_ECPPS2_supported(p);
2097 else
2098 parport_PS2_supported(p);
2099
2100 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2101
2102 pr_info("%s: PC-style at 0x%lx", p->name, p->base);
2103 if (p->base_hi && priv->ecr)
2104 pr_cont(" (0x%lx)", p->base_hi);
2105 if (p->irq == PARPORT_IRQ_AUTO) {
2106 p->irq = PARPORT_IRQ_NONE;
2107 parport_irq_probe(p);
2108 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2109 p->irq = PARPORT_IRQ_NONE;
2110 parport_irq_probe(p);
2111 probedirq = p->irq;
2112 p->irq = PARPORT_IRQ_NONE;
2113 }
2114 if (p->irq != PARPORT_IRQ_NONE) {
2115 pr_cont(", irq %d", p->irq);
2116 priv->ctr_writable |= 0x10;
2117
2118 if (p->dma == PARPORT_DMA_AUTO) {
2119 p->dma = PARPORT_DMA_NONE;
2120 parport_dma_probe(p);
2121 }
2122 }
2123 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2124 is mandatory (see above) */
2125 p->dma = PARPORT_DMA_NONE;
2126
2127 #ifdef CONFIG_PARPORT_PC_FIFO
2128 if (parport_ECP_supported(p) &&
2129 p->dma != PARPORT_DMA_NOFIFO &&
2130 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2131 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2132 if (p->dma != PARPORT_DMA_NONE)
2133 p->modes |= PARPORT_MODE_DMA;
2134 } else
2135 /* We can't use the DMA channel after all. */
2136 p->dma = PARPORT_DMA_NONE;
2137 #endif /* Allowed to use FIFO/DMA */
2138
2139 p->modes &= ~mode_mask;
2140
2141 #ifdef CONFIG_PARPORT_PC_FIFO
2142 if ((p->modes & PARPORT_MODE_COMPAT) != 0)
2143 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2144 #ifdef CONFIG_PARPORT_1284
2145 if ((p->modes & PARPORT_MODE_ECP) != 0)
2146 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2147 #endif
2148 if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) {
2149 if ((p->modes & PARPORT_MODE_DMA) != 0)
2150 pr_cont(", dma %d", p->dma);
2151 else
2152 pr_cont(", using FIFO");
2153 }
2154 #endif /* Allowed to use FIFO/DMA */
2155
2156 pr_cont(" [");
2157
2158 #define printmode(x) \
2159 do { \
2160 if (p->modes & PARPORT_MODE_##x) \
2161 pr_cont("%s%s", f++ ? "," : "", #x); \
2162 } while (0)
2163
2164 {
2165 int f = 0;
2166 printmode(PCSPP);
2167 printmode(TRISTATE);
2168 printmode(COMPAT);
2169 printmode(EPP);
2170 printmode(ECP);
2171 printmode(DMA);
2172 }
2173 #undef printmode
2174 #ifndef CONFIG_PARPORT_1284
2175 pr_cont("(,...)");
2176 #endif /* CONFIG_PARPORT_1284 */
2177 pr_cont("]\n");
2178 if (probedirq != PARPORT_IRQ_NONE)
2179 pr_info("%s: irq %d detected\n", p->name, probedirq);
2180
2181 /* If No ECP release the ports grabbed above. */
2182 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2183 release_region(base_hi, 3);
2184 ECR_res = NULL;
2185 }
2186 /* Likewise for EEP ports */
2187 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2188 release_region(base+3, 5);
2189 EPP_res = NULL;
2190 }
2191 if (p->irq != PARPORT_IRQ_NONE) {
2192 if (request_irq(p->irq, parport_irq_handler,
2193 irqflags, p->name, p)) {
2194 pr_warn("%s: irq %d in use, resorting to polled operation\n",
2195 p->name, p->irq);
2196 p->irq = PARPORT_IRQ_NONE;
2197 p->dma = PARPORT_DMA_NONE;
2198 }
2199
2200 #ifdef CONFIG_PARPORT_PC_FIFO
2201 #ifdef HAS_DMA
2202 if (p->dma != PARPORT_DMA_NONE) {
2203 if (request_dma(p->dma, p->name)) {
2204 pr_warn("%s: dma %d in use, resorting to PIO operation\n",
2205 p->name, p->dma);
2206 p->dma = PARPORT_DMA_NONE;
2207 } else {
2208 priv->dma_buf =
2209 dma_alloc_coherent(dev,
2210 PAGE_SIZE,
2211 &priv->dma_handle,
2212 GFP_KERNEL);
2213 if (!priv->dma_buf) {
2214 pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n",
2215 p->name);
2216 free_dma(p->dma);
2217 p->dma = PARPORT_DMA_NONE;
2218 }
2219 }
2220 }
2221 #endif
2222 #endif
2223 }
2224
2225 /* Done probing. Now put the port into a sensible start-up state. */
2226 if (priv->ecr)
2227 /*
2228 * Put the ECP detected port in PS2 mode.
2229 * Do this also for ports that have ECR but don't do ECP.
2230 */
2231 ECR_WRITE(p, 0x34);
2232
2233 parport_pc_write_data(p, 0);
2234 parport_pc_data_forward(p);
2235
2236 /* Now that we've told the sharing engine about the port, and
2237 found out its characteristics, let the high-level drivers
2238 know about it. */
2239 spin_lock(&ports_lock);
2240 list_add(&priv->list, &ports_list);
2241 spin_unlock(&ports_lock);
2242 parport_announce_port(p);
2243
2244 return p;
2245
2246 out5:
2247 if (ECR_res)
2248 release_region(base_hi, 3);
2249 if (EPP_res)
2250 release_region(base+0x3, 5);
2251 release_region(base, 3);
2252 out4:
2253 parport_del_port(p);
2254 out3:
2255 kfree(priv);
2256 out2:
2257 kfree(ops);
2258 out1:
2259 if (pdev)
2260 platform_device_unregister(pdev);
2261 return NULL;
2262 }
2263
parport_pc_probe_port(unsigned long int base,unsigned long int base_hi,int irq,int dma,struct device * dev,int irqflags)2264 struct parport *parport_pc_probe_port(unsigned long int base,
2265 unsigned long int base_hi,
2266 int irq, int dma,
2267 struct device *dev,
2268 int irqflags)
2269 {
2270 return __parport_pc_probe_port(base, base_hi, irq, dma,
2271 dev, irqflags, 0, 0);
2272 }
2273 EXPORT_SYMBOL(parport_pc_probe_port);
2274
parport_pc_unregister_port(struct parport * p)2275 void parport_pc_unregister_port(struct parport *p)
2276 {
2277 struct parport_pc_private *priv = p->private_data;
2278 struct parport_operations *ops = p->ops;
2279
2280 parport_remove_port(p);
2281 spin_lock(&ports_lock);
2282 list_del_init(&priv->list);
2283 spin_unlock(&ports_lock);
2284 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2285 if (p->dma != PARPORT_DMA_NONE)
2286 free_dma(p->dma);
2287 #endif
2288 if (p->irq != PARPORT_IRQ_NONE)
2289 free_irq(p->irq, p);
2290 release_region(p->base, 3);
2291 if (p->size > 3)
2292 release_region(p->base + 3, p->size - 3);
2293 if (p->modes & PARPORT_MODE_ECP)
2294 release_region(p->base_hi, 3);
2295 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2296 if (priv->dma_buf)
2297 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2298 priv->dma_buf,
2299 priv->dma_handle);
2300 #endif
2301 kfree(p->private_data);
2302 parport_del_port(p);
2303 kfree(ops); /* hope no-one cached it */
2304 }
2305 EXPORT_SYMBOL(parport_pc_unregister_port);
2306
2307 #ifdef CONFIG_PCI
2308
2309 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
sio_ite_8872_probe(struct pci_dev * pdev,int autoirq,int autodma,const struct parport_pc_via_data * via)2310 static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2311 const struct parport_pc_via_data *via)
2312 {
2313 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2314 u32 ite8872set;
2315 u32 ite8872_lpt, ite8872_lpthi;
2316 u8 ite8872_irq, type;
2317 int irq;
2318 int i;
2319
2320 pr_debug("sio_ite_8872_probe()\n");
2321
2322 /* make sure which one chip */
2323 for (i = 0; i < 5; i++) {
2324 if (request_region(inta_addr[i], 32, "it887x")) {
2325 int test;
2326 pci_write_config_dword(pdev, 0x60,
2327 0xe5000000 | inta_addr[i]);
2328 pci_write_config_dword(pdev, 0x78,
2329 0x00000000 | inta_addr[i]);
2330 test = inb(inta_addr[i]);
2331 if (test != 0xff)
2332 break;
2333 release_region(inta_addr[i], 32);
2334 }
2335 }
2336 if (i >= 5) {
2337 pr_info("parport_pc: cannot find ITE8872 INTA\n");
2338 return 0;
2339 }
2340
2341 type = inb(inta_addr[i] + 0x18);
2342 type &= 0x0f;
2343
2344 switch (type) {
2345 case 0x2:
2346 pr_info("parport_pc: ITE8871 found (1P)\n");
2347 ite8872set = 0x64200000;
2348 break;
2349 case 0xa:
2350 pr_info("parport_pc: ITE8875 found (1P)\n");
2351 ite8872set = 0x64200000;
2352 break;
2353 case 0xe:
2354 pr_info("parport_pc: ITE8872 found (2S1P)\n");
2355 ite8872set = 0x64e00000;
2356 break;
2357 case 0x6:
2358 pr_info("parport_pc: ITE8873 found (1S)\n");
2359 release_region(inta_addr[i], 32);
2360 return 0;
2361 case 0x8:
2362 pr_info("parport_pc: ITE8874 found (2S)\n");
2363 release_region(inta_addr[i], 32);
2364 return 0;
2365 default:
2366 pr_info("parport_pc: unknown ITE887x\n");
2367 pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n");
2368 release_region(inta_addr[i], 32);
2369 return 0;
2370 }
2371
2372 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2373 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2374 ite8872_lpt &= 0x0000ff00;
2375 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2376 ite8872_lpthi &= 0x0000ff00;
2377 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2378 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2379 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2380 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2381 /* SET Parallel IRQ */
2382 pci_write_config_dword(pdev, 0x9c,
2383 ite8872set | (ite8872_irq * 0x11111));
2384
2385 pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq);
2386 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2387 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi);
2388
2389 /* Let the user (or defaults) steer us away from interrupts */
2390 irq = ite8872_irq;
2391 if (autoirq != PARPORT_IRQ_AUTO)
2392 irq = PARPORT_IRQ_NONE;
2393
2394 /*
2395 * Release the resource so that parport_pc_probe_port can get it.
2396 */
2397 release_region(inta_addr[i], 32);
2398 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2399 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2400 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2401 ite8872_lpt);
2402 if (irq != PARPORT_IRQ_NONE)
2403 pr_cont(", irq=%d", irq);
2404 pr_cont("\n");
2405 return 1;
2406 }
2407
2408 return 0;
2409 }
2410
2411 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2412 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2413 static int parport_init_mode;
2414
2415 /* Data for two known VIA chips */
2416 static struct parport_pc_via_data via_686a_data = {
2417 0x51,
2418 0x50,
2419 0x85,
2420 0x02,
2421 0xE2,
2422 0xF0,
2423 0xE6
2424 };
2425 static struct parport_pc_via_data via_8231_data = {
2426 0x45,
2427 0x44,
2428 0x50,
2429 0x04,
2430 0xF2,
2431 0xFA,
2432 0xF6
2433 };
2434
sio_via_probe(struct pci_dev * pdev,int autoirq,int autodma,const struct parport_pc_via_data * via)2435 static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2436 const struct parport_pc_via_data *via)
2437 {
2438 u8 tmp, tmp2, siofunc;
2439 u8 ppcontrol = 0;
2440 int dma, irq;
2441 unsigned port1, port2;
2442 unsigned have_epp = 0;
2443
2444 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2445
2446 switch (parport_init_mode) {
2447 case 1:
2448 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2449 siofunc = VIA_FUNCTION_PARPORT_SPP;
2450 break;
2451 case 2:
2452 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2453 siofunc = VIA_FUNCTION_PARPORT_SPP;
2454 ppcontrol = VIA_PARPORT_BIDIR;
2455 break;
2456 case 3:
2457 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2458 siofunc = VIA_FUNCTION_PARPORT_EPP;
2459 ppcontrol = VIA_PARPORT_BIDIR;
2460 have_epp = 1;
2461 break;
2462 case 4:
2463 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2464 siofunc = VIA_FUNCTION_PARPORT_ECP;
2465 ppcontrol = VIA_PARPORT_BIDIR;
2466 break;
2467 case 5:
2468 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2469 siofunc = VIA_FUNCTION_PARPORT_ECP;
2470 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2471 have_epp = 1;
2472 break;
2473 default:
2474 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2475 siofunc = VIA_FUNCTION_PROBE;
2476 break;
2477 }
2478 /*
2479 * unlock super i/o configuration
2480 */
2481 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2482 tmp |= via->via_pci_superio_config_data;
2483 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2484
2485 /* Bits 1-0: Parallel Port Mode / Enable */
2486 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2487 tmp = inb(VIA_CONFIG_DATA);
2488 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2489 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2490 tmp2 = inb(VIA_CONFIG_DATA);
2491 if (siofunc == VIA_FUNCTION_PROBE) {
2492 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2493 ppcontrol = tmp2;
2494 } else {
2495 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2496 tmp |= siofunc;
2497 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2498 outb(tmp, VIA_CONFIG_DATA);
2499 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2500 tmp2 |= ppcontrol;
2501 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2502 outb(tmp2, VIA_CONFIG_DATA);
2503 }
2504
2505 /* Parallel Port I/O Base Address, bits 9-2 */
2506 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2507 port1 = inb(VIA_CONFIG_DATA) << 2;
2508
2509 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2510 port1);
2511 if (port1 == 0x3BC && have_epp) {
2512 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2513 outb((0x378 >> 2), VIA_CONFIG_DATA);
2514 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2515 port1 = 0x378;
2516 }
2517
2518 /*
2519 * lock super i/o configuration
2520 */
2521 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2522 tmp &= ~via->via_pci_superio_config_data;
2523 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2524
2525 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2526 pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2527 return 0;
2528 }
2529
2530 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2531 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2532 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2533
2534 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2535 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2536 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2537 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2538 } else
2539 /* if ECP not enabled, DMA is not enabled, assumed
2540 bogus 'dma' value */
2541 dma = PARPORT_DMA_NONE;
2542
2543 /* Let the user (or defaults) steer us away from interrupts and DMA */
2544 if (autoirq == PARPORT_IRQ_NONE) {
2545 irq = PARPORT_IRQ_NONE;
2546 dma = PARPORT_DMA_NONE;
2547 }
2548 if (autodma == PARPORT_DMA_NONE)
2549 dma = PARPORT_DMA_NONE;
2550
2551 switch (port1) {
2552 case 0x3bc:
2553 port2 = 0x7bc; break;
2554 case 0x378:
2555 port2 = 0x778; break;
2556 case 0x278:
2557 port2 = 0x678; break;
2558 default:
2559 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2560 port1);
2561 return 0;
2562 }
2563
2564 /* filter bogus IRQs */
2565 switch (irq) {
2566 case 0:
2567 case 2:
2568 case 8:
2569 case 13:
2570 irq = PARPORT_IRQ_NONE;
2571 break;
2572
2573 default: /* do nothing */
2574 break;
2575 }
2576
2577 /* finally, do the probe with values obtained */
2578 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2579 pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2580 if (irq != PARPORT_IRQ_NONE)
2581 pr_cont(", irq=%d", irq);
2582 if (dma != PARPORT_DMA_NONE)
2583 pr_cont(", dma=%d", dma);
2584 pr_cont("\n");
2585 return 1;
2586 }
2587
2588 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2589 port1, irq, dma);
2590 return 0;
2591 }
2592
2593
2594 enum parport_pc_sio_types {
2595 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2596 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2597 sio_ite_8872,
2598 last_sio
2599 };
2600
2601 /* each element directly indexed from enum list, above */
2602 static struct parport_pc_superio {
2603 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2604 const struct parport_pc_via_data *via);
2605 const struct parport_pc_via_data *via;
2606 } parport_pc_superio_info[] = {
2607 { sio_via_probe, &via_686a_data, },
2608 { sio_via_probe, &via_8231_data, },
2609 { sio_ite_8872_probe, NULL, },
2610 };
2611
2612 enum parport_pc_pci_cards {
2613 siig_1p_10x = last_sio,
2614 siig_2p_10x,
2615 siig_1p_20x,
2616 siig_2p_20x,
2617 lava_parallel,
2618 lava_parallel_dual_a,
2619 lava_parallel_dual_b,
2620 boca_ioppar,
2621 plx_9050,
2622 timedia_4006a,
2623 timedia_4014,
2624 timedia_4008a,
2625 timedia_4018,
2626 timedia_9018a,
2627 syba_2p_epp,
2628 syba_1p_ecp,
2629 titan_010l,
2630 avlab_1p,
2631 avlab_2p,
2632 oxsemi_952,
2633 oxsemi_954,
2634 oxsemi_840,
2635 oxsemi_pcie_pport,
2636 aks_0100,
2637 mobility_pp,
2638 netmos_9900,
2639 netmos_9705,
2640 netmos_9715,
2641 netmos_9755,
2642 netmos_9805,
2643 netmos_9815,
2644 netmos_9901,
2645 netmos_9865,
2646 quatech_sppxp100,
2647 wch_ch382l,
2648 };
2649
2650
2651 /* each element directly indexed from enum list, above
2652 * (but offset by last_sio) */
2653 static struct parport_pc_pci {
2654 int numports;
2655 struct { /* BAR (base address registers) numbers in the config
2656 space header */
2657 int lo;
2658 int hi;
2659 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2660 } addr[2];
2661
2662 /* Bit field of parport modes to exclude. */
2663 unsigned int mode_mask;
2664
2665 /* If non-zero, sets the bitmask of writable ECR bits. In that
2666 * case additionally bit 0 will be forcibly set on writes. */
2667 unsigned char ecr_writable;
2668
2669 /* If set, this is called immediately after pci_enable_device.
2670 * If it returns non-zero, no probing will take place and the
2671 * ports will not be used. */
2672 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2673
2674 /* If set, this is called after probing for ports. If 'failed'
2675 * is non-zero we couldn't use any of the ports. */
2676 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2677 } cards[] = {
2678 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2679 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2680 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2681 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2682 /* lava_parallel */ { 1, { { 0, -1 }, } },
2683 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2684 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2685 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2686 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2687 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2688 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2689 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2690 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2691 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2692 /* SYBA uses fixed offsets in
2693 a 1K io window */
2694 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2695 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2696 /* titan_010l */ { 1, { { 3, -1 }, } },
2697 /* avlab_1p */ { 1, { { 0, 1}, } },
2698 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2699 /* The Oxford Semi cards are unusual: older variants of 954 don't
2700 * support ECP, and 840 locks up if you write 1 to bit 2! None
2701 * implement nFault or service interrupts and all require 00001
2702 * bit pattern to be used for bits 4:0 with ECR writes. */
2703 /* oxsemi_952 */ { 1, { { 0, 1 }, },
2704 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2705 /* oxsemi_954 */ { 1, { { 0, 1 }, },
2706 PARPORT_MODE_ECP |
2707 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2708 /* oxsemi_840 */ { 1, { { 0, 1 }, },
2709 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2710 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, },
2711 PARPORT_MODE_COMPAT, ECR_MODE_MASK },
2712 /* aks_0100 */ { 1, { { 0, -1 }, } },
2713 /* mobility_pp */ { 1, { { 0, 1 }, } },
2714 /* netmos_9900 */ { 1, { { 0, -1 }, } },
2715
2716 /* The netmos entries below are untested */
2717 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2718 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2719 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2720 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2721 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2722 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2723 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2724 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2725 /* wch_ch382l */ { 1, { { 2, -1 }, } },
2726 };
2727
2728 static const struct pci_device_id parport_pc_pci_tbl[] = {
2729 /* Super-IO onboard chips */
2730 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2731 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2732 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2734
2735 /* PCI cards */
2736 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2738 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2740 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2742 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2744 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2746 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2748 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2750 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2752 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2753 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2754 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2755 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2756 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2757 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2758 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2759 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2760 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2762 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2764 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2766 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2767 /* AFAVLAB_TK9902 */
2768 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2769 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2770 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2772 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2774 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2776 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2778 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2780 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2782 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2784 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2786 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2788 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2790 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2792 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2794 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2795 /* NetMos communication controllers */
2796 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
2797 0xA000, 0x2000, 0, 0, netmos_9900 },
2798 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2800 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2802 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2804 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2806 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2808 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2809 0xA000, 0x2000, 0, 0, netmos_9901 },
2810 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2811 0xA000, 0x1000, 0, 0, netmos_9865 },
2812 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2813 0xA000, 0x2000, 0, 0, netmos_9865 },
2814 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2815 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2817 /* WCH CH382L PCI-E single parallel port card */
2818 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2819 { 0, } /* terminate list */
2820 };
2821 MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2822
2823 struct pci_parport_data {
2824 int num;
2825 struct parport *ports[2];
2826 };
2827
parport_pc_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)2828 static int parport_pc_pci_probe(struct pci_dev *dev,
2829 const struct pci_device_id *id)
2830 {
2831 int err, count, n, i = id->driver_data;
2832 struct pci_parport_data *data;
2833
2834 if (i < last_sio)
2835 /* This is an onboard Super-IO and has already been probed */
2836 return 0;
2837
2838 /* This is a PCI card */
2839 i -= last_sio;
2840 count = 0;
2841 err = pci_enable_device(dev);
2842 if (err)
2843 return err;
2844
2845 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2846 if (!data)
2847 return -ENOMEM;
2848
2849 if (cards[i].preinit_hook &&
2850 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2851 kfree(data);
2852 return -ENODEV;
2853 }
2854
2855 for (n = 0; n < cards[i].numports; n++) {
2856 int lo = cards[i].addr[n].lo;
2857 int hi = cards[i].addr[n].hi;
2858 int irq;
2859 unsigned long io_lo, io_hi;
2860 io_lo = pci_resource_start(dev, lo);
2861 io_hi = 0;
2862 if ((hi >= 0) && (hi <= 6))
2863 io_hi = pci_resource_start(dev, hi);
2864 else if (hi > 6)
2865 io_lo += hi; /* Reinterpret the meaning of
2866 "hi" as an offset (see SYBA
2867 def.) */
2868 /* TODO: test if sharing interrupts works */
2869 irq = dev->irq;
2870 if (irq == IRQ_NONE) {
2871 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2872 id->vendor, id->device, io_lo, io_hi);
2873 irq = PARPORT_IRQ_NONE;
2874 } else {
2875 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2876 id->vendor, id->device, io_lo, io_hi, irq);
2877 }
2878 data->ports[count] =
2879 __parport_pc_probe_port(io_lo, io_hi, irq,
2880 PARPORT_DMA_NONE, &dev->dev,
2881 IRQF_SHARED,
2882 cards[i].mode_mask,
2883 cards[i].ecr_writable);
2884 if (data->ports[count])
2885 count++;
2886 }
2887
2888 data->num = count;
2889
2890 if (cards[i].postinit_hook)
2891 cards[i].postinit_hook(dev, count == 0);
2892
2893 if (count) {
2894 pci_set_drvdata(dev, data);
2895 return 0;
2896 }
2897
2898 kfree(data);
2899
2900 return -ENODEV;
2901 }
2902
parport_pc_pci_remove(struct pci_dev * dev)2903 static void parport_pc_pci_remove(struct pci_dev *dev)
2904 {
2905 struct pci_parport_data *data = pci_get_drvdata(dev);
2906 int i;
2907
2908 if (data) {
2909 for (i = data->num - 1; i >= 0; i--)
2910 parport_pc_unregister_port(data->ports[i]);
2911
2912 kfree(data);
2913 }
2914 }
2915
2916 static struct pci_driver parport_pc_pci_driver = {
2917 .name = "parport_pc",
2918 .id_table = parport_pc_pci_tbl,
2919 .probe = parport_pc_pci_probe,
2920 .remove = parport_pc_pci_remove,
2921 };
2922
parport_pc_init_superio(int autoirq,int autodma)2923 static int __init parport_pc_init_superio(int autoirq, int autodma)
2924 {
2925 const struct pci_device_id *id;
2926 struct pci_dev *pdev = NULL;
2927 int ret = 0;
2928
2929 for_each_pci_dev(pdev) {
2930 id = pci_match_id(parport_pc_pci_tbl, pdev);
2931 if (id == NULL || id->driver_data >= last_sio)
2932 continue;
2933
2934 if (parport_pc_superio_info[id->driver_data].probe(
2935 pdev, autoirq, autodma,
2936 parport_pc_superio_info[id->driver_data].via)) {
2937 ret++;
2938 }
2939 }
2940
2941 return ret; /* number of devices found */
2942 }
2943 #else
2944 static struct pci_driver parport_pc_pci_driver;
parport_pc_init_superio(int autoirq,int autodma)2945 static int __init parport_pc_init_superio(int autoirq, int autodma)
2946 {
2947 return 0;
2948 }
2949 #endif /* CONFIG_PCI */
2950
2951 #ifdef CONFIG_PNP
2952
2953 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2954 /* Standard LPT Printer Port */
2955 {.id = "PNP0400", .driver_data = 0},
2956 /* ECP Printer Port */
2957 {.id = "PNP0401", .driver_data = 0},
2958 { }
2959 };
2960
2961 MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2962
parport_pc_pnp_probe(struct pnp_dev * dev,const struct pnp_device_id * id)2963 static int parport_pc_pnp_probe(struct pnp_dev *dev,
2964 const struct pnp_device_id *id)
2965 {
2966 struct parport *pdata;
2967 unsigned long io_lo, io_hi;
2968 int dma, irq;
2969
2970 if (pnp_port_valid(dev, 0) &&
2971 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2972 io_lo = pnp_port_start(dev, 0);
2973 } else
2974 return -EINVAL;
2975
2976 if (pnp_port_valid(dev, 1) &&
2977 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2978 io_hi = pnp_port_start(dev, 1);
2979 } else
2980 io_hi = 0;
2981
2982 if (pnp_irq_valid(dev, 0) &&
2983 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2984 irq = pnp_irq(dev, 0);
2985 } else
2986 irq = PARPORT_IRQ_NONE;
2987
2988 if (pnp_dma_valid(dev, 0) &&
2989 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2990 dma = pnp_dma(dev, 0);
2991 } else
2992 dma = PARPORT_DMA_NONE;
2993
2994 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2995 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2996 if (pdata == NULL)
2997 return -ENODEV;
2998
2999 pnp_set_drvdata(dev, pdata);
3000 return 0;
3001 }
3002
parport_pc_pnp_remove(struct pnp_dev * dev)3003 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3004 {
3005 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3006 if (!pdata)
3007 return;
3008
3009 parport_pc_unregister_port(pdata);
3010 }
3011
3012 /* we only need the pnp layer to activate the device, at least for now */
3013 static struct pnp_driver parport_pc_pnp_driver = {
3014 .name = "parport_pc",
3015 .id_table = parport_pc_pnp_tbl,
3016 .probe = parport_pc_pnp_probe,
3017 .remove = parport_pc_pnp_remove,
3018 };
3019
3020 #else
3021 static struct pnp_driver parport_pc_pnp_driver;
3022 #endif /* CONFIG_PNP */
3023
parport_pc_platform_probe(struct platform_device * pdev)3024 static int parport_pc_platform_probe(struct platform_device *pdev)
3025 {
3026 /* Always succeed, the actual probing is done in
3027 * parport_pc_probe_port(). */
3028 return 0;
3029 }
3030
3031 static struct platform_driver parport_pc_platform_driver = {
3032 .driver = {
3033 .name = "parport_pc",
3034 },
3035 .probe = parport_pc_platform_probe,
3036 };
3037
3038 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3039 static int __attribute__((unused))
parport_pc_find_isa_ports(int autoirq,int autodma)3040 parport_pc_find_isa_ports(int autoirq, int autodma)
3041 {
3042 int count = 0;
3043
3044 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3045 count++;
3046 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3047 count++;
3048 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3049 count++;
3050
3051 return count;
3052 }
3053
3054 /* This function is called by parport_pc_init if the user didn't
3055 * specify any ports to probe. Its job is to find some ports. Order
3056 * is important here -- we want ISA ports to be registered first,
3057 * followed by PCI cards (for least surprise), but before that we want
3058 * to do chipset-specific tests for some onboard ports that we know
3059 * about.
3060 *
3061 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3062 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3063 */
parport_pc_find_ports(int autoirq,int autodma)3064 static void __init parport_pc_find_ports(int autoirq, int autodma)
3065 {
3066 int count = 0, err;
3067
3068 #ifdef CONFIG_PARPORT_PC_SUPERIO
3069 detect_and_report_it87();
3070 detect_and_report_winbond();
3071 detect_and_report_smsc();
3072 #endif
3073
3074 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3075 count += parport_pc_init_superio(autoirq, autodma);
3076
3077 /* PnP ports, skip detection if SuperIO already found them */
3078 if (!count) {
3079 err = pnp_register_driver(&parport_pc_pnp_driver);
3080 if (!err)
3081 pnp_registered_parport = 1;
3082 }
3083
3084 /* ISA ports and whatever (see asm/parport.h). */
3085 parport_pc_find_nonpci_ports(autoirq, autodma);
3086
3087 err = pci_register_driver(&parport_pc_pci_driver);
3088 if (!err)
3089 pci_registered_parport = 1;
3090 }
3091
3092 /*
3093 * Piles of crap below pretend to be a parser for module and kernel
3094 * parameters. Say "thank you" to whoever had come up with that
3095 * syntax and keep in mind that code below is a cleaned up version.
3096 */
3097
3098 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3099 [0 ... PARPORT_PC_MAX_PORTS] = 0
3100 };
3101 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3102 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3103 };
3104 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3105 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3106 };
3107 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3108 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3109 };
3110
parport_parse_param(const char * s,int * val,int automatic,int none,int nofifo)3111 static int __init parport_parse_param(const char *s, int *val,
3112 int automatic, int none, int nofifo)
3113 {
3114 if (!s)
3115 return 0;
3116 if (!strncmp(s, "auto", 4))
3117 *val = automatic;
3118 else if (!strncmp(s, "none", 4))
3119 *val = none;
3120 else if (nofifo && !strncmp(s, "nofifo", 6))
3121 *val = nofifo;
3122 else {
3123 char *ep;
3124 unsigned long r = simple_strtoul(s, &ep, 0);
3125 if (ep != s)
3126 *val = r;
3127 else {
3128 pr_err("parport: bad specifier `%s'\n", s);
3129 return -1;
3130 }
3131 }
3132 return 0;
3133 }
3134
parport_parse_irq(const char * irqstr,int * val)3135 static int __init parport_parse_irq(const char *irqstr, int *val)
3136 {
3137 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3138 PARPORT_IRQ_NONE, 0);
3139 }
3140
parport_parse_dma(const char * dmastr,int * val)3141 static int __init parport_parse_dma(const char *dmastr, int *val)
3142 {
3143 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3144 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3145 }
3146
3147 #ifdef CONFIG_PCI
parport_init_mode_setup(char * str)3148 static int __init parport_init_mode_setup(char *str)
3149 {
3150 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n",
3151 str);
3152
3153 if (!strcmp(str, "spp"))
3154 parport_init_mode = 1;
3155 if (!strcmp(str, "ps2"))
3156 parport_init_mode = 2;
3157 if (!strcmp(str, "epp"))
3158 parport_init_mode = 3;
3159 if (!strcmp(str, "ecp"))
3160 parport_init_mode = 4;
3161 if (!strcmp(str, "ecpepp"))
3162 parport_init_mode = 5;
3163 return 1;
3164 }
3165 #endif
3166
3167 #ifdef MODULE
3168 static char *irq[PARPORT_PC_MAX_PORTS];
3169 static char *dma[PARPORT_PC_MAX_PORTS];
3170
3171 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3172 module_param_hw_array(io, int, ioport, NULL, 0);
3173 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3174 module_param_hw_array(io_hi, int, ioport, NULL, 0);
3175 MODULE_PARM_DESC(irq, "IRQ line");
3176 module_param_hw_array(irq, charp, irq, NULL, 0);
3177 MODULE_PARM_DESC(dma, "DMA channel");
3178 module_param_hw_array(dma, charp, dma, NULL, 0);
3179 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3180 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3181 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3182 module_param(verbose_probing, int, 0644);
3183 #endif
3184 #ifdef CONFIG_PCI
3185 static char *init_mode;
3186 MODULE_PARM_DESC(init_mode,
3187 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3188 module_param(init_mode, charp, 0);
3189 #endif
3190
parse_parport_params(void)3191 static int __init parse_parport_params(void)
3192 {
3193 unsigned int i;
3194 int val;
3195
3196 #ifdef CONFIG_PCI
3197 if (init_mode)
3198 parport_init_mode_setup(init_mode);
3199 #endif
3200
3201 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3202 if (parport_parse_irq(irq[i], &val))
3203 return 1;
3204 irqval[i] = val;
3205 if (parport_parse_dma(dma[i], &val))
3206 return 1;
3207 dmaval[i] = val;
3208 }
3209 if (!io[0]) {
3210 /* The user can make us use any IRQs or DMAs we find. */
3211 if (irq[0] && !parport_parse_irq(irq[0], &val))
3212 switch (val) {
3213 case PARPORT_IRQ_NONE:
3214 case PARPORT_IRQ_AUTO:
3215 irqval[0] = val;
3216 break;
3217 default:
3218 pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n");
3219 }
3220
3221 if (dma[0] && !parport_parse_dma(dma[0], &val))
3222 switch (val) {
3223 case PARPORT_DMA_NONE:
3224 case PARPORT_DMA_AUTO:
3225 dmaval[0] = val;
3226 break;
3227 default:
3228 pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n");
3229 }
3230 }
3231 return 0;
3232 }
3233
3234 #else
3235
3236 static int parport_setup_ptr __initdata;
3237
3238 /*
3239 * Acceptable parameters:
3240 *
3241 * parport=0
3242 * parport=auto
3243 * parport=0xBASE[,IRQ[,DMA]]
3244 *
3245 * IRQ/DMA may be numeric or 'auto' or 'none'
3246 */
parport_setup(char * str)3247 static int __init parport_setup(char *str)
3248 {
3249 char *endptr;
3250 char *sep;
3251 int val;
3252
3253 if (!str || !*str || (*str == '0' && !*(str+1))) {
3254 /* Disable parport if "parport=0" in cmdline */
3255 io[0] = PARPORT_DISABLE;
3256 return 1;
3257 }
3258
3259 if (!strncmp(str, "auto", 4)) {
3260 irqval[0] = PARPORT_IRQ_AUTO;
3261 dmaval[0] = PARPORT_DMA_AUTO;
3262 return 1;
3263 }
3264
3265 val = simple_strtoul(str, &endptr, 0);
3266 if (endptr == str) {
3267 pr_warn("parport=%s not understood\n", str);
3268 return 1;
3269 }
3270
3271 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3272 pr_err("parport=%s ignored, too many ports\n", str);
3273 return 1;
3274 }
3275
3276 io[parport_setup_ptr] = val;
3277 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3278 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3279
3280 sep = strchr(str, ',');
3281 if (sep++) {
3282 if (parport_parse_irq(sep, &val))
3283 return 1;
3284 irqval[parport_setup_ptr] = val;
3285 sep = strchr(sep, ',');
3286 if (sep++) {
3287 if (parport_parse_dma(sep, &val))
3288 return 1;
3289 dmaval[parport_setup_ptr] = val;
3290 }
3291 }
3292 parport_setup_ptr++;
3293 return 1;
3294 }
3295
parse_parport_params(void)3296 static int __init parse_parport_params(void)
3297 {
3298 return io[0] == PARPORT_DISABLE;
3299 }
3300
3301 __setup("parport=", parport_setup);
3302
3303 /*
3304 * Acceptable parameters:
3305 *
3306 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3307 */
3308 #ifdef CONFIG_PCI
3309 __setup("parport_init_mode=", parport_init_mode_setup);
3310 #endif
3311 #endif
3312
3313 /* "Parser" ends here */
3314
parport_pc_init(void)3315 static int __init parport_pc_init(void)
3316 {
3317 int err;
3318
3319 if (parse_parport_params())
3320 return -EINVAL;
3321
3322 err = platform_driver_register(&parport_pc_platform_driver);
3323 if (err)
3324 return err;
3325
3326 if (io[0]) {
3327 int i;
3328 /* Only probe the ports we were given. */
3329 user_specified = 1;
3330 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3331 if (!io[i])
3332 break;
3333 if (io_hi[i] == PARPORT_IOHI_AUTO)
3334 io_hi[i] = 0x400 + io[i];
3335 parport_pc_probe_port(io[i], io_hi[i],
3336 irqval[i], dmaval[i], NULL, 0);
3337 }
3338 } else
3339 parport_pc_find_ports(irqval[0], dmaval[0]);
3340
3341 return 0;
3342 }
3343
parport_pc_exit(void)3344 static void __exit parport_pc_exit(void)
3345 {
3346 if (pci_registered_parport)
3347 pci_unregister_driver(&parport_pc_pci_driver);
3348 if (pnp_registered_parport)
3349 pnp_unregister_driver(&parport_pc_pnp_driver);
3350 platform_driver_unregister(&parport_pc_platform_driver);
3351
3352 while (!list_empty(&ports_list)) {
3353 struct parport_pc_private *priv;
3354 struct parport *port;
3355 struct device *dev;
3356 priv = list_entry(ports_list.next,
3357 struct parport_pc_private, list);
3358 port = priv->port;
3359 dev = port->dev;
3360 parport_pc_unregister_port(port);
3361 if (dev && dev->bus == &platform_bus_type)
3362 platform_device_unregister(to_platform_device(dev));
3363 }
3364 }
3365
3366 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3367 MODULE_DESCRIPTION("PC-style parallel port driver");
3368 MODULE_LICENSE("GPL");
3369 module_init(parport_pc_init)
3370 module_exit(parport_pc_exit)
3371