1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
43
44 #include <linux/pci_ids.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
pci_slot_name(const struct pci_slot * slot)84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 };
135
136 /**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153 };
154
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
157
158 /*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
167 /*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
171 typedef int __bitwise pci_power_t;
172
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
180
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
183
pci_power_name(pci_power_t state)184 static inline const char *pci_power_name(pci_power_t state)
185 {
186 return pci_power_names[1 + (__force int) state];
187 }
188
189 /**
190 * typedef pci_channel_state_t
191 *
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
195 */
196 typedef unsigned int __bitwise pci_channel_state_t;
197
198 enum {
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207 };
208
209 typedef unsigned int __bitwise pcie_reset_state_t;
210
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220 };
221
222 typedef unsigned short __bitwise pci_dev_flags_t;
223 enum pci_dev_flags {
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248 };
249
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
253 };
254
255 typedef unsigned short __bitwise pci_bus_flags_t;
256 enum pci_bus_flags {
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
261 };
262
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
266 PCIE_LNK_X1 = 0x01,
267 PCIE_LNK_X2 = 0x02,
268 PCIE_LNK_X4 = 0x04,
269 PCIE_LNK_X8 = 0x08,
270 PCIE_LNK_X12 = 0x0c,
271 PCIE_LNK_X16 = 0x10,
272 PCIE_LNK_X32 = 0x20,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
274 };
275
276 /* See matching string table in pci_speed_string() */
277 enum pci_bus_speed {
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
289 AGP_UNKNOWN = 0x0c,
290 AGP_1X = 0x0d,
291 AGP_2X = 0x0e,
292 AGP_4X = 0x0f,
293 AGP_8X = 0x10,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
304 };
305
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
308
309 struct pci_vpd {
310 struct mutex lock;
311 unsigned int len;
312 u8 cap;
313 };
314
315 struct irq_affinity;
316 struct pcie_link_state;
317 struct pci_sriov;
318 struct pci_p2pdma;
319 struct rcec_ea;
320
321 /* The pci_dev structure describes PCI devices */
322 struct pci_dev {
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
326
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
330
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
342 #endif
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
346 #endif
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
363
364 struct device_dma_parameters dma_parms;
365
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 unsigned int imm_ready:1; /* Supports Immediate Readiness */
370 u8 pm_cap; /* PM capability offset */
371 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 can be generated */
373 unsigned int pme_poll:1; /* Poll device's PME status bit */
374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
382 unsigned int wakeup_prepared:1;
383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
387 user sysfs */
388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 bit manually */
390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
392
393 #ifdef CONFIG_PCIEASPM
394 struct pcie_link_state *link_state; /* ASPM link state */
395 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 supported from root to here */
397 u16 l1ss; /* L1SS Capability pointer */
398 #endif
399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
401
402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
404
405 int cfg_size; /* Size of config space */
406
407 /*
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
410 */
411 unsigned int irq;
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
414
415 bool match_driver; /* Skip attaching driver */
416
417 unsigned int transparent:1; /* Subtractive decode bridge */
418 unsigned int io_window:1; /* Bridge has I/O window */
419 unsigned int pref_window:1; /* Bridge has pref mem window */
420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
421 unsigned int multifunction:1; /* Multi-function device */
422
423 unsigned int is_busmaster:1; /* Is busmaster */
424 unsigned int no_msi:1; /* May not use MSI */
425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
426 unsigned int block_cfg_access:1; /* Config space access blocked */
427 unsigned int broken_parity_status:1; /* Generates false positive parity */
428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
429 unsigned int msi_enabled:1;
430 unsigned int msix_enabled:1;
431 unsigned int ari_enabled:1; /* ARI forwarding */
432 unsigned int ats_enabled:1; /* Address Translation Svc */
433 unsigned int pasid_enabled:1; /* Process Address Space ID */
434 unsigned int pri_enabled:1; /* Page Request Interface */
435 unsigned int is_managed:1; /* Managed via devres */
436 unsigned int is_msi_managed:1; /* MSI release via devres installed */
437 unsigned int needs_freset:1; /* Requires fundamental reset */
438 unsigned int state_saved:1;
439 unsigned int is_physfn:1;
440 unsigned int is_virtfn:1;
441 unsigned int is_hotplug_bridge:1;
442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
444 /*
445 * Devices marked being untrusted are the ones that can potentially
446 * execute DMA attacks and similar. They are typically connected
447 * through external ports such as Thunderbolt but not limited to
448 * that. When an IOMMU is enabled they should be getting full
449 * mappings to make sure they cannot access arbitrary memory.
450 */
451 unsigned int untrusted:1;
452 /*
453 * Info from the platform, e.g., ACPI or device tree, may mark a
454 * device as "external-facing". An external-facing device is
455 * itself internal but devices downstream from it are external.
456 */
457 unsigned int external_facing:1;
458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
460 unsigned int irq_managed:1;
461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
462 unsigned int is_probed:1; /* Device probing in progress */
463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
467 pci_dev_flags_t dev_flags;
468 atomic_t enable_cnt; /* pci_enable_device has been called */
469
470 u32 saved_config_space[16]; /* Config space saved at suspend time */
471 struct hlist_head saved_cap_space;
472 int rom_attr_enabled; /* Display of ROM attribute enabled? */
473 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
474 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
475
476 #ifdef CONFIG_HOTPLUG_PCI_PCIE
477 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
478 #endif
479 #ifdef CONFIG_PCIE_PTM
480 u16 ptm_cap; /* PTM Capability */
481 unsigned int ptm_root:1;
482 unsigned int ptm_enabled:1;
483 u8 ptm_granularity;
484 #endif
485 #ifdef CONFIG_PCI_MSI
486 void __iomem *msix_base;
487 raw_spinlock_t msi_lock;
488 #endif
489 struct pci_vpd vpd;
490 #ifdef CONFIG_PCIE_DPC
491 u16 dpc_cap;
492 unsigned int dpc_rp_extensions:1;
493 u8 dpc_rp_log_size;
494 #endif
495 #ifdef CONFIG_PCI_ATS
496 union {
497 struct pci_sriov *sriov; /* PF: SR-IOV info */
498 struct pci_dev *physfn; /* VF: related PF */
499 };
500 u16 ats_cap; /* ATS Capability offset */
501 u8 ats_stu; /* ATS Smallest Translation Unit */
502 #endif
503 #ifdef CONFIG_PCI_PRI
504 u16 pri_cap; /* PRI Capability offset */
505 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
506 unsigned int pasid_required:1; /* PRG Response PASID Required */
507 #endif
508 #ifdef CONFIG_PCI_PASID
509 u16 pasid_cap; /* PASID Capability offset */
510 u16 pasid_features;
511 #endif
512 #ifdef CONFIG_PCI_P2PDMA
513 struct pci_p2pdma __rcu *p2pdma;
514 #endif
515 u16 acs_cap; /* ACS Capability offset */
516 phys_addr_t rom; /* Physical address if not from BAR */
517 size_t romlen; /* Length if not from BAR */
518 /*
519 * Driver name to force a match. Do not set directly, because core
520 * frees it. Use driver_set_override() to set or clear it.
521 */
522 const char *driver_override;
523
524 unsigned long priv_flags; /* Private flags for the PCI driver */
525
526 /* These methods index pci_reset_fn_methods[] */
527 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
528 };
529
pci_physfn(struct pci_dev * dev)530 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
531 {
532 #ifdef CONFIG_PCI_IOV
533 if (dev->is_virtfn)
534 dev = dev->physfn;
535 #endif
536 return dev;
537 }
538
539 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
540
541 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
542 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
543
pci_channel_offline(struct pci_dev * pdev)544 static inline int pci_channel_offline(struct pci_dev *pdev)
545 {
546 return (pdev->error_state != pci_channel_io_normal);
547 }
548
549 /*
550 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
551 * Group number is limited to a 16-bit value, therefore (int)-1 is
552 * not a valid PCI domain number, and can be used as a sentinel
553 * value indicating ->domain_nr is not set by the driver (and
554 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
555 * pci_bus_find_domain_nr()).
556 */
557 #define PCI_DOMAIN_NR_NOT_SET (-1)
558
559 struct pci_host_bridge {
560 struct device dev;
561 struct pci_bus *bus; /* Root bus */
562 struct pci_ops *ops;
563 struct pci_ops *child_ops;
564 void *sysdata;
565 int busnr;
566 int domain_nr;
567 struct list_head windows; /* resource_entry */
568 struct list_head dma_ranges; /* dma ranges resource list */
569 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
570 int (*map_irq)(const struct pci_dev *, u8, u8);
571 void (*release_fn)(struct pci_host_bridge *);
572 void *release_data;
573 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
574 unsigned int no_ext_tags:1; /* No Extended Tags */
575 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
576 unsigned int native_aer:1; /* OS may use PCIe AER */
577 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
578 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
579 unsigned int native_pme:1; /* OS may use PCIe PME */
580 unsigned int native_ltr:1; /* OS may use PCIe LTR */
581 unsigned int native_dpc:1; /* OS may use PCIe DPC */
582 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
583 unsigned int preserve_config:1; /* Preserve FW resource setup */
584 unsigned int size_windows:1; /* Enable root bus sizing */
585 unsigned int msi_domain:1; /* Bridge wants MSI domain */
586
587 /* Resource alignment requirements */
588 resource_size_t (*align_resource)(struct pci_dev *dev,
589 const struct resource *res,
590 resource_size_t start,
591 resource_size_t size,
592 resource_size_t align);
593 unsigned long private[] ____cacheline_aligned;
594 };
595
596 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
597
pci_host_bridge_priv(struct pci_host_bridge * bridge)598 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
599 {
600 return (void *)bridge->private;
601 }
602
pci_host_bridge_from_priv(void * priv)603 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
604 {
605 return container_of(priv, struct pci_host_bridge, private);
606 }
607
608 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
609 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
610 size_t priv);
611 void pci_free_host_bridge(struct pci_host_bridge *bridge);
612 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
613
614 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
615 void (*release_fn)(struct pci_host_bridge *),
616 void *release_data);
617
618 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
619
620 /*
621 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
622 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
623 * buses below host bridges or subtractive decode bridges) go in the list.
624 * Use pci_bus_for_each_resource() to iterate through all the resources.
625 */
626
627 /*
628 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
629 * and there's no way to program the bridge with the details of the window.
630 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
631 * decode bit set, because they are explicit and can be programmed with _SRS.
632 */
633 #define PCI_SUBTRACTIVE_DECODE 0x1
634
635 struct pci_bus_resource {
636 struct list_head list;
637 struct resource *res;
638 unsigned int flags;
639 };
640
641 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
642
643 struct pci_bus {
644 struct list_head node; /* Node in list of buses */
645 struct pci_bus *parent; /* Parent bus this bridge is on */
646 struct list_head children; /* List of child buses */
647 struct list_head devices; /* List of devices on this bus */
648 struct pci_dev *self; /* Bridge device as seen by parent */
649 struct list_head slots; /* List of slots on this bus;
650 protected by pci_slot_mutex */
651 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
652 struct list_head resources; /* Address space routed to this bus */
653 struct resource busn_res; /* Bus numbers routed to this bus */
654
655 struct pci_ops *ops; /* Configuration access functions */
656 void *sysdata; /* Hook for sys-specific extension */
657 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
658
659 unsigned char number; /* Bus number */
660 unsigned char primary; /* Number of primary bridge */
661 unsigned char max_bus_speed; /* enum pci_bus_speed */
662 unsigned char cur_bus_speed; /* enum pci_bus_speed */
663 #ifdef CONFIG_PCI_DOMAINS_GENERIC
664 int domain_nr;
665 #endif
666
667 char name[48];
668
669 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
670 pci_bus_flags_t bus_flags; /* Inherited by child buses */
671 struct device *bridge;
672 struct device dev;
673 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
674 struct bin_attribute *legacy_mem; /* Legacy mem */
675 unsigned int is_added:1;
676 unsigned int unsafe_warn:1; /* warned about RW1C config write */
677 };
678
679 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
680
pci_dev_id(struct pci_dev * dev)681 static inline u16 pci_dev_id(struct pci_dev *dev)
682 {
683 return PCI_DEVID(dev->bus->number, dev->devfn);
684 }
685
686 /*
687 * Returns true if the PCI bus is root (behind host-PCI bridge),
688 * false otherwise
689 *
690 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
691 * This is incorrect because "virtual" buses added for SR-IOV (via
692 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
693 */
pci_is_root_bus(struct pci_bus * pbus)694 static inline bool pci_is_root_bus(struct pci_bus *pbus)
695 {
696 return !(pbus->parent);
697 }
698
699 /**
700 * pci_is_bridge - check if the PCI device is a bridge
701 * @dev: PCI device
702 *
703 * Return true if the PCI device is bridge whether it has subordinate
704 * or not.
705 */
pci_is_bridge(struct pci_dev * dev)706 static inline bool pci_is_bridge(struct pci_dev *dev)
707 {
708 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
709 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
710 }
711
712 #define for_each_pci_bridge(dev, bus) \
713 list_for_each_entry(dev, &bus->devices, bus_list) \
714 if (!pci_is_bridge(dev)) {} else
715
pci_upstream_bridge(struct pci_dev * dev)716 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
717 {
718 dev = pci_physfn(dev);
719 if (pci_is_root_bus(dev->bus))
720 return NULL;
721
722 return dev->bus->self;
723 }
724
725 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)726 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
727 {
728 return pci_dev->msi_enabled || pci_dev->msix_enabled;
729 }
730 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)731 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
732 #endif
733
734 /* Error values that may be returned by PCI functions */
735 #define PCIBIOS_SUCCESSFUL 0x00
736 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
737 #define PCIBIOS_BAD_VENDOR_ID 0x83
738 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
739 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
740 #define PCIBIOS_SET_FAILED 0x88
741 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
742
743 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)744 static inline int pcibios_err_to_errno(int err)
745 {
746 if (err <= PCIBIOS_SUCCESSFUL)
747 return err; /* Assume already errno */
748
749 switch (err) {
750 case PCIBIOS_FUNC_NOT_SUPPORTED:
751 return -ENOENT;
752 case PCIBIOS_BAD_VENDOR_ID:
753 return -ENOTTY;
754 case PCIBIOS_DEVICE_NOT_FOUND:
755 return -ENODEV;
756 case PCIBIOS_BAD_REGISTER_NUMBER:
757 return -EFAULT;
758 case PCIBIOS_SET_FAILED:
759 return -EIO;
760 case PCIBIOS_BUFFER_TOO_SMALL:
761 return -ENOSPC;
762 }
763
764 return -ERANGE;
765 }
766
767 /* Low-level architecture-dependent routines */
768
769 struct pci_ops {
770 int (*add_bus)(struct pci_bus *bus);
771 void (*remove_bus)(struct pci_bus *bus);
772 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
773 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
774 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
775 };
776
777 /*
778 * ACPI needs to be able to access PCI config space before we've done a
779 * PCI bus scan and created pci_bus structures.
780 */
781 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
782 int reg, int len, u32 *val);
783 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
784 int reg, int len, u32 val);
785
786 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
787 typedef u64 pci_bus_addr_t;
788 #else
789 typedef u32 pci_bus_addr_t;
790 #endif
791
792 struct pci_bus_region {
793 pci_bus_addr_t start;
794 pci_bus_addr_t end;
795 };
796
797 struct pci_dynids {
798 spinlock_t lock; /* Protects list, index */
799 struct list_head list; /* For IDs added at runtime */
800 };
801
802
803 /*
804 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
805 * a set of callbacks in struct pci_error_handlers, that device driver
806 * will be notified of PCI bus errors, and will be driven to recovery
807 * when an error occurs.
808 */
809
810 typedef unsigned int __bitwise pci_ers_result_t;
811
812 enum pci_ers_result {
813 /* No result/none/not supported in device driver */
814 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
815
816 /* Device driver can recover without slot reset */
817 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
818
819 /* Device driver wants slot to be reset */
820 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
821
822 /* Device has completely failed, is unrecoverable */
823 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
824
825 /* Device driver is fully recovered and operational */
826 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
827
828 /* No AER capabilities registered for the driver */
829 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
830 };
831
832 /* PCI bus error event callbacks */
833 struct pci_error_handlers {
834 /* PCI bus error detected on this device */
835 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
836 pci_channel_state_t error);
837
838 /* MMIO has been re-enabled, but not DMA */
839 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
840
841 /* PCI slot has been reset */
842 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
843
844 /* PCI function reset prepare or completed */
845 void (*reset_prepare)(struct pci_dev *dev);
846 void (*reset_done)(struct pci_dev *dev);
847
848 /* Device driver may resume normal operations */
849 void (*resume)(struct pci_dev *dev);
850
851 /* Allow device driver to record more details of a correctable error */
852 void (*cor_error_detected)(struct pci_dev *dev);
853 };
854
855
856 struct module;
857
858 /**
859 * struct pci_driver - PCI driver structure
860 * @node: List of driver structures.
861 * @name: Driver name.
862 * @id_table: Pointer to table of device IDs the driver is
863 * interested in. Most drivers should export this
864 * table using MODULE_DEVICE_TABLE(pci,...).
865 * @probe: This probing function gets called (during execution
866 * of pci_register_driver() for already existing
867 * devices or later if a new device gets inserted) for
868 * all PCI devices which match the ID table and are not
869 * "owned" by the other drivers yet. This function gets
870 * passed a "struct pci_dev \*" for each device whose
871 * entry in the ID table matches the device. The probe
872 * function returns zero when the driver chooses to
873 * take "ownership" of the device or an error code
874 * (negative number) otherwise.
875 * The probe function always gets called from process
876 * context, so it can sleep.
877 * @remove: The remove() function gets called whenever a device
878 * being handled by this driver is removed (either during
879 * deregistration of the driver or when it's manually
880 * pulled out of a hot-pluggable slot).
881 * The remove function always gets called from process
882 * context, so it can sleep.
883 * @suspend: Put device into low power state.
884 * @resume: Wake device from low power state.
885 * (Please see Documentation/power/pci.rst for descriptions
886 * of PCI Power Management and the related functions.)
887 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
888 * Intended to stop any idling DMA operations.
889 * Useful for enabling wake-on-lan (NIC) or changing
890 * the power state of a device before reboot.
891 * e.g. drivers/net/e100.c.
892 * @sriov_configure: Optional driver callback to allow configuration of
893 * number of VFs to enable via sysfs "sriov_numvfs" file.
894 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
895 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
896 * This will change MSI-X Table Size in the VF Message Control
897 * registers.
898 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
899 * MSI-X vectors available for distribution to the VFs.
900 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
901 * @groups: Sysfs attribute groups.
902 * @dev_groups: Attributes attached to the device that will be
903 * created once it is bound to the driver.
904 * @driver: Driver model structure.
905 * @dynids: List of dynamically added device IDs.
906 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
907 * For most device drivers, no need to care about this flag
908 * as long as all DMAs are handled through the kernel DMA API.
909 * For some special ones, for example VFIO drivers, they know
910 * how to manage the DMA themselves and set this flag so that
911 * the IOMMU layer will allow them to setup and manage their
912 * own I/O address space.
913 */
914 struct pci_driver {
915 struct list_head node;
916 const char *name;
917 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
918 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
919 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
920 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
921 int (*resume)(struct pci_dev *dev); /* Device woken up */
922 void (*shutdown)(struct pci_dev *dev);
923 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
924 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
925 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
926 const struct pci_error_handlers *err_handler;
927 const struct attribute_group **groups;
928 const struct attribute_group **dev_groups;
929 struct device_driver driver;
930 struct pci_dynids dynids;
931 bool driver_managed_dma;
932 };
933
to_pci_driver(struct device_driver * drv)934 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
935 {
936 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
937 }
938
939 /**
940 * PCI_DEVICE - macro used to describe a specific PCI device
941 * @vend: the 16 bit PCI Vendor ID
942 * @dev: the 16 bit PCI Device ID
943 *
944 * This macro is used to create a struct pci_device_id that matches a
945 * specific device. The subvendor and subdevice fields will be set to
946 * PCI_ANY_ID.
947 */
948 #define PCI_DEVICE(vend,dev) \
949 .vendor = (vend), .device = (dev), \
950 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
951
952 /**
953 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
954 * override_only flags.
955 * @vend: the 16 bit PCI Vendor ID
956 * @dev: the 16 bit PCI Device ID
957 * @driver_override: the 32 bit PCI Device override_only
958 *
959 * This macro is used to create a struct pci_device_id that matches only a
960 * driver_override device. The subvendor and subdevice fields will be set to
961 * PCI_ANY_ID.
962 */
963 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
964 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
965 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
966
967 /**
968 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
969 * "driver_override" PCI device.
970 * @vend: the 16 bit PCI Vendor ID
971 * @dev: the 16 bit PCI Device ID
972 *
973 * This macro is used to create a struct pci_device_id that matches a
974 * specific device. The subvendor and subdevice fields will be set to
975 * PCI_ANY_ID and the driver_override will be set to
976 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
977 */
978 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
979 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
980
981 /**
982 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
983 * @vend: the 16 bit PCI Vendor ID
984 * @dev: the 16 bit PCI Device ID
985 * @subvend: the 16 bit PCI Subvendor ID
986 * @subdev: the 16 bit PCI Subdevice ID
987 *
988 * This macro is used to create a struct pci_device_id that matches a
989 * specific device with subsystem information.
990 */
991 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
992 .vendor = (vend), .device = (dev), \
993 .subvendor = (subvend), .subdevice = (subdev)
994
995 /**
996 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
997 * @dev_class: the class, subclass, prog-if triple for this device
998 * @dev_class_mask: the class mask for this device
999 *
1000 * This macro is used to create a struct pci_device_id that matches a
1001 * specific PCI class. The vendor, device, subvendor, and subdevice
1002 * fields will be set to PCI_ANY_ID.
1003 */
1004 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1005 .class = (dev_class), .class_mask = (dev_class_mask), \
1006 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1007 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1008
1009 /**
1010 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1011 * @vend: the vendor name
1012 * @dev: the 16 bit PCI Device ID
1013 *
1014 * This macro is used to create a struct pci_device_id that matches a
1015 * specific PCI device. The subvendor, and subdevice fields will be set
1016 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1017 * private data.
1018 */
1019 #define PCI_VDEVICE(vend, dev) \
1020 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1021 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1022
1023 /**
1024 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1025 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1026 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1027 * @data: the driver data to be filled
1028 *
1029 * This macro is used to create a struct pci_device_id that matches a
1030 * specific PCI device. The subvendor, and subdevice fields will be set
1031 * to PCI_ANY_ID.
1032 */
1033 #define PCI_DEVICE_DATA(vend, dev, data) \
1034 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1035 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1036 .driver_data = (kernel_ulong_t)(data)
1037
1038 enum {
1039 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1040 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1041 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1042 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1043 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1044 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1045 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1046 };
1047
1048 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1049 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1050 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1051 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1052
1053 /* These external functions are only available when PCI support is enabled */
1054 #ifdef CONFIG_PCI
1055
1056 extern unsigned int pci_flags;
1057
pci_set_flags(int flags)1058 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1059 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1060 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1061 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1062
1063 void pcie_bus_configure_settings(struct pci_bus *bus);
1064
1065 enum pcie_bus_config_types {
1066 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1067 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1068 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1069 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1070 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1071 };
1072
1073 extern enum pcie_bus_config_types pcie_bus_config;
1074
1075 extern struct bus_type pci_bus_type;
1076
1077 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1078 * code, or PCI core code. */
1079 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1080 /* Some device drivers need know if PCI is initiated */
1081 int no_pci_devices(void);
1082
1083 void pcibios_resource_survey_bus(struct pci_bus *bus);
1084 void pcibios_bus_add_device(struct pci_dev *pdev);
1085 void pcibios_add_bus(struct pci_bus *bus);
1086 void pcibios_remove_bus(struct pci_bus *bus);
1087 void pcibios_fixup_bus(struct pci_bus *);
1088 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1089 /* Architecture-specific versions may override this (weak) */
1090 char *pcibios_setup(char *str);
1091
1092 /* Used only when drivers/pci/setup.c is used */
1093 resource_size_t pcibios_align_resource(void *, const struct resource *,
1094 resource_size_t,
1095 resource_size_t);
1096
1097 /* Weak but can be overridden by arch */
1098 void pci_fixup_cardbus(struct pci_bus *);
1099
1100 /* Generic PCI functions used internally */
1101
1102 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1103 struct resource *res);
1104 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1105 struct pci_bus_region *region);
1106 void pcibios_scan_specific_bus(int busn);
1107 struct pci_bus *pci_find_bus(int domain, int busnr);
1108 void pci_bus_add_devices(const struct pci_bus *bus);
1109 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1110 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1111 struct pci_ops *ops, void *sysdata,
1112 struct list_head *resources);
1113 int pci_host_probe(struct pci_host_bridge *bridge);
1114 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1115 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1116 void pci_bus_release_busn_res(struct pci_bus *b);
1117 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1118 struct pci_ops *ops, void *sysdata,
1119 struct list_head *resources);
1120 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1121 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1122 int busnr);
1123 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1124 const char *name,
1125 struct hotplug_slot *hotplug);
1126 void pci_destroy_slot(struct pci_slot *slot);
1127 #ifdef CONFIG_SYSFS
1128 void pci_dev_assign_slot(struct pci_dev *dev);
1129 #else
pci_dev_assign_slot(struct pci_dev * dev)1130 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1131 #endif
1132 int pci_scan_slot(struct pci_bus *bus, int devfn);
1133 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1134 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1135 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1136 void pci_bus_add_device(struct pci_dev *dev);
1137 void pci_read_bridge_bases(struct pci_bus *child);
1138 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1139 struct resource *res);
1140 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1141 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1142 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1143 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1144 void pci_dev_put(struct pci_dev *dev);
1145 void pci_remove_bus(struct pci_bus *b);
1146 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1147 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1148 void pci_stop_root_bus(struct pci_bus *bus);
1149 void pci_remove_root_bus(struct pci_bus *bus);
1150 void pci_setup_cardbus(struct pci_bus *bus);
1151 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1152 void pci_sort_breadthfirst(void);
1153 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1154 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1155
1156 /* Generic PCI functions exported to card drivers */
1157
1158 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1159 u8 pci_find_capability(struct pci_dev *dev, int cap);
1160 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1161 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1162 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1163 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1164 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1165 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1166 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1167 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1168
1169 u64 pci_get_dsn(struct pci_dev *dev);
1170
1171 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1172 struct pci_dev *from);
1173 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1174 unsigned int ss_vendor, unsigned int ss_device,
1175 struct pci_dev *from);
1176 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1177 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1178 unsigned int devfn);
1179 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1180 int pci_dev_present(const struct pci_device_id *ids);
1181
1182 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1183 int where, u8 *val);
1184 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1185 int where, u16 *val);
1186 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1187 int where, u32 *val);
1188 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1189 int where, u8 val);
1190 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1191 int where, u16 val);
1192 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1193 int where, u32 val);
1194
1195 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1196 int where, int size, u32 *val);
1197 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1198 int where, int size, u32 val);
1199 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1200 int where, int size, u32 *val);
1201 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1202 int where, int size, u32 val);
1203
1204 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1205
1206 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1207 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1208 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1209 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1210 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1211 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1212
1213 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1214 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1215 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1216 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1217 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1218 u16 clear, u16 set);
1219 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1220 u32 clear, u32 set);
1221
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1222 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1223 u16 set)
1224 {
1225 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1226 }
1227
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1228 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1229 u32 set)
1230 {
1231 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1232 }
1233
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1234 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1235 u16 clear)
1236 {
1237 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1238 }
1239
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1240 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1241 u32 clear)
1242 {
1243 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1244 }
1245
1246 /* User-space driven config access */
1247 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1248 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1249 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1250 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1251 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1252 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1253
1254 int __must_check pci_enable_device(struct pci_dev *dev);
1255 int __must_check pci_enable_device_io(struct pci_dev *dev);
1256 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1257 int __must_check pci_reenable_device(struct pci_dev *);
1258 int __must_check pcim_enable_device(struct pci_dev *pdev);
1259 void pcim_pin_device(struct pci_dev *pdev);
1260
pci_intx_mask_supported(struct pci_dev * pdev)1261 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1262 {
1263 /*
1264 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1265 * writable and no quirk has marked the feature broken.
1266 */
1267 return !pdev->broken_intx_masking;
1268 }
1269
pci_is_enabled(struct pci_dev * pdev)1270 static inline int pci_is_enabled(struct pci_dev *pdev)
1271 {
1272 return (atomic_read(&pdev->enable_cnt) > 0);
1273 }
1274
pci_is_managed(struct pci_dev * pdev)1275 static inline int pci_is_managed(struct pci_dev *pdev)
1276 {
1277 return pdev->is_managed;
1278 }
1279
1280 void pci_disable_device(struct pci_dev *dev);
1281
1282 extern unsigned int pcibios_max_latency;
1283 void pci_set_master(struct pci_dev *dev);
1284 void pci_clear_master(struct pci_dev *dev);
1285
1286 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1287 int pci_set_cacheline_size(struct pci_dev *dev);
1288 int __must_check pci_set_mwi(struct pci_dev *dev);
1289 int __must_check pcim_set_mwi(struct pci_dev *dev);
1290 int pci_try_set_mwi(struct pci_dev *dev);
1291 void pci_clear_mwi(struct pci_dev *dev);
1292 void pci_disable_parity(struct pci_dev *dev);
1293 void pci_intx(struct pci_dev *dev, int enable);
1294 bool pci_check_and_mask_intx(struct pci_dev *dev);
1295 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1296 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1297 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1298 int pcix_get_max_mmrbc(struct pci_dev *dev);
1299 int pcix_get_mmrbc(struct pci_dev *dev);
1300 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1301 int pcie_get_readrq(struct pci_dev *dev);
1302 int pcie_set_readrq(struct pci_dev *dev, int rq);
1303 int pcie_get_mps(struct pci_dev *dev);
1304 int pcie_set_mps(struct pci_dev *dev, int mps);
1305 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1306 enum pci_bus_speed *speed,
1307 enum pcie_link_width *width);
1308 void pcie_print_link_status(struct pci_dev *dev);
1309 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1310 int pcie_flr(struct pci_dev *dev);
1311 int __pci_reset_function_locked(struct pci_dev *dev);
1312 int pci_reset_function(struct pci_dev *dev);
1313 int pci_reset_function_locked(struct pci_dev *dev);
1314 int pci_try_reset_function(struct pci_dev *dev);
1315 int pci_probe_reset_slot(struct pci_slot *slot);
1316 int pci_probe_reset_bus(struct pci_bus *bus);
1317 int pci_reset_bus(struct pci_dev *dev);
1318 void pci_reset_secondary_bus(struct pci_dev *dev);
1319 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1320 void pci_update_resource(struct pci_dev *dev, int resno);
1321 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1322 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1323 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1324 static inline int pci_rebar_bytes_to_size(u64 bytes)
1325 {
1326 bytes = roundup_pow_of_two(bytes);
1327
1328 /* Return BAR size as defined in the resizable BAR specification */
1329 return max(ilog2(bytes), 20) - 20;
1330 }
1331
1332 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1333 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1334 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1335 bool pci_device_is_present(struct pci_dev *pdev);
1336 void pci_ignore_hotplug(struct pci_dev *dev);
1337 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1338 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1339
1340 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1341 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1342 const char *fmt, ...);
1343 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1344
1345 /* ROM control related routines */
1346 int pci_enable_rom(struct pci_dev *pdev);
1347 void pci_disable_rom(struct pci_dev *pdev);
1348 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1349 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1350
1351 /* Power management related routines */
1352 int pci_save_state(struct pci_dev *dev);
1353 void pci_restore_state(struct pci_dev *dev);
1354 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1355 int pci_load_saved_state(struct pci_dev *dev,
1356 struct pci_saved_state *state);
1357 int pci_load_and_free_saved_state(struct pci_dev *dev,
1358 struct pci_saved_state **state);
1359 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1360 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1361 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1362 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1363 void pci_pme_active(struct pci_dev *dev, bool enable);
1364 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1365 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1366 int pci_prepare_to_sleep(struct pci_dev *dev);
1367 int pci_back_from_sleep(struct pci_dev *dev);
1368 bool pci_dev_run_wake(struct pci_dev *dev);
1369 void pci_d3cold_enable(struct pci_dev *dev);
1370 void pci_d3cold_disable(struct pci_dev *dev);
1371 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1372 void pci_resume_bus(struct pci_bus *bus);
1373 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1374
1375 /* For use by arch with custom probe code */
1376 void set_pcie_port_type(struct pci_dev *pdev);
1377 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1378
1379 /* Functions for PCI Hotplug drivers to use */
1380 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1381 unsigned int pci_rescan_bus(struct pci_bus *bus);
1382 void pci_lock_rescan_remove(void);
1383 void pci_unlock_rescan_remove(void);
1384
1385 /* Vital Product Data routines */
1386 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1387 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1388 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1389 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1390
1391 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1392 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1393 void pci_bus_assign_resources(const struct pci_bus *bus);
1394 void pci_bus_claim_resources(struct pci_bus *bus);
1395 void pci_bus_size_bridges(struct pci_bus *bus);
1396 int pci_claim_resource(struct pci_dev *, int);
1397 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1398 void pci_assign_unassigned_resources(void);
1399 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1400 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1401 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1402 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1403 void pdev_enable_device(struct pci_dev *);
1404 int pci_enable_resources(struct pci_dev *, int mask);
1405 void pci_assign_irq(struct pci_dev *dev);
1406 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1407 #define HAVE_PCI_REQ_REGIONS 2
1408 int __must_check pci_request_regions(struct pci_dev *, const char *);
1409 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1410 void pci_release_regions(struct pci_dev *);
1411 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1412 void pci_release_region(struct pci_dev *, int);
1413 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1414 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1415 void pci_release_selected_regions(struct pci_dev *, int);
1416
1417 static inline __must_check struct resource *
pci_request_config_region_exclusive(struct pci_dev * pdev,unsigned int offset,unsigned int len,const char * name)1418 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1419 unsigned int len, const char *name)
1420 {
1421 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1422 name, IORESOURCE_EXCLUSIVE);
1423 }
1424
pci_release_config_region(struct pci_dev * pdev,unsigned int offset,unsigned int len)1425 static inline void pci_release_config_region(struct pci_dev *pdev,
1426 unsigned int offset,
1427 unsigned int len)
1428 {
1429 __release_region(&pdev->driver_exclusive_resource, offset, len);
1430 }
1431
1432 /* drivers/pci/bus.c */
1433 void pci_add_resource(struct list_head *resources, struct resource *res);
1434 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1435 resource_size_t offset);
1436 void pci_free_resource_list(struct list_head *resources);
1437 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1438 unsigned int flags);
1439 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1440 void pci_bus_remove_resources(struct pci_bus *bus);
1441 int devm_request_pci_bus_resources(struct device *dev,
1442 struct list_head *resources);
1443
1444 /* Temporary until new and working PCI SBR API in place */
1445 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1446
1447 #define pci_bus_for_each_resource(bus, res, i) \
1448 for (i = 0; \
1449 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1450 i++)
1451
1452 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1453 struct resource *res, resource_size_t size,
1454 resource_size_t align, resource_size_t min,
1455 unsigned long type_mask,
1456 resource_size_t (*alignf)(void *,
1457 const struct resource *,
1458 resource_size_t,
1459 resource_size_t),
1460 void *alignf_data);
1461
1462
1463 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1464 resource_size_t size);
1465 unsigned long pci_address_to_pio(phys_addr_t addr);
1466 phys_addr_t pci_pio_to_address(unsigned long pio);
1467 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1468 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1469 phys_addr_t phys_addr);
1470 void pci_unmap_iospace(struct resource *res);
1471 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1472 resource_size_t offset,
1473 resource_size_t size);
1474 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1475 struct resource *res);
1476
pci_bus_address(struct pci_dev * pdev,int bar)1477 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1478 {
1479 struct pci_bus_region region;
1480
1481 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1482 return region.start;
1483 }
1484
1485 /* Proper probing supporting hot-pluggable devices */
1486 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1487 const char *mod_name);
1488
1489 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1490 #define pci_register_driver(driver) \
1491 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1492
1493 void pci_unregister_driver(struct pci_driver *dev);
1494
1495 /**
1496 * module_pci_driver() - Helper macro for registering a PCI driver
1497 * @__pci_driver: pci_driver struct
1498 *
1499 * Helper macro for PCI drivers which do not do anything special in module
1500 * init/exit. This eliminates a lot of boilerplate. Each module may only
1501 * use this macro once, and calling it replaces module_init() and module_exit()
1502 */
1503 #define module_pci_driver(__pci_driver) \
1504 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1505
1506 /**
1507 * builtin_pci_driver() - Helper macro for registering a PCI driver
1508 * @__pci_driver: pci_driver struct
1509 *
1510 * Helper macro for PCI drivers which do not do anything special in their
1511 * init code. This eliminates a lot of boilerplate. Each driver may only
1512 * use this macro once, and calling it replaces device_initcall(...)
1513 */
1514 #define builtin_pci_driver(__pci_driver) \
1515 builtin_driver(__pci_driver, pci_register_driver)
1516
1517 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1518 int pci_add_dynid(struct pci_driver *drv,
1519 unsigned int vendor, unsigned int device,
1520 unsigned int subvendor, unsigned int subdevice,
1521 unsigned int class, unsigned int class_mask,
1522 unsigned long driver_data);
1523 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1524 struct pci_dev *dev);
1525 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1526 int pass);
1527
1528 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1529 void *userdata);
1530 int pci_cfg_space_size(struct pci_dev *dev);
1531 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1532 void pci_setup_bridge(struct pci_bus *bus);
1533 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1534 unsigned long type);
1535
1536 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1537 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1538
1539 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1540 unsigned int command_bits, u32 flags);
1541
1542 /*
1543 * Virtual interrupts allow for more interrupts to be allocated
1544 * than the device has interrupts for. These are not programmed
1545 * into the device's MSI-X table and must be handled by some
1546 * other driver means.
1547 */
1548 #define PCI_IRQ_VIRTUAL (1 << 4)
1549
1550 #define PCI_IRQ_ALL_TYPES \
1551 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1552
1553 #include <linux/dmapool.h>
1554
1555 struct msix_entry {
1556 u32 vector; /* Kernel uses to write allocated vector */
1557 u16 entry; /* Driver uses to specify entry, OS writes */
1558 };
1559
1560 #ifdef CONFIG_PCI_MSI
1561 int pci_msi_vec_count(struct pci_dev *dev);
1562 void pci_disable_msi(struct pci_dev *dev);
1563 int pci_msix_vec_count(struct pci_dev *dev);
1564 void pci_disable_msix(struct pci_dev *dev);
1565 void pci_restore_msi_state(struct pci_dev *dev);
1566 int pci_msi_enabled(void);
1567 int pci_enable_msi(struct pci_dev *dev);
1568 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1569 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1570 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1571 struct msix_entry *entries, int nvec)
1572 {
1573 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1574 if (rc < 0)
1575 return rc;
1576 return 0;
1577 }
1578 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1579 unsigned int max_vecs, unsigned int flags);
1580 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1581 unsigned int max_vecs, unsigned int flags,
1582 struct irq_affinity *affd);
1583
1584 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1585 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1586 const struct irq_affinity_desc *affdesc);
1587 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1588
1589 void pci_free_irq_vectors(struct pci_dev *dev);
1590 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1591 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1592
1593 #else
pci_msi_vec_count(struct pci_dev * dev)1594 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1595 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1596 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1597 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1598 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1599 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1600 static inline int pci_enable_msi(struct pci_dev *dev)
1601 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1602 static inline int pci_enable_msix_range(struct pci_dev *dev,
1603 struct msix_entry *entries, int minvec, int maxvec)
1604 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1605 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1606 struct msix_entry *entries, int nvec)
1607 { return -ENOSYS; }
1608
1609 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1610 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1611 unsigned int max_vecs, unsigned int flags,
1612 struct irq_affinity *aff_desc)
1613 {
1614 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1615 return 1;
1616 return -ENOSPC;
1617 }
1618 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1619 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1620 unsigned int max_vecs, unsigned int flags)
1621 {
1622 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1623 flags, NULL);
1624 }
1625
pci_msix_alloc_irq_at(struct pci_dev * dev,unsigned int index,const struct irq_affinity_desc * affdesc)1626 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1627 const struct irq_affinity_desc *affdesc)
1628 {
1629 struct msi_map map = { .index = -ENOSYS, };
1630
1631 return map;
1632 }
1633
pci_msix_free_irq(struct pci_dev * pdev,struct msi_map map)1634 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1635 {
1636 }
1637
pci_free_irq_vectors(struct pci_dev * dev)1638 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1639 {
1640 }
1641
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1642 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1643 {
1644 if (WARN_ON_ONCE(nr > 0))
1645 return -EINVAL;
1646 return dev->irq;
1647 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1648 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1649 int vec)
1650 {
1651 return cpu_possible_mask;
1652 }
1653 #endif
1654
1655 /**
1656 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1657 * @d: the INTx IRQ domain
1658 * @node: the DT node for the device whose interrupt we're translating
1659 * @intspec: the interrupt specifier data from the DT
1660 * @intsize: the number of entries in @intspec
1661 * @out_hwirq: pointer at which to write the hwirq number
1662 * @out_type: pointer at which to write the interrupt type
1663 *
1664 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1665 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1666 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1667 * INTx value to obtain the hwirq number.
1668 *
1669 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1670 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1671 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1672 struct device_node *node,
1673 const u32 *intspec,
1674 unsigned int intsize,
1675 unsigned long *out_hwirq,
1676 unsigned int *out_type)
1677 {
1678 const u32 intx = intspec[0];
1679
1680 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1681 return -EINVAL;
1682
1683 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1684 return 0;
1685 }
1686
1687 #ifdef CONFIG_PCIEPORTBUS
1688 extern bool pcie_ports_disabled;
1689 extern bool pcie_ports_native;
1690 #else
1691 #define pcie_ports_disabled true
1692 #define pcie_ports_native false
1693 #endif
1694
1695 #define PCIE_LINK_STATE_L0S BIT(0)
1696 #define PCIE_LINK_STATE_L1 BIT(1)
1697 #define PCIE_LINK_STATE_CLKPM BIT(2)
1698 #define PCIE_LINK_STATE_L1_1 BIT(3)
1699 #define PCIE_LINK_STATE_L1_2 BIT(4)
1700 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1701 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1702 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
1703 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
1704 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
1705 PCIE_LINK_STATE_L1_2_PCIPM)
1706
1707 #ifdef CONFIG_PCIEASPM
1708 int pci_disable_link_state(struct pci_dev *pdev, int state);
1709 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1710 int pci_enable_link_state(struct pci_dev *pdev, int state);
1711 void pcie_no_aspm(void);
1712 bool pcie_aspm_support_enabled(void);
1713 bool pcie_aspm_enabled(struct pci_dev *pdev);
1714 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1715 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1716 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1717 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1718 { return 0; }
pci_enable_link_state(struct pci_dev * pdev,int state)1719 static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1720 { return 0; }
pcie_no_aspm(void)1721 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1722 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1723 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1724 #endif
1725
1726 #ifdef CONFIG_PCIEAER
1727 bool pci_aer_available(void);
1728 #else
pci_aer_available(void)1729 static inline bool pci_aer_available(void) { return false; }
1730 #endif
1731
1732 bool pci_ats_disabled(void);
1733
1734 #ifdef CONFIG_PCIE_PTM
1735 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1736 void pci_disable_ptm(struct pci_dev *dev);
1737 bool pcie_ptm_enabled(struct pci_dev *dev);
1738 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1739 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1740 { return -EINVAL; }
pci_disable_ptm(struct pci_dev * dev)1741 static inline void pci_disable_ptm(struct pci_dev *dev) { }
pcie_ptm_enabled(struct pci_dev * dev)1742 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1743 { return false; }
1744 #endif
1745
1746 void pci_cfg_access_lock(struct pci_dev *dev);
1747 bool pci_cfg_access_trylock(struct pci_dev *dev);
1748 void pci_cfg_access_unlock(struct pci_dev *dev);
1749
1750 void pci_dev_lock(struct pci_dev *dev);
1751 int pci_dev_trylock(struct pci_dev *dev);
1752 void pci_dev_unlock(struct pci_dev *dev);
1753
1754 /*
1755 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1756 * a PCI domain is defined to be a set of PCI buses which share
1757 * configuration space.
1758 */
1759 #ifdef CONFIG_PCI_DOMAINS
1760 extern int pci_domains_supported;
1761 #else
1762 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1763 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1764 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1765 #endif /* CONFIG_PCI_DOMAINS */
1766
1767 /*
1768 * Generic implementation for PCI domain support. If your
1769 * architecture does not need custom management of PCI
1770 * domains then this implementation will be used
1771 */
1772 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1773 static inline int pci_domain_nr(struct pci_bus *bus)
1774 {
1775 return bus->domain_nr;
1776 }
1777 #ifdef CONFIG_ACPI
1778 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1779 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1780 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1781 { return 0; }
1782 #endif
1783 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1784 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
1785 #endif
1786
1787 /* Some architectures require additional setup to direct VGA traffic */
1788 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1789 unsigned int command_bits, u32 flags);
1790 void pci_register_set_vga_state(arch_set_vga_state_t func);
1791
1792 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1793 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1794 {
1795 return pci_request_selected_regions(pdev,
1796 pci_select_bars(pdev, IORESOURCE_IO), name);
1797 }
1798
1799 static inline void
pci_release_io_regions(struct pci_dev * pdev)1800 pci_release_io_regions(struct pci_dev *pdev)
1801 {
1802 return pci_release_selected_regions(pdev,
1803 pci_select_bars(pdev, IORESOURCE_IO));
1804 }
1805
1806 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1807 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1808 {
1809 return pci_request_selected_regions(pdev,
1810 pci_select_bars(pdev, IORESOURCE_MEM), name);
1811 }
1812
1813 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1814 pci_release_mem_regions(struct pci_dev *pdev)
1815 {
1816 return pci_release_selected_regions(pdev,
1817 pci_select_bars(pdev, IORESOURCE_MEM));
1818 }
1819
1820 #else /* CONFIG_PCI is not enabled */
1821
pci_set_flags(int flags)1822 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1823 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1824 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1825 static inline int pci_has_flag(int flag) { return 0; }
1826
1827 /*
1828 * If the system does not have PCI, clearly these return errors. Define
1829 * these as simple inline functions to avoid hair in drivers.
1830 */
1831 #define _PCI_NOP(o, s, t) \
1832 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1833 int where, t val) \
1834 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1835
1836 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1837 _PCI_NOP(o, word, u16 x) \
1838 _PCI_NOP(o, dword, u32 x)
1839 _PCI_NOP_ALL(read, *)
1840 _PCI_NOP_ALL(write,)
1841
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1842 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1843 unsigned int device,
1844 struct pci_dev *from)
1845 { return NULL; }
1846
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1847 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1848 unsigned int device,
1849 unsigned int ss_vendor,
1850 unsigned int ss_device,
1851 struct pci_dev *from)
1852 { return NULL; }
1853
pci_get_class(unsigned int class,struct pci_dev * from)1854 static inline struct pci_dev *pci_get_class(unsigned int class,
1855 struct pci_dev *from)
1856 { return NULL; }
1857
1858
pci_dev_present(const struct pci_device_id * ids)1859 static inline int pci_dev_present(const struct pci_device_id *ids)
1860 { return 0; }
1861
1862 #define no_pci_devices() (1)
1863 #define pci_dev_put(dev) do { } while (0)
1864
pci_set_master(struct pci_dev * dev)1865 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1866 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1867 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1868 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1869 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1870 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1871 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1872 struct module *owner,
1873 const char *mod_name)
1874 { return 0; }
pci_register_driver(struct pci_driver * drv)1875 static inline int pci_register_driver(struct pci_driver *drv)
1876 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1877 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1878 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1879 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1880 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1881 int cap)
1882 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1883 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1884 { return 0; }
1885
pci_get_dsn(struct pci_dev * dev)1886 static inline u64 pci_get_dsn(struct pci_dev *dev)
1887 { return 0; }
1888
1889 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1890 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1891 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1892 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1893 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1894 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1895 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1896 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1897 pm_message_t state)
1898 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1899 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1900 int enable)
1901 { return 0; }
1902
pci_find_resource(struct pci_dev * dev,struct resource * res)1903 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1904 struct resource *res)
1905 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1906 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1907 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1908 static inline void pci_release_regions(struct pci_dev *dev) { }
1909
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1910 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1911 phys_addr_t addr, resource_size_t size)
1912 { return -EINVAL; }
1913
pci_address_to_pio(phys_addr_t addr)1914 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1915
pci_find_next_bus(const struct pci_bus * from)1916 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1917 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1918 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1919 unsigned int devfn)
1920 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1921 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1922 unsigned int bus, unsigned int devfn)
1923 { return NULL; }
1924
pci_domain_nr(struct pci_bus * bus)1925 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1926 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1927
1928 #define dev_is_pci(d) (false)
1929 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1930 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1931 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1932 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1933 struct device_node *node,
1934 const u32 *intspec,
1935 unsigned int intsize,
1936 unsigned long *out_hwirq,
1937 unsigned int *out_type)
1938 { return -EINVAL; }
1939
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1940 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1941 struct pci_dev *dev)
1942 { return NULL; }
pci_ats_disabled(void)1943 static inline bool pci_ats_disabled(void) { return true; }
1944
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1945 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1946 {
1947 return -EINVAL;
1948 }
1949
1950 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1951 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1952 unsigned int max_vecs, unsigned int flags,
1953 struct irq_affinity *aff_desc)
1954 {
1955 return -ENOSPC;
1956 }
1957 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1958 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1959 unsigned int max_vecs, unsigned int flags)
1960 {
1961 return -ENOSPC;
1962 }
1963 #endif /* CONFIG_PCI */
1964
1965 /* Include architecture-dependent settings and functions */
1966
1967 #include <asm/pci.h>
1968
1969 /*
1970 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1971 * is expected to be an offset within that region.
1972 *
1973 */
1974 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1975 struct vm_area_struct *vma,
1976 enum pci_mmap_state mmap_state, int write_combine);
1977
1978 #ifndef arch_can_pci_mmap_wc
1979 #define arch_can_pci_mmap_wc() 0
1980 #endif
1981
1982 #ifndef arch_can_pci_mmap_io
1983 #define arch_can_pci_mmap_io() 0
1984 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1985 #else
1986 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1987 #endif
1988
1989 #ifndef pci_root_bus_fwnode
1990 #define pci_root_bus_fwnode(bus) NULL
1991 #endif
1992
1993 /*
1994 * These helpers provide future and backwards compatibility
1995 * for accessing popular PCI BAR info
1996 */
1997 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1998 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1999 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
2000 #define pci_resource_len(dev,bar) \
2001 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
2002 \
2003 (pci_resource_end((dev), (bar)) - \
2004 pci_resource_start((dev), (bar)) + 1))
2005
2006 /*
2007 * Similar to the helpers above, these manipulate per-pci_dev
2008 * driver-specific data. They are really just a wrapper around
2009 * the generic device structure functions of these calls.
2010 */
pci_get_drvdata(struct pci_dev * pdev)2011 static inline void *pci_get_drvdata(struct pci_dev *pdev)
2012 {
2013 return dev_get_drvdata(&pdev->dev);
2014 }
2015
pci_set_drvdata(struct pci_dev * pdev,void * data)2016 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2017 {
2018 dev_set_drvdata(&pdev->dev, data);
2019 }
2020
pci_name(const struct pci_dev * pdev)2021 static inline const char *pci_name(const struct pci_dev *pdev)
2022 {
2023 return dev_name(&pdev->dev);
2024 }
2025
2026 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2027 const struct resource *rsrc,
2028 resource_size_t *start, resource_size_t *end);
2029
2030 /*
2031 * The world is not perfect and supplies us with broken PCI devices.
2032 * For at least a part of these bugs we need a work-around, so both
2033 * generic (drivers/pci/quirks.c) and per-architecture code can define
2034 * fixup hooks to be called for particular buggy devices.
2035 */
2036
2037 struct pci_fixup {
2038 u16 vendor; /* Or PCI_ANY_ID */
2039 u16 device; /* Or PCI_ANY_ID */
2040 u32 class; /* Or PCI_ANY_ID */
2041 unsigned int class_shift; /* should be 0, 8, 16 */
2042 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2043 int hook_offset;
2044 #else
2045 void (*hook)(struct pci_dev *dev);
2046 #endif
2047 };
2048
2049 enum pci_fixup_pass {
2050 pci_fixup_early, /* Before probing BARs */
2051 pci_fixup_header, /* After reading configuration header */
2052 pci_fixup_final, /* Final phase of device fixups */
2053 pci_fixup_enable, /* pci_enable_device() time */
2054 pci_fixup_resume, /* pci_device_resume() */
2055 pci_fixup_suspend, /* pci_device_suspend() */
2056 pci_fixup_resume_early, /* pci_device_resume_early() */
2057 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2058 };
2059
2060 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2061 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2062 class_shift, hook) \
2063 __ADDRESSABLE(hook) \
2064 asm(".section " #sec ", \"a\" \n" \
2065 ".balign 16 \n" \
2066 ".short " #vendor ", " #device " \n" \
2067 ".long " #class ", " #class_shift " \n" \
2068 ".long " #hook " - . \n" \
2069 ".previous \n");
2070
2071 /*
2072 * Clang's LTO may rename static functions in C, but has no way to
2073 * handle such renamings when referenced from inline asm. To work
2074 * around this, create global C stubs for these cases.
2075 */
2076 #ifdef CONFIG_LTO_CLANG
2077 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2078 class_shift, hook, stub) \
2079 void stub(struct pci_dev *dev); \
2080 void stub(struct pci_dev *dev) \
2081 { \
2082 hook(dev); \
2083 } \
2084 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2085 class_shift, stub)
2086 #else
2087 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2088 class_shift, hook, stub) \
2089 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2090 class_shift, hook)
2091 #endif
2092
2093 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2094 class_shift, hook) \
2095 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2096 class_shift, hook, __UNIQUE_ID(hook))
2097 #else
2098 /* Anonymous variables would be nice... */
2099 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2100 class_shift, hook) \
2101 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2102 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2103 = { vendor, device, class, class_shift, hook };
2104 #endif
2105
2106 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2107 class_shift, hook) \
2108 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2109 hook, vendor, device, class, class_shift, hook)
2110 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2111 class_shift, hook) \
2112 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2113 hook, vendor, device, class, class_shift, hook)
2114 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2115 class_shift, hook) \
2116 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2117 hook, vendor, device, class, class_shift, hook)
2118 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2119 class_shift, hook) \
2120 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2121 hook, vendor, device, class, class_shift, hook)
2122 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2123 class_shift, hook) \
2124 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2125 resume##hook, vendor, device, class, class_shift, hook)
2126 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2127 class_shift, hook) \
2128 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2129 resume_early##hook, vendor, device, class, class_shift, hook)
2130 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2131 class_shift, hook) \
2132 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2133 suspend##hook, vendor, device, class, class_shift, hook)
2134 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2135 class_shift, hook) \
2136 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2137 suspend_late##hook, vendor, device, class, class_shift, hook)
2138
2139 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2140 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2141 hook, vendor, device, PCI_ANY_ID, 0, hook)
2142 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2143 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2144 hook, vendor, device, PCI_ANY_ID, 0, hook)
2145 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2146 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2147 hook, vendor, device, PCI_ANY_ID, 0, hook)
2148 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2149 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2150 hook, vendor, device, PCI_ANY_ID, 0, hook)
2151 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2152 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2153 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2154 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2155 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2156 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2157 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2158 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2159 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2160 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2161 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2162 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2163
2164 #ifdef CONFIG_PCI_QUIRKS
2165 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2166 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2167 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2168 struct pci_dev *dev) { }
2169 #endif
2170
2171 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2172 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2173 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2174 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2175 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2176 const char *name);
2177 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2178
2179 extern int pci_pci_problems;
2180 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2181 #define PCIPCI_TRITON 2
2182 #define PCIPCI_NATOMA 4
2183 #define PCIPCI_VIAETBF 8
2184 #define PCIPCI_VSFX 16
2185 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2186 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2187
2188 extern unsigned long pci_cardbus_io_size;
2189 extern unsigned long pci_cardbus_mem_size;
2190 extern u8 pci_dfl_cache_line_size;
2191 extern u8 pci_cache_line_size;
2192
2193 /* Architecture-specific versions may override these (weak) */
2194 void pcibios_disable_device(struct pci_dev *dev);
2195 void pcibios_set_master(struct pci_dev *dev);
2196 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2197 enum pcie_reset_state state);
2198 int pcibios_device_add(struct pci_dev *dev);
2199 void pcibios_release_device(struct pci_dev *dev);
2200 #ifdef CONFIG_PCI
2201 void pcibios_penalize_isa_irq(int irq, int active);
2202 #else
pcibios_penalize_isa_irq(int irq,int active)2203 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2204 #endif
2205 int pcibios_alloc_irq(struct pci_dev *dev);
2206 void pcibios_free_irq(struct pci_dev *dev);
2207 resource_size_t pcibios_default_alignment(void);
2208
2209 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2210 void __init pci_mmcfg_early_init(void);
2211 void __init pci_mmcfg_late_init(void);
2212 #else
pci_mmcfg_early_init(void)2213 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2214 static inline void pci_mmcfg_late_init(void) { }
2215 #endif
2216
2217 int pci_ext_cfg_avail(void);
2218
2219 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2220 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2221
2222 #ifdef CONFIG_PCI_IOV
2223 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2224 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2225 int pci_iov_vf_id(struct pci_dev *dev);
2226 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2227 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2228 void pci_disable_sriov(struct pci_dev *dev);
2229
2230 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2231 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2232 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2233 int pci_num_vf(struct pci_dev *dev);
2234 int pci_vfs_assigned(struct pci_dev *dev);
2235 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2236 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2237 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2238 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2239 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2240
2241 /* Arch may override these (weak) */
2242 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2243 int pcibios_sriov_disable(struct pci_dev *pdev);
2244 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2245 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2246 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2247 {
2248 return -ENOSYS;
2249 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2250 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2251 {
2252 return -ENOSYS;
2253 }
2254
pci_iov_vf_id(struct pci_dev * dev)2255 static inline int pci_iov_vf_id(struct pci_dev *dev)
2256 {
2257 return -ENOSYS;
2258 }
2259
pci_iov_get_pf_drvdata(struct pci_dev * dev,struct pci_driver * pf_driver)2260 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2261 struct pci_driver *pf_driver)
2262 {
2263 return ERR_PTR(-EINVAL);
2264 }
2265
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2266 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2267 { return -ENODEV; }
2268
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2269 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2270 struct pci_dev *virtfn, int id)
2271 {
2272 return -ENODEV;
2273 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2274 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2275 {
2276 return -ENOSYS;
2277 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2278 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2279 int id) { }
pci_disable_sriov(struct pci_dev * dev)2280 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2281 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2282 static inline int pci_vfs_assigned(struct pci_dev *dev)
2283 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2284 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2285 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2286 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2287 { return 0; }
2288 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2289 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2290 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2291 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2292 #endif
2293
2294 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2295 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2296 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2297 #endif
2298
2299 /**
2300 * pci_pcie_cap - get the saved PCIe capability offset
2301 * @dev: PCI device
2302 *
2303 * PCIe capability offset is calculated at PCI device initialization
2304 * time and saved in the data structure. This function returns saved
2305 * PCIe capability offset. Using this instead of pci_find_capability()
2306 * reduces unnecessary search in the PCI configuration space. If you
2307 * need to calculate PCIe capability offset from raw device for some
2308 * reasons, please use pci_find_capability() instead.
2309 */
pci_pcie_cap(struct pci_dev * dev)2310 static inline int pci_pcie_cap(struct pci_dev *dev)
2311 {
2312 return dev->pcie_cap;
2313 }
2314
2315 /**
2316 * pci_is_pcie - check if the PCI device is PCI Express capable
2317 * @dev: PCI device
2318 *
2319 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2320 */
pci_is_pcie(struct pci_dev * dev)2321 static inline bool pci_is_pcie(struct pci_dev *dev)
2322 {
2323 return pci_pcie_cap(dev);
2324 }
2325
2326 /**
2327 * pcie_caps_reg - get the PCIe Capabilities Register
2328 * @dev: PCI device
2329 */
pcie_caps_reg(const struct pci_dev * dev)2330 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2331 {
2332 return dev->pcie_flags_reg;
2333 }
2334
2335 /**
2336 * pci_pcie_type - get the PCIe device/port type
2337 * @dev: PCI device
2338 */
pci_pcie_type(const struct pci_dev * dev)2339 static inline int pci_pcie_type(const struct pci_dev *dev)
2340 {
2341 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2342 }
2343
2344 /**
2345 * pcie_find_root_port - Get the PCIe root port device
2346 * @dev: PCI device
2347 *
2348 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2349 * for a given PCI/PCIe Device.
2350 */
pcie_find_root_port(struct pci_dev * dev)2351 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2352 {
2353 while (dev) {
2354 if (pci_is_pcie(dev) &&
2355 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2356 return dev;
2357 dev = pci_upstream_bridge(dev);
2358 }
2359
2360 return NULL;
2361 }
2362
2363 void pci_request_acs(void);
2364 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2365 bool pci_acs_path_enabled(struct pci_dev *start,
2366 struct pci_dev *end, u16 acs_flags);
2367 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2368
2369 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2370 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2371
2372 /* Large Resource Data Type Tag Item Names */
2373 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2374 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2375 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2376
2377 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2378 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2379 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2380
2381 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2382 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2383 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2384 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2385 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2386
2387 /**
2388 * pci_vpd_alloc - Allocate buffer and read VPD into it
2389 * @dev: PCI device
2390 * @size: pointer to field where VPD length is returned
2391 *
2392 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2393 */
2394 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2395
2396 /**
2397 * pci_vpd_find_id_string - Locate id string in VPD
2398 * @buf: Pointer to buffered VPD data
2399 * @len: The length of the buffer area in which to search
2400 * @size: Pointer to field where length of id string is returned
2401 *
2402 * Returns the index of the id string or -ENOENT if not found.
2403 */
2404 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2405
2406 /**
2407 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2408 * @buf: Pointer to buffered VPD data
2409 * @len: The length of the buffer area in which to search
2410 * @kw: The keyword to search for
2411 * @size: Pointer to field where length of found keyword data is returned
2412 *
2413 * Returns the index of the information field keyword data or -ENOENT if
2414 * not found.
2415 */
2416 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2417 const char *kw, unsigned int *size);
2418
2419 /**
2420 * pci_vpd_check_csum - Check VPD checksum
2421 * @buf: Pointer to buffered VPD data
2422 * @len: VPD size
2423 *
2424 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2425 */
2426 int pci_vpd_check_csum(const void *buf, unsigned int len);
2427
2428 /* PCI <-> OF binding helpers */
2429 #ifdef CONFIG_OF
2430 struct device_node;
2431 struct irq_domain;
2432 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2433 bool pci_host_of_has_msi_map(struct device *dev);
2434
2435 /* Arch may override this (weak) */
2436 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2437
2438 #else /* CONFIG_OF */
2439 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2440 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2441 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2442 #endif /* CONFIG_OF */
2443
2444 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2445 pci_device_to_OF_node(const struct pci_dev *pdev)
2446 {
2447 return pdev ? pdev->dev.of_node : NULL;
2448 }
2449
pci_bus_to_OF_node(struct pci_bus * bus)2450 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2451 {
2452 return bus ? bus->dev.of_node : NULL;
2453 }
2454
2455 #ifdef CONFIG_ACPI
2456 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2457
2458 void
2459 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2460 bool pci_pr3_present(struct pci_dev *pdev);
2461 #else
2462 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2463 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2464 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2465 #endif
2466
2467 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2468 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2469 {
2470 return pdev->dev.archdata.edev;
2471 }
2472 #endif
2473
2474 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2475 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2476 int pci_for_each_dma_alias(struct pci_dev *pdev,
2477 int (*fn)(struct pci_dev *pdev,
2478 u16 alias, void *data), void *data);
2479
2480 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2481 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2482 {
2483 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2484 }
pci_clear_dev_assigned(struct pci_dev * pdev)2485 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2486 {
2487 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2488 }
pci_is_dev_assigned(struct pci_dev * pdev)2489 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2490 {
2491 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2492 }
2493
2494 /**
2495 * pci_ari_enabled - query ARI forwarding status
2496 * @bus: the PCI bus
2497 *
2498 * Returns true if ARI forwarding is enabled.
2499 */
pci_ari_enabled(struct pci_bus * bus)2500 static inline bool pci_ari_enabled(struct pci_bus *bus)
2501 {
2502 return bus->self && bus->self->ari_enabled;
2503 }
2504
2505 /**
2506 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2507 * @pdev: PCI device to check
2508 *
2509 * Walk upwards from @pdev and check for each encountered bridge if it's part
2510 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2511 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2512 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2513 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2514 {
2515 struct pci_dev *parent = pdev;
2516
2517 if (pdev->is_thunderbolt)
2518 return true;
2519
2520 while ((parent = pci_upstream_bridge(parent)))
2521 if (parent->is_thunderbolt)
2522 return true;
2523
2524 return false;
2525 }
2526
2527 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2528 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2529 #endif
2530
2531 struct msi_domain_template;
2532
2533 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
2534 unsigned int hwsize, void *data);
2535 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
2536 const struct irq_affinity_desc *affdesc);
2537 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
2538
2539 #include <linux/dma-mapping.h>
2540
2541 #define pci_printk(level, pdev, fmt, arg...) \
2542 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2543
2544 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2545 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2546 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2547 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2548 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2549 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2550 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2551 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2552 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2553
2554 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2555 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2556
2557 #define pci_info_ratelimited(pdev, fmt, arg...) \
2558 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2559
2560 #define pci_WARN(pdev, condition, fmt, arg...) \
2561 WARN(condition, "%s %s: " fmt, \
2562 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2563
2564 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2565 WARN_ONCE(condition, "%s %s: " fmt, \
2566 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2567
2568 #endif /* LINUX_PCI_H */
2569