1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This header defines architecture specific interfaces, x86 version
6 */
7
8 #ifndef _ASM_X86_KVM_HOST_H
9 #define _ASM_X86_KVM_HOST_H
10
11 #include <linux/types.h>
12 #include <linux/mm.h>
13 #include <linux/mmu_notifier.h>
14 #include <linux/tracepoint.h>
15 #include <linux/cpumask.h>
16 #include <linux/irq_work.h>
17 #include <linux/irq.h>
18 #include <linux/workqueue.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22 #include <linux/kvm_types.h>
23 #include <linux/perf_event.h>
24 #include <linux/pvclock_gtod.h>
25 #include <linux/clocksource.h>
26 #include <linux/irqbypass.h>
27 #include <linux/hyperv.h>
28 #include <linux/kfifo.h>
29
30 #include <asm/apic.h>
31 #include <asm/pvclock-abi.h>
32 #include <asm/desc.h>
33 #include <asm/mtrr.h>
34 #include <asm/msr-index.h>
35 #include <asm/asm.h>
36 #include <asm/kvm_page_track.h>
37 #include <asm/kvm_vcpu_regs.h>
38 #include <asm/hyperv-tlfs.h>
39
40 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS
41
42 #define KVM_MAX_VCPUS 1024
43
44 /*
45 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs
46 * might be larger than the actual number of VCPUs because the
47 * APIC ID encodes CPU topology information.
48 *
49 * In the worst case, we'll need less than one extra bit for the
50 * Core ID, and less than one extra bit for the Package (Die) ID,
51 * so ratio of 4 should be enough.
52 */
53 #define KVM_VCPU_ID_RATIO 4
54 #define KVM_MAX_VCPU_IDS (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO)
55
56 /* memory slots that are not exposed to userspace */
57 #define KVM_INTERNAL_MEM_SLOTS 3
58
59 #define KVM_HALT_POLL_NS_DEFAULT 200000
60
61 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
62
63 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
64 KVM_DIRTY_LOG_INITIALLY_SET)
65
66 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \
67 KVM_BUS_LOCK_DETECTION_EXIT)
68
69 #define KVM_X86_NOTIFY_VMEXIT_VALID_BITS (KVM_X86_NOTIFY_VMEXIT_ENABLED | \
70 KVM_X86_NOTIFY_VMEXIT_USER)
71
72 /* x86-specific vcpu->requests bit members */
73 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
74 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
75 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
76 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
77 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
78 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
79 #define KVM_REQ_EVENT KVM_ARCH_REQ(6)
80 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
81 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
82 #define KVM_REQ_NMI KVM_ARCH_REQ(9)
83 #define KVM_REQ_PMU KVM_ARCH_REQ(10)
84 #define KVM_REQ_PMI KVM_ARCH_REQ(11)
85 #ifdef CONFIG_KVM_SMM
86 #define KVM_REQ_SMI KVM_ARCH_REQ(12)
87 #endif
88 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
89 #define KVM_REQ_MCLOCK_INPROGRESS \
90 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
91 #define KVM_REQ_SCAN_IOAPIC \
92 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
93 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
94 #define KVM_REQ_APIC_PAGE_RELOAD \
95 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
96 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
97 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
98 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
99 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
100 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
101 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
102 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24)
103 #define KVM_REQ_APICV_UPDATE \
104 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
105 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26)
106 #define KVM_REQ_TLB_FLUSH_GUEST \
107 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
108 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28)
109 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29)
110 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \
111 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
112 #define KVM_REQ_MMU_FREE_OBSOLETE_ROOTS \
113 KVM_ARCH_REQ_FLAGS(31, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
114 #define KVM_REQ_HV_TLB_FLUSH \
115 KVM_ARCH_REQ_FLAGS(32, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
116
117 #define CR0_RESERVED_BITS \
118 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
119 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
120 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
121
122 #define CR4_RESERVED_BITS \
123 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
124 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
125 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
126 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
127 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
128 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
129
130 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
131
132
133
134 #define INVALID_PAGE (~(hpa_t)0)
135 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
136
137 /* KVM Hugepage definitions for x86 */
138 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
139 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
140 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
141 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
142 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
143 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
144 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
145
146 #define KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO 50
147 #define KVM_MIN_ALLOC_MMU_PAGES 64UL
148 #define KVM_MMU_HASH_SHIFT 12
149 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
150 #define KVM_MIN_FREE_MMU_PAGES 5
151 #define KVM_REFILL_PAGES 25
152 #define KVM_MAX_CPUID_ENTRIES 256
153 #define KVM_NR_FIXED_MTRR_REGION 88
154 #define KVM_NR_VAR_MTRR 8
155
156 #define ASYNC_PF_PER_VCPU 64
157
158 enum kvm_reg {
159 VCPU_REGS_RAX = __VCPU_REGS_RAX,
160 VCPU_REGS_RCX = __VCPU_REGS_RCX,
161 VCPU_REGS_RDX = __VCPU_REGS_RDX,
162 VCPU_REGS_RBX = __VCPU_REGS_RBX,
163 VCPU_REGS_RSP = __VCPU_REGS_RSP,
164 VCPU_REGS_RBP = __VCPU_REGS_RBP,
165 VCPU_REGS_RSI = __VCPU_REGS_RSI,
166 VCPU_REGS_RDI = __VCPU_REGS_RDI,
167 #ifdef CONFIG_X86_64
168 VCPU_REGS_R8 = __VCPU_REGS_R8,
169 VCPU_REGS_R9 = __VCPU_REGS_R9,
170 VCPU_REGS_R10 = __VCPU_REGS_R10,
171 VCPU_REGS_R11 = __VCPU_REGS_R11,
172 VCPU_REGS_R12 = __VCPU_REGS_R12,
173 VCPU_REGS_R13 = __VCPU_REGS_R13,
174 VCPU_REGS_R14 = __VCPU_REGS_R14,
175 VCPU_REGS_R15 = __VCPU_REGS_R15,
176 #endif
177 VCPU_REGS_RIP,
178 NR_VCPU_REGS,
179
180 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
181 VCPU_EXREG_CR0,
182 VCPU_EXREG_CR3,
183 VCPU_EXREG_CR4,
184 VCPU_EXREG_RFLAGS,
185 VCPU_EXREG_SEGMENTS,
186 VCPU_EXREG_EXIT_INFO_1,
187 VCPU_EXREG_EXIT_INFO_2,
188 };
189
190 enum {
191 VCPU_SREG_ES,
192 VCPU_SREG_CS,
193 VCPU_SREG_SS,
194 VCPU_SREG_DS,
195 VCPU_SREG_FS,
196 VCPU_SREG_GS,
197 VCPU_SREG_TR,
198 VCPU_SREG_LDTR,
199 };
200
201 enum exit_fastpath_completion {
202 EXIT_FASTPATH_NONE,
203 EXIT_FASTPATH_REENTER_GUEST,
204 EXIT_FASTPATH_EXIT_HANDLED,
205 };
206 typedef enum exit_fastpath_completion fastpath_t;
207
208 struct x86_emulate_ctxt;
209 struct x86_exception;
210 union kvm_smram;
211 enum x86_intercept;
212 enum x86_intercept_stage;
213
214 #define KVM_NR_DB_REGS 4
215
216 #define DR6_BUS_LOCK (1 << 11)
217 #define DR6_BD (1 << 13)
218 #define DR6_BS (1 << 14)
219 #define DR6_BT (1 << 15)
220 #define DR6_RTM (1 << 16)
221 /*
222 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
223 * We can regard all the bits in DR6_FIXED_1 as active_low bits;
224 * they will never be 0 for now, but when they are defined
225 * in the future it will require no code change.
226 *
227 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
228 */
229 #define DR6_ACTIVE_LOW 0xffff0ff0
230 #define DR6_VOLATILE 0x0001e80f
231 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
232
233 #define DR7_BP_EN_MASK 0x000000ff
234 #define DR7_GE (1 << 9)
235 #define DR7_GD (1 << 13)
236 #define DR7_FIXED_1 0x00000400
237 #define DR7_VOLATILE 0xffff2bff
238
239 #define KVM_GUESTDBG_VALID_MASK \
240 (KVM_GUESTDBG_ENABLE | \
241 KVM_GUESTDBG_SINGLESTEP | \
242 KVM_GUESTDBG_USE_HW_BP | \
243 KVM_GUESTDBG_USE_SW_BP | \
244 KVM_GUESTDBG_INJECT_BP | \
245 KVM_GUESTDBG_INJECT_DB | \
246 KVM_GUESTDBG_BLOCKIRQ)
247
248
249 #define PFERR_PRESENT_BIT 0
250 #define PFERR_WRITE_BIT 1
251 #define PFERR_USER_BIT 2
252 #define PFERR_RSVD_BIT 3
253 #define PFERR_FETCH_BIT 4
254 #define PFERR_PK_BIT 5
255 #define PFERR_SGX_BIT 15
256 #define PFERR_GUEST_FINAL_BIT 32
257 #define PFERR_GUEST_PAGE_BIT 33
258 #define PFERR_IMPLICIT_ACCESS_BIT 48
259
260 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT)
261 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT)
262 #define PFERR_USER_MASK BIT(PFERR_USER_BIT)
263 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT)
264 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT)
265 #define PFERR_PK_MASK BIT(PFERR_PK_BIT)
266 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT)
267 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT)
268 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT)
269 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT)
270
271 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
272 PFERR_WRITE_MASK | \
273 PFERR_PRESENT_MASK)
274
275 /* apic attention bits */
276 #define KVM_APIC_CHECK_VAPIC 0
277 /*
278 * The following bit is set with PV-EOI, unset on EOI.
279 * We detect PV-EOI changes by guest by comparing
280 * this bit with PV-EOI in guest memory.
281 * See the implementation in apic_update_pv_eoi.
282 */
283 #define KVM_APIC_PV_EOI_PENDING 1
284
285 struct kvm_kernel_irq_routing_entry;
286
287 /*
288 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page
289 * also includes TDP pages) to determine whether or not a page can be used in
290 * the given MMU context. This is a subset of the overall kvm_cpu_role to
291 * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating
292 * 2 bytes per gfn instead of 4 bytes per gfn.
293 *
294 * Upper-level shadow pages having gptes are tracked for write-protection via
295 * gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create
296 * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise
297 * gfn_track will overflow and explosions will ensure.
298 *
299 * A unique shadow page (SP) for a gfn is created if and only if an existing SP
300 * cannot be reused. The ability to reuse a SP is tracked by its role, which
301 * incorporates various mode bits and properties of the SP. Roughly speaking,
302 * the number of unique SPs that can theoretically be created is 2^n, where n
303 * is the number of bits that are used to compute the role.
304 *
305 * But, even though there are 19 bits in the mask below, not all combinations
306 * of modes and flags are possible:
307 *
308 * - invalid shadow pages are not accounted, so the bits are effectively 18
309 *
310 * - quadrant will only be used if has_4_byte_gpte=1 (non-PAE paging);
311 * execonly and ad_disabled are only used for nested EPT which has
312 * has_4_byte_gpte=0. Therefore, 2 bits are always unused.
313 *
314 * - the 4 bits of level are effectively limited to the values 2/3/4/5,
315 * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE
316 * paging has exactly one upper level, making level completely redundant
317 * when has_4_byte_gpte=1.
318 *
319 * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if
320 * cr0_wp=0, therefore these three bits only give rise to 5 possibilities.
321 *
322 * Therefore, the maximum number of possible upper-level shadow pages for a
323 * single gfn is a bit less than 2^13.
324 */
325 union kvm_mmu_page_role {
326 u32 word;
327 struct {
328 unsigned level:4;
329 unsigned has_4_byte_gpte:1;
330 unsigned quadrant:2;
331 unsigned direct:1;
332 unsigned access:3;
333 unsigned invalid:1;
334 unsigned efer_nx:1;
335 unsigned cr0_wp:1;
336 unsigned smep_andnot_wp:1;
337 unsigned smap_andnot_wp:1;
338 unsigned ad_disabled:1;
339 unsigned guest_mode:1;
340 unsigned passthrough:1;
341 unsigned :5;
342
343 /*
344 * This is left at the top of the word so that
345 * kvm_memslots_for_spte_role can extract it with a
346 * simple shift. While there is room, give it a whole
347 * byte so it is also faster to load it from memory.
348 */
349 unsigned smm:8;
350 };
351 };
352
353 /*
354 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties
355 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER,
356 * including on nested transitions, if nothing in the full role changes then
357 * MMU re-configuration can be skipped. @valid bit is set on first usage so we
358 * don't treat all-zero structure as valid data.
359 *
360 * The properties that are tracked in the extended role but not the page role
361 * are for things that either (a) do not affect the validity of the shadow page
362 * or (b) are indirectly reflected in the shadow page's role. For example,
363 * CR4.PKE only affects permission checks for software walks of the guest page
364 * tables (because KVM doesn't support Protection Keys with shadow paging), and
365 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level.
366 *
367 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role.
368 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and
369 * SMAP, but the MMU's permission checks for software walks need to be SMEP and
370 * SMAP aware regardless of CR0.WP.
371 */
372 union kvm_mmu_extended_role {
373 u32 word;
374 struct {
375 unsigned int valid:1;
376 unsigned int execonly:1;
377 unsigned int cr4_pse:1;
378 unsigned int cr4_pke:1;
379 unsigned int cr4_smap:1;
380 unsigned int cr4_smep:1;
381 unsigned int cr4_la57:1;
382 unsigned int efer_lma:1;
383 };
384 };
385
386 union kvm_cpu_role {
387 u64 as_u64;
388 struct {
389 union kvm_mmu_page_role base;
390 union kvm_mmu_extended_role ext;
391 };
392 };
393
394 struct kvm_rmap_head {
395 unsigned long val;
396 };
397
398 struct kvm_pio_request {
399 unsigned long linear_rip;
400 unsigned long count;
401 int in;
402 int port;
403 int size;
404 };
405
406 #define PT64_ROOT_MAX_LEVEL 5
407
408 struct rsvd_bits_validate {
409 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
410 u64 bad_mt_xwr;
411 };
412
413 struct kvm_mmu_root_info {
414 gpa_t pgd;
415 hpa_t hpa;
416 };
417
418 #define KVM_MMU_ROOT_INFO_INVALID \
419 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
420
421 #define KVM_MMU_NUM_PREV_ROOTS 3
422
423 #define KVM_HAVE_MMU_RWLOCK
424
425 struct kvm_mmu_page;
426 struct kvm_page_fault;
427
428 /*
429 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
430 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
431 * current mmu mode.
432 */
433 struct kvm_mmu {
434 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
435 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
436 int (*page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault);
437 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
438 struct x86_exception *fault);
439 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
440 gpa_t gva_or_gpa, u64 access,
441 struct x86_exception *exception);
442 int (*sync_page)(struct kvm_vcpu *vcpu,
443 struct kvm_mmu_page *sp);
444 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
445 struct kvm_mmu_root_info root;
446 union kvm_cpu_role cpu_role;
447 union kvm_mmu_page_role root_role;
448
449 /*
450 * The pkru_mask indicates if protection key checks are needed. It
451 * consists of 16 domains indexed by page fault error code bits [4:1],
452 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
453 * Each domain has 2 bits which are ANDed with AD and WD from PKRU.
454 */
455 u32 pkru_mask;
456
457 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
458
459 /*
460 * Bitmap; bit set = permission fault
461 * Byte index: page fault error code [4:1]
462 * Bit index: pte permissions in ACC_* format
463 */
464 u8 permissions[16];
465
466 u64 *pae_root;
467 u64 *pml4_root;
468 u64 *pml5_root;
469
470 /*
471 * check zero bits on shadow page table entries, these
472 * bits include not only hardware reserved bits but also
473 * the bits spte never used.
474 */
475 struct rsvd_bits_validate shadow_zero_check;
476
477 struct rsvd_bits_validate guest_rsvd_check;
478
479 u64 pdptrs[4]; /* pae */
480 };
481
482 struct kvm_tlb_range {
483 u64 start_gfn;
484 u64 pages;
485 };
486
487 enum pmc_type {
488 KVM_PMC_GP = 0,
489 KVM_PMC_FIXED,
490 };
491
492 struct kvm_pmc {
493 enum pmc_type type;
494 u8 idx;
495 bool is_paused;
496 bool intr;
497 u64 counter;
498 u64 prev_counter;
499 u64 eventsel;
500 struct perf_event *perf_event;
501 struct kvm_vcpu *vcpu;
502 /*
503 * only for creating or reusing perf_event,
504 * eventsel value for general purpose counters,
505 * ctrl value for fixed counters.
506 */
507 u64 current_config;
508 };
509
510 /* More counters may conflict with other existing Architectural MSRs */
511 #define KVM_INTEL_PMC_MAX_GENERIC 8
512 #define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
513 #define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
514 #define KVM_PMC_MAX_FIXED 3
515 #define MSR_ARCH_PERFMON_FIXED_CTR_MAX (MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_PMC_MAX_FIXED - 1)
516 #define KVM_AMD_PMC_MAX_GENERIC 6
517 struct kvm_pmu {
518 unsigned nr_arch_gp_counters;
519 unsigned nr_arch_fixed_counters;
520 unsigned available_event_types;
521 u64 fixed_ctr_ctrl;
522 u64 fixed_ctr_ctrl_mask;
523 u64 global_ctrl;
524 u64 global_status;
525 u64 counter_bitmask[2];
526 u64 global_ctrl_mask;
527 u64 global_ovf_ctrl_mask;
528 u64 reserved_bits;
529 u64 raw_event_mask;
530 u8 version;
531 struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC];
532 struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
533 struct irq_work irq_work;
534
535 /*
536 * Overlay the bitmap with a 64-bit atomic so that all bits can be
537 * set in a single access, e.g. to reprogram all counters when the PMU
538 * filter changes.
539 */
540 union {
541 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
542 atomic64_t __reprogram_pmi;
543 };
544 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
545 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
546
547 u64 ds_area;
548 u64 pebs_enable;
549 u64 pebs_enable_mask;
550 u64 pebs_data_cfg;
551 u64 pebs_data_cfg_mask;
552
553 /*
554 * If a guest counter is cross-mapped to host counter with different
555 * index, its PEBS capability will be temporarily disabled.
556 *
557 * The user should make sure that this mask is updated
558 * after disabling interrupts and before perf_guest_get_msrs();
559 */
560 u64 host_cross_mapped_mask;
561
562 /*
563 * The gate to release perf_events not marked in
564 * pmc_in_use only once in a vcpu time slice.
565 */
566 bool need_cleanup;
567
568 /*
569 * The total number of programmed perf_events and it helps to avoid
570 * redundant check before cleanup if guest don't use vPMU at all.
571 */
572 u8 event_count;
573 };
574
575 struct kvm_pmu_ops;
576
577 enum {
578 KVM_DEBUGREG_BP_ENABLED = 1,
579 KVM_DEBUGREG_WONT_EXIT = 2,
580 };
581
582 struct kvm_mtrr_range {
583 u64 base;
584 u64 mask;
585 struct list_head node;
586 };
587
588 struct kvm_mtrr {
589 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
590 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
591 u64 deftype;
592
593 struct list_head head;
594 };
595
596 /* Hyper-V SynIC timer */
597 struct kvm_vcpu_hv_stimer {
598 struct hrtimer timer;
599 int index;
600 union hv_stimer_config config;
601 u64 count;
602 u64 exp_time;
603 struct hv_message msg;
604 bool msg_pending;
605 };
606
607 /* Hyper-V synthetic interrupt controller (SynIC)*/
608 struct kvm_vcpu_hv_synic {
609 u64 version;
610 u64 control;
611 u64 msg_page;
612 u64 evt_page;
613 atomic64_t sint[HV_SYNIC_SINT_COUNT];
614 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
615 DECLARE_BITMAP(auto_eoi_bitmap, 256);
616 DECLARE_BITMAP(vec_bitmap, 256);
617 bool active;
618 bool dont_zero_synic_pages;
619 };
620
621 /* The maximum number of entries on the TLB flush fifo. */
622 #define KVM_HV_TLB_FLUSH_FIFO_SIZE (16)
623 /*
624 * Note: the following 'magic' entry is made up by KVM to avoid putting
625 * anything besides GVA on the TLB flush fifo. It is theoretically possible
626 * to observe a request to flush 4095 PFNs starting from 0xfffffffffffff000
627 * which will look identical. KVM's action to 'flush everything' instead of
628 * flushing these particular addresses is, however, fully legitimate as
629 * flushing more than requested is always OK.
630 */
631 #define KVM_HV_TLB_FLUSHALL_ENTRY ((u64)-1)
632
633 enum hv_tlb_flush_fifos {
634 HV_L1_TLB_FLUSH_FIFO,
635 HV_L2_TLB_FLUSH_FIFO,
636 HV_NR_TLB_FLUSH_FIFOS,
637 };
638
639 struct kvm_vcpu_hv_tlb_flush_fifo {
640 spinlock_t write_lock;
641 DECLARE_KFIFO(entries, u64, KVM_HV_TLB_FLUSH_FIFO_SIZE);
642 };
643
644 /* Hyper-V per vcpu emulation context */
645 struct kvm_vcpu_hv {
646 struct kvm_vcpu *vcpu;
647 u32 vp_index;
648 u64 hv_vapic;
649 s64 runtime_offset;
650 struct kvm_vcpu_hv_synic synic;
651 struct kvm_hyperv_exit exit;
652 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
653 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
654 bool enforce_cpuid;
655 struct {
656 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */
657 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */
658 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */
659 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */
660 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */
661 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */
662 u32 nested_eax; /* HYPERV_CPUID_NESTED_FEATURES.EAX */
663 u32 nested_ebx; /* HYPERV_CPUID_NESTED_FEATURES.EBX */
664 } cpuid_cache;
665
666 struct kvm_vcpu_hv_tlb_flush_fifo tlb_flush_fifo[HV_NR_TLB_FLUSH_FIFOS];
667
668 /* Preallocated buffer for handling hypercalls passing sparse vCPU set */
669 u64 sparse_banks[HV_MAX_SPARSE_VCPU_BANKS];
670
671 struct hv_vp_assist_page vp_assist_page;
672
673 struct {
674 u64 pa_page_gpa;
675 u64 vm_id;
676 u32 vp_id;
677 } nested;
678 };
679
680 struct kvm_hypervisor_cpuid {
681 u32 base;
682 u32 limit;
683 };
684
685 /* Xen HVM per vcpu emulation context */
686 struct kvm_vcpu_xen {
687 u64 hypercall_rip;
688 u32 current_runstate;
689 u8 upcall_vector;
690 struct gfn_to_pfn_cache vcpu_info_cache;
691 struct gfn_to_pfn_cache vcpu_time_info_cache;
692 struct gfn_to_pfn_cache runstate_cache;
693 struct gfn_to_pfn_cache runstate2_cache;
694 u64 last_steal;
695 u64 runstate_entry_time;
696 u64 runstate_times[4];
697 unsigned long evtchn_pending_sel;
698 u32 vcpu_id; /* The Xen / ACPI vCPU ID */
699 u32 timer_virq;
700 u64 timer_expires; /* In guest epoch */
701 atomic_t timer_pending;
702 struct hrtimer timer;
703 int poll_evtchn;
704 struct timer_list poll_timer;
705 struct kvm_hypervisor_cpuid cpuid;
706 };
707
708 struct kvm_queued_exception {
709 bool pending;
710 bool injected;
711 bool has_error_code;
712 u8 vector;
713 u32 error_code;
714 unsigned long payload;
715 bool has_payload;
716 };
717
718 struct kvm_vcpu_arch {
719 /*
720 * rip and regs accesses must go through
721 * kvm_{register,rip}_{read,write} functions.
722 */
723 unsigned long regs[NR_VCPU_REGS];
724 u32 regs_avail;
725 u32 regs_dirty;
726
727 unsigned long cr0;
728 unsigned long cr0_guest_owned_bits;
729 unsigned long cr2;
730 unsigned long cr3;
731 unsigned long cr4;
732 unsigned long cr4_guest_owned_bits;
733 unsigned long cr4_guest_rsvd_bits;
734 unsigned long cr8;
735 u32 host_pkru;
736 u32 pkru;
737 u32 hflags;
738 u64 efer;
739 u64 apic_base;
740 struct kvm_lapic *apic; /* kernel irqchip context */
741 bool load_eoi_exitmap_pending;
742 DECLARE_BITMAP(ioapic_handled_vectors, 256);
743 unsigned long apic_attention;
744 int32_t apic_arb_prio;
745 int mp_state;
746 u64 ia32_misc_enable_msr;
747 u64 smbase;
748 u64 smi_count;
749 bool at_instruction_boundary;
750 bool tpr_access_reporting;
751 bool xsaves_enabled;
752 bool xfd_no_write_intercept;
753 u64 ia32_xss;
754 u64 microcode_version;
755 u64 arch_capabilities;
756 u64 perf_capabilities;
757
758 /*
759 * Paging state of the vcpu
760 *
761 * If the vcpu runs in guest mode with two level paging this still saves
762 * the paging mode of the l1 guest. This context is always used to
763 * handle faults.
764 */
765 struct kvm_mmu *mmu;
766
767 /* Non-nested MMU for L1 */
768 struct kvm_mmu root_mmu;
769
770 /* L1 MMU when running nested */
771 struct kvm_mmu guest_mmu;
772
773 /*
774 * Paging state of an L2 guest (used for nested npt)
775 *
776 * This context will save all necessary information to walk page tables
777 * of an L2 guest. This context is only initialized for page table
778 * walking and not for faulting since we never handle l2 page faults on
779 * the host.
780 */
781 struct kvm_mmu nested_mmu;
782
783 /*
784 * Pointer to the mmu context currently used for
785 * gva_to_gpa translations.
786 */
787 struct kvm_mmu *walk_mmu;
788
789 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
790 struct kvm_mmu_memory_cache mmu_shadow_page_cache;
791 struct kvm_mmu_memory_cache mmu_shadowed_info_cache;
792 struct kvm_mmu_memory_cache mmu_page_header_cache;
793
794 /*
795 * QEMU userspace and the guest each have their own FPU state.
796 * In vcpu_run, we switch between the user and guest FPU contexts.
797 * While running a VCPU, the VCPU thread will have the guest FPU
798 * context.
799 *
800 * Note that while the PKRU state lives inside the fpu registers,
801 * it is switched out separately at VMENTER and VMEXIT time. The
802 * "guest_fpstate" state here contains the guest FPU context, with the
803 * host PRKU bits.
804 */
805 struct fpu_guest guest_fpu;
806
807 u64 xcr0;
808 u64 guest_supported_xcr0;
809
810 struct kvm_pio_request pio;
811 void *pio_data;
812 void *sev_pio_data;
813 unsigned sev_pio_count;
814
815 u8 event_exit_inst_len;
816
817 bool exception_from_userspace;
818
819 /* Exceptions to be injected to the guest. */
820 struct kvm_queued_exception exception;
821 /* Exception VM-Exits to be synthesized to L1. */
822 struct kvm_queued_exception exception_vmexit;
823
824 struct kvm_queued_interrupt {
825 bool injected;
826 bool soft;
827 u8 nr;
828 } interrupt;
829
830 int halt_request; /* real mode on Intel only */
831
832 int cpuid_nent;
833 struct kvm_cpuid_entry2 *cpuid_entries;
834 struct kvm_hypervisor_cpuid kvm_cpuid;
835
836 u64 reserved_gpa_bits;
837 int maxphyaddr;
838
839 /* emulate context */
840
841 struct x86_emulate_ctxt *emulate_ctxt;
842 bool emulate_regs_need_sync_to_vcpu;
843 bool emulate_regs_need_sync_from_vcpu;
844 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
845
846 gpa_t time;
847 struct pvclock_vcpu_time_info hv_clock;
848 unsigned int hw_tsc_khz;
849 struct gfn_to_pfn_cache pv_time;
850 /* set guest stopped flag in pvclock flags field */
851 bool pvclock_set_guest_stopped_request;
852
853 struct {
854 u8 preempted;
855 u64 msr_val;
856 u64 last_steal;
857 struct gfn_to_hva_cache cache;
858 } st;
859
860 u64 l1_tsc_offset;
861 u64 tsc_offset; /* current tsc offset */
862 u64 last_guest_tsc;
863 u64 last_host_tsc;
864 u64 tsc_offset_adjustment;
865 u64 this_tsc_nsec;
866 u64 this_tsc_write;
867 u64 this_tsc_generation;
868 bool tsc_catchup;
869 bool tsc_always_catchup;
870 s8 virtual_tsc_shift;
871 u32 virtual_tsc_mult;
872 u32 virtual_tsc_khz;
873 s64 ia32_tsc_adjust_msr;
874 u64 msr_ia32_power_ctl;
875 u64 l1_tsc_scaling_ratio;
876 u64 tsc_scaling_ratio; /* current scaling ratio */
877
878 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
879 unsigned nmi_pending; /* NMI queued after currently running handler */
880 bool nmi_injected; /* Trying to inject an NMI this entry */
881 bool smi_pending; /* SMI queued after currently running handler */
882 u8 handling_intr_from_guest;
883
884 struct kvm_mtrr mtrr_state;
885 u64 pat;
886
887 unsigned switch_db_regs;
888 unsigned long db[KVM_NR_DB_REGS];
889 unsigned long dr6;
890 unsigned long dr7;
891 unsigned long eff_db[KVM_NR_DB_REGS];
892 unsigned long guest_debug_dr7;
893 u64 msr_platform_info;
894 u64 msr_misc_features_enables;
895
896 u64 mcg_cap;
897 u64 mcg_status;
898 u64 mcg_ctl;
899 u64 mcg_ext_ctl;
900 u64 *mce_banks;
901 u64 *mci_ctl2_banks;
902
903 /* Cache MMIO info */
904 u64 mmio_gva;
905 unsigned mmio_access;
906 gfn_t mmio_gfn;
907 u64 mmio_gen;
908
909 struct kvm_pmu pmu;
910
911 /* used for guest single stepping over the given code position */
912 unsigned long singlestep_rip;
913
914 bool hyperv_enabled;
915 struct kvm_vcpu_hv *hyperv;
916 struct kvm_vcpu_xen xen;
917
918 cpumask_var_t wbinvd_dirty_mask;
919
920 unsigned long last_retry_eip;
921 unsigned long last_retry_addr;
922
923 struct {
924 bool halted;
925 gfn_t gfns[ASYNC_PF_PER_VCPU];
926 struct gfn_to_hva_cache data;
927 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */
928 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */
929 u16 vec;
930 u32 id;
931 bool send_user_only;
932 u32 host_apf_flags;
933 bool delivery_as_pf_vmexit;
934 bool pageready_pending;
935 } apf;
936
937 /* OSVW MSRs (AMD only) */
938 struct {
939 u64 length;
940 u64 status;
941 } osvw;
942
943 struct {
944 u64 msr_val;
945 struct gfn_to_hva_cache data;
946 } pv_eoi;
947
948 u64 msr_kvm_poll_control;
949
950 /*
951 * Indicates the guest is trying to write a gfn that contains one or
952 * more of the PTEs used to translate the write itself, i.e. the access
953 * is changing its own translation in the guest page tables. KVM exits
954 * to userspace if emulation of the faulting instruction fails and this
955 * flag is set, as KVM cannot make forward progress.
956 *
957 * If emulation fails for a write to guest page tables, KVM unprotects
958 * (zaps) the shadow page for the target gfn and resumes the guest to
959 * retry the non-emulatable instruction (on hardware). Unprotecting the
960 * gfn doesn't allow forward progress for a self-changing access because
961 * doing so also zaps the translation for the gfn, i.e. retrying the
962 * instruction will hit a !PRESENT fault, which results in a new shadow
963 * page and sends KVM back to square one.
964 */
965 bool write_fault_to_shadow_pgtable;
966
967 /* set at EPT violation at this point */
968 unsigned long exit_qualification;
969
970 /* pv related host specific info */
971 struct {
972 bool pv_unhalted;
973 } pv;
974
975 int pending_ioapic_eoi;
976 int pending_external_vector;
977
978 /* be preempted when it's in kernel-mode(cpl=0) */
979 bool preempted_in_kernel;
980
981 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */
982 bool l1tf_flush_l1d;
983
984 /* Host CPU on which VM-entry was most recently attempted */
985 int last_vmentry_cpu;
986
987 /* AMD MSRC001_0015 Hardware Configuration */
988 u64 msr_hwcr;
989
990 /* pv related cpuid info */
991 struct {
992 /*
993 * value of the eax register in the KVM_CPUID_FEATURES CPUID
994 * leaf.
995 */
996 u32 features;
997
998 /*
999 * indicates whether pv emulation should be disabled if features
1000 * are not present in the guest's cpuid
1001 */
1002 bool enforce;
1003 } pv_cpuid;
1004
1005 /* Protected Guests */
1006 bool guest_state_protected;
1007
1008 /*
1009 * Set when PDPTS were loaded directly by the userspace without
1010 * reading the guest memory
1011 */
1012 bool pdptrs_from_userspace;
1013
1014 #if IS_ENABLED(CONFIG_HYPERV)
1015 hpa_t hv_root_tdp;
1016 #endif
1017 };
1018
1019 struct kvm_lpage_info {
1020 int disallow_lpage;
1021 };
1022
1023 struct kvm_arch_memory_slot {
1024 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
1025 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
1026 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
1027 };
1028
1029 /*
1030 * Track the mode of the optimized logical map, as the rules for decoding the
1031 * destination vary per mode. Enabling the optimized logical map requires all
1032 * software-enabled local APIs to be in the same mode, each addressable APIC to
1033 * be mapped to only one MDA, and each MDA to map to at most one APIC.
1034 */
1035 enum kvm_apic_logical_mode {
1036 /* All local APICs are software disabled. */
1037 KVM_APIC_MODE_SW_DISABLED,
1038 /* All software enabled local APICs in xAPIC cluster addressing mode. */
1039 KVM_APIC_MODE_XAPIC_CLUSTER,
1040 /* All software enabled local APICs in xAPIC flat addressing mode. */
1041 KVM_APIC_MODE_XAPIC_FLAT,
1042 /* All software enabled local APICs in x2APIC mode. */
1043 KVM_APIC_MODE_X2APIC,
1044 /*
1045 * Optimized map disabled, e.g. not all local APICs in the same logical
1046 * mode, same logical ID assigned to multiple APICs, etc.
1047 */
1048 KVM_APIC_MODE_MAP_DISABLED,
1049 };
1050
1051 struct kvm_apic_map {
1052 struct rcu_head rcu;
1053 enum kvm_apic_logical_mode logical_mode;
1054 u32 max_apic_id;
1055 union {
1056 struct kvm_lapic *xapic_flat_map[8];
1057 struct kvm_lapic *xapic_cluster_map[16][4];
1058 };
1059 struct kvm_lapic *phys_map[];
1060 };
1061
1062 /* Hyper-V synthetic debugger (SynDbg)*/
1063 struct kvm_hv_syndbg {
1064 struct {
1065 u64 control;
1066 u64 status;
1067 u64 send_page;
1068 u64 recv_page;
1069 u64 pending_page;
1070 } control;
1071 u64 options;
1072 };
1073
1074 /* Current state of Hyper-V TSC page clocksource */
1075 enum hv_tsc_page_status {
1076 /* TSC page was not set up or disabled */
1077 HV_TSC_PAGE_UNSET = 0,
1078 /* TSC page MSR was written by the guest, update pending */
1079 HV_TSC_PAGE_GUEST_CHANGED,
1080 /* TSC page update was triggered from the host side */
1081 HV_TSC_PAGE_HOST_CHANGED,
1082 /* TSC page was properly set up and is currently active */
1083 HV_TSC_PAGE_SET,
1084 /* TSC page was set up with an inaccessible GPA */
1085 HV_TSC_PAGE_BROKEN,
1086 };
1087
1088 /* Hyper-V emulation context */
1089 struct kvm_hv {
1090 struct mutex hv_lock;
1091 u64 hv_guest_os_id;
1092 u64 hv_hypercall;
1093 u64 hv_tsc_page;
1094 enum hv_tsc_page_status hv_tsc_page_status;
1095
1096 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */
1097 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
1098 u64 hv_crash_ctl;
1099
1100 struct ms_hyperv_tsc_page tsc_ref;
1101
1102 struct idr conn_to_evt;
1103
1104 u64 hv_reenlightenment_control;
1105 u64 hv_tsc_emulation_control;
1106 u64 hv_tsc_emulation_status;
1107 u64 hv_invtsc_control;
1108
1109 /* How many vCPUs have VP index != vCPU index */
1110 atomic_t num_mismatched_vp_indexes;
1111
1112 /*
1113 * How many SynICs use 'AutoEOI' feature
1114 * (protected by arch.apicv_update_lock)
1115 */
1116 unsigned int synic_auto_eoi_used;
1117
1118 struct hv_partition_assist_pg *hv_pa_pg;
1119 struct kvm_hv_syndbg hv_syndbg;
1120 };
1121
1122 struct msr_bitmap_range {
1123 u32 flags;
1124 u32 nmsrs;
1125 u32 base;
1126 unsigned long *bitmap;
1127 };
1128
1129 /* Xen emulation context */
1130 struct kvm_xen {
1131 struct mutex xen_lock;
1132 u32 xen_version;
1133 bool long_mode;
1134 bool runstate_update_flag;
1135 u8 upcall_vector;
1136 struct gfn_to_pfn_cache shinfo_cache;
1137 struct idr evtchn_ports;
1138 unsigned long poll_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)];
1139 };
1140
1141 enum kvm_irqchip_mode {
1142 KVM_IRQCHIP_NONE,
1143 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
1144 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
1145 };
1146
1147 struct kvm_x86_msr_filter {
1148 u8 count;
1149 bool default_allow:1;
1150 struct msr_bitmap_range ranges[16];
1151 };
1152
1153 struct kvm_x86_pmu_event_filter {
1154 __u32 action;
1155 __u32 nevents;
1156 __u32 fixed_counter_bitmap;
1157 __u32 flags;
1158 __u32 nr_includes;
1159 __u32 nr_excludes;
1160 __u64 *includes;
1161 __u64 *excludes;
1162 __u64 events[];
1163 };
1164
1165 enum kvm_apicv_inhibit {
1166
1167 /********************************************************************/
1168 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
1169 /********************************************************************/
1170
1171 /*
1172 * APIC acceleration is disabled by a module parameter
1173 * and/or not supported in hardware.
1174 */
1175 APICV_INHIBIT_REASON_DISABLE,
1176
1177 /*
1178 * APIC acceleration is inhibited because AutoEOI feature is
1179 * being used by a HyperV guest.
1180 */
1181 APICV_INHIBIT_REASON_HYPERV,
1182
1183 /*
1184 * APIC acceleration is inhibited because the userspace didn't yet
1185 * enable the kernel/split irqchip.
1186 */
1187 APICV_INHIBIT_REASON_ABSENT,
1188
1189 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ
1190 * (out of band, debug measure of blocking all interrupts on this vCPU)
1191 * was enabled, to avoid AVIC/APICv bypassing it.
1192 */
1193 APICV_INHIBIT_REASON_BLOCKIRQ,
1194
1195 /*
1196 * APICv is disabled because not all vCPUs have a 1:1 mapping between
1197 * APIC ID and vCPU, _and_ KVM is not applying its x2APIC hotplug hack.
1198 */
1199 APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED,
1200
1201 /*
1202 * For simplicity, the APIC acceleration is inhibited
1203 * first time either APIC ID or APIC base are changed by the guest
1204 * from their reset values.
1205 */
1206 APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
1207 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
1208
1209 /******************************************************/
1210 /* INHIBITs that are relevant only to the AMD's AVIC. */
1211 /******************************************************/
1212
1213 /*
1214 * AVIC is inhibited on a vCPU because it runs a nested guest.
1215 *
1216 * This is needed because unlike APICv, the peers of this vCPU
1217 * cannot use the doorbell mechanism to signal interrupts via AVIC when
1218 * a vCPU runs nested.
1219 */
1220 APICV_INHIBIT_REASON_NESTED,
1221
1222 /*
1223 * On SVM, the wait for the IRQ window is implemented with pending vIRQ,
1224 * which cannot be injected when the AVIC is enabled, thus AVIC
1225 * is inhibited while KVM waits for IRQ window.
1226 */
1227 APICV_INHIBIT_REASON_IRQWIN,
1228
1229 /*
1230 * PIT (i8254) 're-inject' mode, relies on EOI intercept,
1231 * which AVIC doesn't support for edge triggered interrupts.
1232 */
1233 APICV_INHIBIT_REASON_PIT_REINJ,
1234
1235 /*
1236 * AVIC is disabled because SEV doesn't support it.
1237 */
1238 APICV_INHIBIT_REASON_SEV,
1239
1240 /*
1241 * AVIC is disabled because not all vCPUs with a valid LDR have a 1:1
1242 * mapping between logical ID and vCPU.
1243 */
1244 APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED,
1245 };
1246
1247 struct kvm_arch {
1248 unsigned long n_used_mmu_pages;
1249 unsigned long n_requested_mmu_pages;
1250 unsigned long n_max_mmu_pages;
1251 unsigned int indirect_shadow_pages;
1252 u8 mmu_valid_gen;
1253 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
1254 struct list_head active_mmu_pages;
1255 struct list_head zapped_obsolete_pages;
1256 /*
1257 * A list of kvm_mmu_page structs that, if zapped, could possibly be
1258 * replaced by an NX huge page. A shadow page is on this list if its
1259 * existence disallows an NX huge page (nx_huge_page_disallowed is set)
1260 * and there are no other conditions that prevent a huge page, e.g.
1261 * the backing host page is huge, dirtly logging is not enabled for its
1262 * memslot, etc... Note, zapping shadow pages on this list doesn't
1263 * guarantee an NX huge page will be created in its stead, e.g. if the
1264 * guest attempts to execute from the region then KVM obviously can't
1265 * create an NX huge page (without hanging the guest).
1266 */
1267 struct list_head possible_nx_huge_pages;
1268 struct kvm_page_track_notifier_node mmu_sp_tracker;
1269 struct kvm_page_track_notifier_head track_notifier_head;
1270 /*
1271 * Protects marking pages unsync during page faults, as TDP MMU page
1272 * faults only take mmu_lock for read. For simplicity, the unsync
1273 * pages lock is always taken when marking pages unsync regardless of
1274 * whether mmu_lock is held for read or write.
1275 */
1276 spinlock_t mmu_unsync_pages_lock;
1277
1278 struct list_head assigned_dev_head;
1279 struct iommu_domain *iommu_domain;
1280 bool iommu_noncoherent;
1281 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA
1282 atomic_t noncoherent_dma_count;
1283 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
1284 atomic_t assigned_device_count;
1285 struct kvm_pic *vpic;
1286 struct kvm_ioapic *vioapic;
1287 struct kvm_pit *vpit;
1288 atomic_t vapics_in_nmi_mode;
1289 struct mutex apic_map_lock;
1290 struct kvm_apic_map __rcu *apic_map;
1291 atomic_t apic_map_dirty;
1292
1293 bool apic_access_memslot_enabled;
1294 bool apic_access_memslot_inhibited;
1295
1296 /* Protects apicv_inhibit_reasons */
1297 struct rw_semaphore apicv_update_lock;
1298 unsigned long apicv_inhibit_reasons;
1299
1300 gpa_t wall_clock;
1301
1302 bool mwait_in_guest;
1303 bool hlt_in_guest;
1304 bool pause_in_guest;
1305 bool cstate_in_guest;
1306
1307 unsigned long irq_sources_bitmap;
1308 s64 kvmclock_offset;
1309
1310 /*
1311 * This also protects nr_vcpus_matched_tsc which is read from a
1312 * preemption-disabled region, so it must be a raw spinlock.
1313 */
1314 raw_spinlock_t tsc_write_lock;
1315 u64 last_tsc_nsec;
1316 u64 last_tsc_write;
1317 u32 last_tsc_khz;
1318 u64 last_tsc_offset;
1319 u64 cur_tsc_nsec;
1320 u64 cur_tsc_write;
1321 u64 cur_tsc_offset;
1322 u64 cur_tsc_generation;
1323 int nr_vcpus_matched_tsc;
1324
1325 u32 default_tsc_khz;
1326
1327 seqcount_raw_spinlock_t pvclock_sc;
1328 bool use_master_clock;
1329 u64 master_kernel_ns;
1330 u64 master_cycle_now;
1331 struct delayed_work kvmclock_update_work;
1332 struct delayed_work kvmclock_sync_work;
1333
1334 struct kvm_xen_hvm_config xen_hvm_config;
1335
1336 /* reads protected by irq_srcu, writes by irq_lock */
1337 struct hlist_head mask_notifier_list;
1338
1339 struct kvm_hv hyperv;
1340 struct kvm_xen xen;
1341
1342 bool backwards_tsc_observed;
1343 bool boot_vcpu_runs_old_kvmclock;
1344 u32 bsp_vcpu_id;
1345
1346 u64 disabled_quirks;
1347
1348 enum kvm_irqchip_mode irqchip_mode;
1349 u8 nr_reserved_ioapic_pins;
1350
1351 bool disabled_lapic_found;
1352
1353 bool x2apic_format;
1354 bool x2apic_broadcast_quirk_disabled;
1355
1356 bool guest_can_read_msr_platform_info;
1357 bool exception_payload_enabled;
1358
1359 bool triple_fault_event;
1360
1361 bool bus_lock_detection_enabled;
1362 bool enable_pmu;
1363
1364 u32 notify_window;
1365 u32 notify_vmexit_flags;
1366 /*
1367 * If exit_on_emulation_error is set, and the in-kernel instruction
1368 * emulator fails to emulate an instruction, allow userspace
1369 * the opportunity to look at it.
1370 */
1371 bool exit_on_emulation_error;
1372
1373 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */
1374 u32 user_space_msr_mask;
1375 struct kvm_x86_msr_filter __rcu *msr_filter;
1376
1377 u32 hypercall_exit_enabled;
1378
1379 /* Guest can access the SGX PROVISIONKEY. */
1380 bool sgx_provisioning_allowed;
1381
1382 struct kvm_x86_pmu_event_filter __rcu *pmu_event_filter;
1383 struct task_struct *nx_huge_page_recovery_thread;
1384
1385 #ifdef CONFIG_X86_64
1386 /* The number of TDP MMU pages across all roots. */
1387 atomic64_t tdp_mmu_pages;
1388
1389 /*
1390 * List of struct kvm_mmu_pages being used as roots.
1391 * All struct kvm_mmu_pages in the list should have
1392 * tdp_mmu_page set.
1393 *
1394 * For reads, this list is protected by:
1395 * the MMU lock in read mode + RCU or
1396 * the MMU lock in write mode
1397 *
1398 * For writes, this list is protected by:
1399 * the MMU lock in read mode + the tdp_mmu_pages_lock or
1400 * the MMU lock in write mode
1401 *
1402 * Roots will remain in the list until their tdp_mmu_root_count
1403 * drops to zero, at which point the thread that decremented the
1404 * count to zero should removed the root from the list and clean
1405 * it up, freeing the root after an RCU grace period.
1406 */
1407 struct list_head tdp_mmu_roots;
1408
1409 /*
1410 * Protects accesses to the following fields when the MMU lock
1411 * is held in read mode:
1412 * - tdp_mmu_roots (above)
1413 * - the link field of kvm_mmu_page structs used by the TDP MMU
1414 * - possible_nx_huge_pages;
1415 * - the possible_nx_huge_page_link field of kvm_mmu_page structs used
1416 * by the TDP MMU
1417 * It is acceptable, but not necessary, to acquire this lock when
1418 * the thread holds the MMU lock in write mode.
1419 */
1420 spinlock_t tdp_mmu_pages_lock;
1421 struct workqueue_struct *tdp_mmu_zap_wq;
1422 #endif /* CONFIG_X86_64 */
1423
1424 /*
1425 * If set, at least one shadow root has been allocated. This flag
1426 * is used as one input when determining whether certain memslot
1427 * related allocations are necessary.
1428 */
1429 bool shadow_root_allocated;
1430
1431 #if IS_ENABLED(CONFIG_HYPERV)
1432 hpa_t hv_root_tdp;
1433 spinlock_t hv_root_tdp_lock;
1434 #endif
1435 /*
1436 * VM-scope maximum vCPU ID. Used to determine the size of structures
1437 * that increase along with the maximum vCPU ID, in which case, using
1438 * the global KVM_MAX_VCPU_IDS may lead to significant memory waste.
1439 */
1440 u32 max_vcpu_ids;
1441
1442 bool disable_nx_huge_pages;
1443
1444 /*
1445 * Memory caches used to allocate shadow pages when performing eager
1446 * page splitting. No need for a shadowed_info_cache since eager page
1447 * splitting only allocates direct shadow pages.
1448 *
1449 * Protected by kvm->slots_lock.
1450 */
1451 struct kvm_mmu_memory_cache split_shadow_page_cache;
1452 struct kvm_mmu_memory_cache split_page_header_cache;
1453
1454 /*
1455 * Memory cache used to allocate pte_list_desc structs while splitting
1456 * huge pages. In the worst case, to split one huge page, 512
1457 * pte_list_desc structs are needed to add each lower level leaf sptep
1458 * to the rmap plus 1 to extend the parent_ptes rmap of the lower level
1459 * page table.
1460 *
1461 * Protected by kvm->slots_lock.
1462 */
1463 #define SPLIT_DESC_CACHE_MIN_NR_OBJECTS (SPTE_ENT_PER_PAGE + 1)
1464 struct kvm_mmu_memory_cache split_desc_cache;
1465 };
1466
1467 struct kvm_vm_stat {
1468 struct kvm_vm_stat_generic generic;
1469 u64 mmu_shadow_zapped;
1470 u64 mmu_pte_write;
1471 u64 mmu_pde_zapped;
1472 u64 mmu_flooded;
1473 u64 mmu_recycled;
1474 u64 mmu_cache_miss;
1475 u64 mmu_unsync;
1476 union {
1477 struct {
1478 atomic64_t pages_4k;
1479 atomic64_t pages_2m;
1480 atomic64_t pages_1g;
1481 };
1482 atomic64_t pages[KVM_NR_PAGE_SIZES];
1483 };
1484 u64 nx_lpage_splits;
1485 u64 max_mmu_page_hash_collisions;
1486 u64 max_mmu_rmap_size;
1487 };
1488
1489 struct kvm_vcpu_stat {
1490 struct kvm_vcpu_stat_generic generic;
1491 u64 pf_taken;
1492 u64 pf_fixed;
1493 u64 pf_emulate;
1494 u64 pf_spurious;
1495 u64 pf_fast;
1496 u64 pf_mmio_spte_created;
1497 u64 pf_guest;
1498 u64 tlb_flush;
1499 u64 invlpg;
1500
1501 u64 exits;
1502 u64 io_exits;
1503 u64 mmio_exits;
1504 u64 signal_exits;
1505 u64 irq_window_exits;
1506 u64 nmi_window_exits;
1507 u64 l1d_flush;
1508 u64 halt_exits;
1509 u64 request_irq_exits;
1510 u64 irq_exits;
1511 u64 host_state_reload;
1512 u64 fpu_reload;
1513 u64 insn_emulation;
1514 u64 insn_emulation_fail;
1515 u64 hypercalls;
1516 u64 irq_injections;
1517 u64 nmi_injections;
1518 u64 req_event;
1519 u64 nested_run;
1520 u64 directed_yield_attempted;
1521 u64 directed_yield_successful;
1522 u64 preemption_reported;
1523 u64 preemption_other;
1524 u64 guest_mode;
1525 u64 notify_window_exits;
1526 };
1527
1528 struct x86_instruction_info;
1529
1530 struct msr_data {
1531 bool host_initiated;
1532 u32 index;
1533 u64 data;
1534 };
1535
1536 struct kvm_lapic_irq {
1537 u32 vector;
1538 u16 delivery_mode;
1539 u16 dest_mode;
1540 bool level;
1541 u16 trig_mode;
1542 u32 shorthand;
1543 u32 dest_id;
1544 bool msi_redir_hint;
1545 };
1546
kvm_lapic_irq_dest_mode(bool dest_mode_logical)1547 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical)
1548 {
1549 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
1550 }
1551
1552 struct kvm_x86_ops {
1553 const char *name;
1554
1555 int (*check_processor_compatibility)(void);
1556
1557 int (*hardware_enable)(void);
1558 void (*hardware_disable)(void);
1559 void (*hardware_unsetup)(void);
1560 bool (*has_emulated_msr)(struct kvm *kvm, u32 index);
1561 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu);
1562
1563 unsigned int vm_size;
1564 int (*vm_init)(struct kvm *kvm);
1565 void (*vm_destroy)(struct kvm *kvm);
1566
1567 /* Create, but do not attach this VCPU */
1568 int (*vcpu_precreate)(struct kvm *kvm);
1569 int (*vcpu_create)(struct kvm_vcpu *vcpu);
1570 void (*vcpu_free)(struct kvm_vcpu *vcpu);
1571 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
1572
1573 void (*prepare_switch_to_guest)(struct kvm_vcpu *vcpu);
1574 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
1575 void (*vcpu_put)(struct kvm_vcpu *vcpu);
1576
1577 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu);
1578 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1579 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
1580 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
1581 void (*get_segment)(struct kvm_vcpu *vcpu,
1582 struct kvm_segment *var, int seg);
1583 int (*get_cpl)(struct kvm_vcpu *vcpu);
1584 void (*set_segment)(struct kvm_vcpu *vcpu,
1585 struct kvm_segment *var, int seg);
1586 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
1587 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
1588 void (*post_set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
1589 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0);
1590 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
1591 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
1592 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1593 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1594 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1595 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
1596 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
1597 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
1598 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
1599 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
1600 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
1601 bool (*get_if_flag)(struct kvm_vcpu *vcpu);
1602
1603 void (*flush_tlb_all)(struct kvm_vcpu *vcpu);
1604 void (*flush_tlb_current)(struct kvm_vcpu *vcpu);
1605 int (*tlb_remote_flush)(struct kvm *kvm);
1606 int (*tlb_remote_flush_with_range)(struct kvm *kvm,
1607 struct kvm_tlb_range *range);
1608
1609 /*
1610 * Flush any TLB entries associated with the given GVA.
1611 * Does not need to flush GPA->HPA mappings.
1612 * Can potentially get non-canonical addresses through INVLPGs, which
1613 * the implementation may choose to ignore if appropriate.
1614 */
1615 void (*flush_tlb_gva)(struct kvm_vcpu *vcpu, gva_t addr);
1616
1617 /*
1618 * Flush any TLB entries created by the guest. Like tlb_flush_gva(),
1619 * does not need to flush GPA->HPA mappings.
1620 */
1621 void (*flush_tlb_guest)(struct kvm_vcpu *vcpu);
1622
1623 int (*vcpu_pre_run)(struct kvm_vcpu *vcpu);
1624 enum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *vcpu);
1625 int (*handle_exit)(struct kvm_vcpu *vcpu,
1626 enum exit_fastpath_completion exit_fastpath);
1627 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
1628 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
1629 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
1630 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
1631 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
1632 unsigned char *hypercall_addr);
1633 void (*inject_irq)(struct kvm_vcpu *vcpu, bool reinjected);
1634 void (*inject_nmi)(struct kvm_vcpu *vcpu);
1635 void (*inject_exception)(struct kvm_vcpu *vcpu);
1636 void (*cancel_injection)(struct kvm_vcpu *vcpu);
1637 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1638 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1639 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
1640 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
1641 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
1642 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
1643 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
1644 bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason);
1645 const unsigned long required_apicv_inhibits;
1646 bool allow_apicv_in_x2apic_without_x2apic_virtualization;
1647 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
1648 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
1649 void (*hwapic_isr_update)(int isr);
1650 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
1651 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
1652 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
1653 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
1654 void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode,
1655 int trig_mode, int vector);
1656 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
1657 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
1658 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
1659 u8 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
1660
1661 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa,
1662 int root_level);
1663
1664 bool (*has_wbinvd_exit)(void);
1665
1666 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu);
1667 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu);
1668 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
1669 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu, u64 multiplier);
1670
1671 /*
1672 * Retrieve somewhat arbitrary exit information. Intended to
1673 * be used only from within tracepoints or error paths.
1674 */
1675 void (*get_exit_info)(struct kvm_vcpu *vcpu, u32 *reason,
1676 u64 *info1, u64 *info2,
1677 u32 *exit_int_info, u32 *exit_int_info_err_code);
1678
1679 int (*check_intercept)(struct kvm_vcpu *vcpu,
1680 struct x86_instruction_info *info,
1681 enum x86_intercept_stage stage,
1682 struct x86_exception *exception);
1683 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu);
1684
1685 void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
1686
1687 void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
1688
1689 /*
1690 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero
1691 * value indicates CPU dirty logging is unsupported or disabled.
1692 */
1693 int cpu_dirty_log_size;
1694 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu);
1695
1696 const struct kvm_x86_nested_ops *nested_ops;
1697
1698 void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
1699 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
1700
1701 int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq,
1702 uint32_t guest_irq, bool set);
1703 void (*pi_start_assignment)(struct kvm *kvm);
1704 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
1705 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
1706
1707 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
1708 bool *expired);
1709 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
1710
1711 void (*setup_mce)(struct kvm_vcpu *vcpu);
1712
1713 #ifdef CONFIG_KVM_SMM
1714 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
1715 int (*enter_smm)(struct kvm_vcpu *vcpu, union kvm_smram *smram);
1716 int (*leave_smm)(struct kvm_vcpu *vcpu, const union kvm_smram *smram);
1717 void (*enable_smi_window)(struct kvm_vcpu *vcpu);
1718 #endif
1719
1720 int (*mem_enc_ioctl)(struct kvm *kvm, void __user *argp);
1721 int (*mem_enc_register_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1722 int (*mem_enc_unregister_region)(struct kvm *kvm, struct kvm_enc_region *argp);
1723 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1724 int (*vm_move_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
1725 void (*guest_memory_reclaimed)(struct kvm *kvm);
1726
1727 int (*get_msr_feature)(struct kvm_msr_entry *entry);
1728
1729 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, int emul_type,
1730 void *insn, int insn_len);
1731
1732 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu);
1733 int (*enable_l2_tlb_flush)(struct kvm_vcpu *vcpu);
1734
1735 void (*migrate_timers)(struct kvm_vcpu *vcpu);
1736 void (*msr_filter_changed)(struct kvm_vcpu *vcpu);
1737 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
1738
1739 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
1740
1741 /*
1742 * Returns vCPU specific APICv inhibit reasons
1743 */
1744 unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu);
1745 };
1746
1747 struct kvm_x86_nested_ops {
1748 void (*leave_nested)(struct kvm_vcpu *vcpu);
1749 bool (*is_exception_vmexit)(struct kvm_vcpu *vcpu, u8 vector,
1750 u32 error_code);
1751 int (*check_events)(struct kvm_vcpu *vcpu);
1752 bool (*has_events)(struct kvm_vcpu *vcpu);
1753 void (*triple_fault)(struct kvm_vcpu *vcpu);
1754 int (*get_state)(struct kvm_vcpu *vcpu,
1755 struct kvm_nested_state __user *user_kvm_nested_state,
1756 unsigned user_data_size);
1757 int (*set_state)(struct kvm_vcpu *vcpu,
1758 struct kvm_nested_state __user *user_kvm_nested_state,
1759 struct kvm_nested_state *kvm_state);
1760 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu);
1761 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa);
1762
1763 int (*enable_evmcs)(struct kvm_vcpu *vcpu,
1764 uint16_t *vmcs_version);
1765 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu);
1766 void (*hv_inject_synthetic_vmexit_post_tlb_flush)(struct kvm_vcpu *vcpu);
1767 };
1768
1769 struct kvm_x86_init_ops {
1770 int (*hardware_setup)(void);
1771 unsigned int (*handle_intel_pt_intr)(void);
1772
1773 struct kvm_x86_ops *runtime_ops;
1774 struct kvm_pmu_ops *pmu_ops;
1775 };
1776
1777 struct kvm_arch_async_pf {
1778 u32 token;
1779 gfn_t gfn;
1780 unsigned long cr3;
1781 bool direct_map;
1782 };
1783
1784 extern u32 __read_mostly kvm_nr_uret_msrs;
1785 extern u64 __read_mostly host_efer;
1786 extern bool __read_mostly allow_smaller_maxphyaddr;
1787 extern bool __read_mostly enable_apicv;
1788 extern struct kvm_x86_ops kvm_x86_ops;
1789
1790 #define KVM_X86_OP(func) \
1791 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func));
1792 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
1793 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
1794 #include <asm/kvm-x86-ops.h>
1795
1796 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops);
1797 void kvm_x86_vendor_exit(void);
1798
1799 #define __KVM_HAVE_ARCH_VM_ALLOC
kvm_arch_alloc_vm(void)1800 static inline struct kvm *kvm_arch_alloc_vm(void)
1801 {
1802 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1803 }
1804
1805 #define __KVM_HAVE_ARCH_VM_FREE
1806 void kvm_arch_free_vm(struct kvm *kvm);
1807
1808 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB
kvm_arch_flush_remote_tlb(struct kvm * kvm)1809 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm)
1810 {
1811 if (kvm_x86_ops.tlb_remote_flush &&
1812 !static_call(kvm_x86_tlb_remote_flush)(kvm))
1813 return 0;
1814 else
1815 return -ENOTSUPP;
1816 }
1817
1818 #define kvm_arch_pmi_in_guest(vcpu) \
1819 ((vcpu) && (vcpu)->arch.handling_intr_from_guest)
1820
1821 void __init kvm_mmu_x86_module_init(void);
1822 int kvm_mmu_vendor_module_init(void);
1823 void kvm_mmu_vendor_module_exit(void);
1824
1825 void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
1826 int kvm_mmu_create(struct kvm_vcpu *vcpu);
1827 int kvm_mmu_init_vm(struct kvm *kvm);
1828 void kvm_mmu_uninit_vm(struct kvm *kvm);
1829
1830 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu);
1831 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1832 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
1833 const struct kvm_memory_slot *memslot,
1834 int start_level);
1835 void kvm_mmu_slot_try_split_huge_pages(struct kvm *kvm,
1836 const struct kvm_memory_slot *memslot,
1837 int target_level);
1838 void kvm_mmu_try_split_huge_pages(struct kvm *kvm,
1839 const struct kvm_memory_slot *memslot,
1840 u64 start, u64 end,
1841 int target_level);
1842 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
1843 const struct kvm_memory_slot *memslot);
1844 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
1845 const struct kvm_memory_slot *memslot);
1846 void kvm_mmu_zap_all(struct kvm *kvm);
1847 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
1848 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
1849
1850 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
1851
1852 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
1853 const void *val, int bytes);
1854
1855 struct kvm_irq_mask_notifier {
1856 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
1857 int irq;
1858 struct hlist_node link;
1859 };
1860
1861 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
1862 struct kvm_irq_mask_notifier *kimn);
1863 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
1864 struct kvm_irq_mask_notifier *kimn);
1865 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
1866 bool mask);
1867
1868 extern bool tdp_enabled;
1869
1870 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
1871
1872 /*
1873 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
1874 * userspace I/O) to indicate that the emulation context
1875 * should be reused as is, i.e. skip initialization of
1876 * emulation context, instruction fetch and decode.
1877 *
1878 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
1879 * Indicates that only select instructions (tagged with
1880 * EmulateOnUD) should be emulated (to minimize the emulator
1881 * attack surface). See also EMULTYPE_TRAP_UD_FORCED.
1882 *
1883 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
1884 * decode the instruction length. For use *only* by
1885 * kvm_x86_ops.skip_emulated_instruction() implementations if
1886 * EMULTYPE_COMPLETE_USER_EXIT is not set.
1887 *
1888 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
1889 * retry native execution under certain conditions,
1890 * Can only be set in conjunction with EMULTYPE_PF.
1891 *
1892 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
1893 * triggered by KVM's magic "force emulation" prefix,
1894 * which is opt in via module param (off by default).
1895 * Bypasses EmulateOnUD restriction despite emulating
1896 * due to an intercepted #UD (see EMULTYPE_TRAP_UD).
1897 * Used to test the full emulator from userspace.
1898 *
1899 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
1900 * backdoor emulation, which is opt in via module param.
1901 * VMware backdoor emulation handles select instructions
1902 * and reinjects the #GP for all other cases.
1903 *
1904 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which
1905 * case the CR2/GPA value pass on the stack is valid.
1906 *
1907 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility
1908 * state and inject single-step #DBs after skipping
1909 * an instruction (after completing userspace I/O).
1910 */
1911 #define EMULTYPE_NO_DECODE (1 << 0)
1912 #define EMULTYPE_TRAP_UD (1 << 1)
1913 #define EMULTYPE_SKIP (1 << 2)
1914 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
1915 #define EMULTYPE_TRAP_UD_FORCED (1 << 4)
1916 #define EMULTYPE_VMWARE_GP (1 << 5)
1917 #define EMULTYPE_PF (1 << 6)
1918 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7)
1919
1920 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
1921 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
1922 void *insn, int insn_len);
1923 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu,
1924 u64 *data, u8 ndata);
1925 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu);
1926
1927 void kvm_enable_efer_bits(u64);
1928 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
1929 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated);
1930 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data);
1931 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data);
1932 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu);
1933 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu);
1934 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
1935 int kvm_emulate_invd(struct kvm_vcpu *vcpu);
1936 int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
1937 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
1938 int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
1939
1940 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
1941 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
1942 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
1943 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu);
1944 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
1945 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
1946
1947 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
1948 void kvm_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
1949 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
1950 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
1951
1952 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
1953 int reason, bool has_error_code, u32 error_code);
1954
1955 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0);
1956 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4);
1957 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
1958 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
1959 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1960 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
1961 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
1962 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
1963 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
1964 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
1965 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
1966
1967 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1968 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
1969
1970 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
1971 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
1972 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
1973
1974 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1975 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1976 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
1977 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
1978 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
1979 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
1980 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
1981 struct x86_exception *fault);
1982 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
1983 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
1984
__kvm_irq_line_state(unsigned long * irq_state,int irq_source_id,int level)1985 static inline int __kvm_irq_line_state(unsigned long *irq_state,
1986 int irq_source_id, int level)
1987 {
1988 /* Logical OR for level trig interrupt */
1989 if (level)
1990 __set_bit(irq_source_id, irq_state);
1991 else
1992 __clear_bit(irq_source_id, irq_state);
1993
1994 return !!(*irq_state);
1995 }
1996
1997 #define KVM_MMU_ROOT_CURRENT BIT(0)
1998 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
1999 #define KVM_MMU_ROOTS_ALL (~0UL)
2000
2001 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
2002 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
2003
2004 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
2005
2006 void kvm_update_dr7(struct kvm_vcpu *vcpu);
2007
2008 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
2009 void kvm_mmu_free_roots(struct kvm *kvm, struct kvm_mmu *mmu,
2010 ulong roots_to_free);
2011 void kvm_mmu_free_guest_mode_roots(struct kvm *kvm, struct kvm_mmu *mmu);
2012 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
2013 struct x86_exception *exception);
2014 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
2015 struct x86_exception *exception);
2016 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
2017 struct x86_exception *exception);
2018
2019 bool kvm_apicv_activated(struct kvm *kvm);
2020 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu);
2021 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
2022 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
2023 enum kvm_apicv_inhibit reason, bool set);
2024 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
2025 enum kvm_apicv_inhibit reason, bool set);
2026
kvm_set_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)2027 static inline void kvm_set_apicv_inhibit(struct kvm *kvm,
2028 enum kvm_apicv_inhibit reason)
2029 {
2030 kvm_set_or_clear_apicv_inhibit(kvm, reason, true);
2031 }
2032
kvm_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)2033 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm,
2034 enum kvm_apicv_inhibit reason)
2035 {
2036 kvm_set_or_clear_apicv_inhibit(kvm, reason, false);
2037 }
2038
2039 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
2040
2041 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
2042 void *insn, int insn_len);
2043 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
2044 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
2045 gva_t gva, hpa_t root_hpa);
2046 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
2047 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd);
2048
2049 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
2050 int tdp_max_root_level, int tdp_huge_page_level);
2051
kvm_read_ldt(void)2052 static inline u16 kvm_read_ldt(void)
2053 {
2054 u16 ldt;
2055 asm("sldt %0" : "=g"(ldt));
2056 return ldt;
2057 }
2058
kvm_load_ldt(u16 sel)2059 static inline void kvm_load_ldt(u16 sel)
2060 {
2061 asm("lldt %0" : : "rm"(sel));
2062 }
2063
2064 #ifdef CONFIG_X86_64
read_msr(unsigned long msr)2065 static inline unsigned long read_msr(unsigned long msr)
2066 {
2067 u64 value;
2068
2069 rdmsrl(msr, value);
2070 return value;
2071 }
2072 #endif
2073
kvm_inject_gp(struct kvm_vcpu * vcpu,u32 error_code)2074 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
2075 {
2076 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2077 }
2078
2079 #define TSS_IOPB_BASE_OFFSET 0x66
2080 #define TSS_BASE_SIZE 0x68
2081 #define TSS_IOPB_SIZE (65536 / 8)
2082 #define TSS_REDIRECTION_SIZE (256 / 8)
2083 #define RMODE_TSS_SIZE \
2084 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
2085
2086 enum {
2087 TASK_SWITCH_CALL = 0,
2088 TASK_SWITCH_IRET = 1,
2089 TASK_SWITCH_JMP = 2,
2090 TASK_SWITCH_GATE = 3,
2091 };
2092
2093 #define HF_GUEST_MASK (1 << 0) /* VCPU is in guest-mode */
2094
2095 #ifdef CONFIG_KVM_SMM
2096 #define HF_SMM_MASK (1 << 1)
2097 #define HF_SMM_INSIDE_NMI_MASK (1 << 2)
2098
2099 # define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE
2100 # define KVM_ADDRESS_SPACE_NUM 2
2101 # define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
2102 # define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
2103 #else
2104 # define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, 0)
2105 #endif
2106
2107 #define KVM_ARCH_WANT_MMU_NOTIFIER
2108
2109 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
2110 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
2111 int kvm_cpu_has_extint(struct kvm_vcpu *v);
2112 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
2113 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
2114 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
2115
2116 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
2117 unsigned long ipi_bitmap_high, u32 min,
2118 unsigned long icr, int op_64_bit);
2119
2120 int kvm_add_user_return_msr(u32 msr);
2121 int kvm_find_user_return_msr(u32 msr);
2122 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
2123
kvm_is_supported_user_return_msr(u32 msr)2124 static inline bool kvm_is_supported_user_return_msr(u32 msr)
2125 {
2126 return kvm_find_user_return_msr(msr) >= 0;
2127 }
2128
2129 u64 kvm_scale_tsc(u64 tsc, u64 ratio);
2130 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
2131 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
2132 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
2133
2134 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
2135 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
2136
2137 void kvm_make_scan_ioapic_request(struct kvm *kvm);
2138 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
2139 unsigned long *vcpu_bitmap);
2140
2141 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
2142 struct kvm_async_pf *work);
2143 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
2144 struct kvm_async_pf *work);
2145 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
2146 struct kvm_async_pf *work);
2147 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu);
2148 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu);
2149 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
2150
2151 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
2152 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
2153 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
2154
2155 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
2156 u32 size);
2157 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
2158 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
2159
2160 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
2161 struct kvm_vcpu **dest_vcpu);
2162
2163 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
2164 struct kvm_lapic_irq *irq);
2165
kvm_irq_is_postable(struct kvm_lapic_irq * irq)2166 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq)
2167 {
2168 /* We can only post Fixed and LowPrio IRQs */
2169 return (irq->delivery_mode == APIC_DM_FIXED ||
2170 irq->delivery_mode == APIC_DM_LOWEST);
2171 }
2172
kvm_arch_vcpu_blocking(struct kvm_vcpu * vcpu)2173 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
2174 {
2175 static_call_cond(kvm_x86_vcpu_blocking)(vcpu);
2176 }
2177
kvm_arch_vcpu_unblocking(struct kvm_vcpu * vcpu)2178 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
2179 {
2180 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu);
2181 }
2182
kvm_cpu_get_apicid(int mps_cpu)2183 static inline int kvm_cpu_get_apicid(int mps_cpu)
2184 {
2185 #ifdef CONFIG_X86_LOCAL_APIC
2186 return default_cpu_present_to_apicid(mps_cpu);
2187 #else
2188 WARN_ON_ONCE(1);
2189 return BAD_APICID;
2190 #endif
2191 }
2192
2193 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages);
2194
2195 #define KVM_CLOCK_VALID_FLAGS \
2196 (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC)
2197
2198 #define KVM_X86_VALID_QUIRKS \
2199 (KVM_X86_QUIRK_LINT0_REENABLED | \
2200 KVM_X86_QUIRK_CD_NW_CLEARED | \
2201 KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \
2202 KVM_X86_QUIRK_OUT_7E_INC_RIP | \
2203 KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \
2204 KVM_X86_QUIRK_FIX_HYPERCALL_INSN | \
2205 KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS)
2206
2207 #endif /* _ASM_X86_KVM_HOST_H */
2208