1 /*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <plat/common/platform.h>
9 #include <lib/pm/mtk_pm.h>
10
11 #define MTK_PM_ST_SMP_READY BIT(0)
12 #define MTK_PM_ST_PWR_READY BIT(1)
13 #define MTK_PM_ST_RESET_READY BIT(2)
14
15 static uintptr_t mtk_secure_entrypoint;
16 static plat_init_func mtk_plat_smp_init;
17 static plat_psci_ops_t mtk_pm_ops;
18 static unsigned int mtk_pm_status;
19
plat_pm_get_warm_entry(void)20 uintptr_t plat_pm_get_warm_entry(void)
21 {
22 return mtk_secure_entrypoint;
23 }
24
plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl * ops)25 int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops)
26 {
27 if (!ops) {
28 return MTK_CPUPM_E_FAIL;
29 }
30
31 #if CONFIG_MTK_CPU_SUSPEND_EN
32 if (!mtk_pm_ops.pwr_domain_suspend) {
33 mtk_pm_ops.pwr_domain_suspend = ops->pwr_domain_suspend;
34 }
35
36 if (!mtk_pm_ops.pwr_domain_suspend_finish) {
37 mtk_pm_ops.pwr_domain_suspend_finish = ops->pwr_domain_suspend_finish;
38 }
39
40 if (!mtk_pm_ops.validate_power_state) {
41 mtk_pm_ops.validate_power_state = ops->validate_power_state;
42 }
43
44 if (!mtk_pm_ops.get_sys_suspend_power_state) {
45 mtk_pm_ops.get_sys_suspend_power_state = ops->get_sys_suspend_power_state;
46 }
47
48 mtk_pm_status |= MTK_PM_ST_PWR_READY;
49 #endif
50 return MTK_CPUPM_E_OK;
51 }
52
plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl * ops)53 int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops)
54 {
55 if (!ops) {
56 return MTK_CPUPM_E_FAIL;
57 }
58
59 #if CONFIG_MTK_SMP_EN
60 if (!mtk_pm_ops.pwr_domain_on) {
61 mtk_pm_ops.pwr_domain_on = ops->pwr_domain_on;
62 }
63
64 if (!mtk_pm_ops.pwr_domain_on_finish) {
65 mtk_pm_ops.pwr_domain_on_finish = ops->pwr_domain_on_finish;
66 }
67
68 if (!mtk_pm_ops.pwr_domain_off) {
69 mtk_pm_ops.pwr_domain_off = ops->pwr_domain_off;
70 }
71
72 if (!mtk_plat_smp_init) {
73 mtk_plat_smp_init = ops->init;
74 }
75
76 mtk_pm_status |= MTK_PM_ST_SMP_READY;
77 #endif
78 return MTK_CPUPM_E_OK;
79 }
80
plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl * ops)81 int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops)
82 {
83 if (!ops) {
84 return MTK_CPUPM_E_FAIL;
85 }
86
87 if (!mtk_pm_ops.system_off) {
88 mtk_pm_ops.system_off = ops->system_off;
89 }
90
91 if (!mtk_pm_ops.system_reset) {
92 mtk_pm_ops.system_reset = ops->system_reset;
93 }
94
95 if (!mtk_pm_ops.system_reset2) {
96 mtk_pm_ops.system_reset2 = ops->system_reset2;
97 }
98
99 mtk_pm_status |= MTK_PM_ST_RESET_READY;
100
101 return MTK_CPUPM_E_OK;
102 }
103
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)104 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
105 const plat_psci_ops_t **psci_ops)
106 {
107 *psci_ops = &mtk_pm_ops;
108 mtk_secure_entrypoint = sec_entrypoint;
109
110 if (mtk_plat_smp_init) {
111 unsigned int cpu_id = plat_my_core_pos();
112
113 mtk_plat_smp_init(cpu_id, mtk_secure_entrypoint);
114 }
115 INFO("%s, smp:(%d), pwr_ctrl:(%d), system_reset:(%d)\n", __func__,
116 !!(mtk_pm_status & MTK_PM_ST_SMP_READY),
117 !!(mtk_pm_status & MTK_PM_ST_PWR_READY),
118 !!(mtk_pm_status & MTK_PM_ST_RESET_READY));
119 return 0;
120 }
121