1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4  * Copyright (c) 2013 Linaro Ltd.
5  *
6  * Common Clock Framework support for all PLL's in Samsung platforms
7 */
8 
9 #ifndef __SAMSUNG_CLK_PLL_H
10 #define __SAMSUNG_CLK_PLL_H
11 
12 enum samsung_pll_type {
13 	pll_2126,
14 	pll_3000,
15 	pll_35xx,
16 	pll_36xx,
17 	pll_2550,
18 	pll_2650,
19 	pll_4500,
20 	pll_4502,
21 	pll_4508,
22 	pll_4600,
23 	pll_4650,
24 	pll_4650c,
25 	pll_6552,
26 	pll_6552_s3c2416,
27 	pll_6553,
28 	pll_2550x,
29 	pll_2550xx,
30 	pll_2650x,
31 	pll_2650xx,
32 	pll_1417x,
33 	pll_1450x,
34 	pll_1451x,
35 	pll_1452x,
36 	pll_1460x,
37 	pll_0822x,
38 	pll_0831x,
39 	pll_142xx,
40 };
41 
42 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
43 	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
44 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
45 	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
46 
47 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
48 	{							\
49 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
50 				_m, _p, _s, 0, 16),		\
51 		.mdiv	=	(_m),				\
52 		.pdiv	=	(_p),				\
53 		.sdiv	=	(_s),				\
54 	}
55 
56 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
57 	{							\
58 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
59 				_m, _p, _s, _k, 16),		\
60 		.mdiv	=	(_m),				\
61 		.pdiv	=	(_p),				\
62 		.sdiv	=	(_s),				\
63 		.kdiv	=	(_k),				\
64 	}
65 
66 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
67 	{							\
68 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
69 				_m, _p, _s - 1, 0, 16),		\
70 		.mdiv	=	(_m),				\
71 		.pdiv	=	(_p),				\
72 		.sdiv	=	(_s),				\
73 		.afc	=	(_afc),				\
74 	}
75 
76 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
77 	{							\
78 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
79 				_m, _p, _s, _k, 16),		\
80 		.mdiv	=	(_m),				\
81 		.pdiv	=	(_p),				\
82 		.sdiv	=	(_s),				\
83 		.kdiv	=	(_k),				\
84 		.vsel	=	(_vsel),			\
85 	}
86 
87 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
88 	{							\
89 		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
90 				_m, _p, _s, _k, 10),		\
91 		.mdiv	=	(_m),				\
92 		.pdiv	=	(_p),				\
93 		.sdiv	=	(_s),				\
94 		.kdiv	=	(_k),				\
95 		.mfr	=	(_mfr),				\
96 		.mrr	=	(_mrr),				\
97 		.vsel	=	(_vsel),			\
98 	}
99 
100 /* NOTE: Rate table should be kept sorted in descending order. */
101 
102 struct samsung_pll_rate_table {
103 	unsigned int rate;
104 	unsigned int pdiv;
105 	unsigned int mdiv;
106 	unsigned int sdiv;
107 	unsigned int kdiv;
108 	unsigned int afc;
109 	unsigned int mfr;
110 	unsigned int mrr;
111 	unsigned int vsel;
112 };
113 
114 #endif /* __SAMSUNG_CLK_PLL_H */
115