1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/ethtool.h>
40 #include <linux/list.h>
41 #include <linux/mutex.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/net_tstamp.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
47 #endif
48 #include <linux/cpu_rmap.h>
49 #include <linux/ptp_clock_kernel.h>
50 #include <linux/irq.h>
51 #include <net/xdp.h>
52
53 #include <linux/mlx4/device.h>
54 #include <linux/mlx4/qp.h>
55 #include <linux/mlx4/cq.h>
56 #include <linux/mlx4/srq.h>
57 #include <linux/mlx4/doorbell.h>
58 #include <linux/mlx4/cmd.h>
59
60 #include "en_port.h"
61 #include "mlx4_stats.h"
62
63 #define DRV_NAME "mlx4_en"
64 #define DRV_VERSION "4.0-0"
65
66 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
67
68 /*
69 * Device constants
70 */
71
72
73 #define MLX4_EN_PAGE_SHIFT 12
74 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
75 #define DEF_RX_RINGS 16
76 #define MAX_RX_RINGS 128
77 #define MIN_RX_RINGS 1
78 #define LOG_TXBB_SIZE 6
79 #define TXBB_SIZE BIT(LOG_TXBB_SIZE)
80 #define HEADROOM (2048 / TXBB_SIZE + 1)
81 #define STAMP_STRIDE 64
82 #define STAMP_DWORDS (STAMP_STRIDE / 4)
83 #define STAMP_SHIFT 31
84 #define STAMP_VAL 0x7fffffff
85 #define STATS_DELAY (HZ / 4)
86 #define SERVICE_TASK_DELAY (HZ / 4)
87 #define MAX_NUM_OF_FS_RULES 256
88
89 #define MLX4_EN_FILTER_HASH_SHIFT 4
90 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
91
92 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
93 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
94
95 /* Maximal size of the bounce buffer:
96 * 256 bytes for LSO headers.
97 * CTRL_SIZE for control desc.
98 * DS_SIZE if skb->head contains some payload.
99 * MAX_SKB_FRAGS frags.
100 */
101 #define MLX4_TX_BOUNCE_BUFFER_SIZE \
102 ALIGN(256 + CTRL_SIZE + DS_SIZE + MAX_SKB_FRAGS * DS_SIZE, TXBB_SIZE)
103
104 #define MLX4_MAX_DESC_TXBBS (MLX4_TX_BOUNCE_BUFFER_SIZE / TXBB_SIZE)
105
106 /*
107 * OS related constants and tunables
108 */
109
110 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
111 #define MLX4_EN_PRIV_FLAGS_PHV 2
112
113 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
114
115 /* Use the maximum between 16384 and a single page */
116 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
117
118 #define MLX4_EN_MAX_RX_FRAGS 4
119
120 /* Maximum ring sizes */
121 #define MLX4_EN_MAX_TX_SIZE 8192
122 #define MLX4_EN_MAX_RX_SIZE 8192
123
124 /* Minimum ring size for our page-allocation scheme to work */
125 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
126 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
127
128 #define MLX4_EN_SMALL_PKT_SIZE 64
129 #define MLX4_EN_MIN_TX_RING_P_UP 1
130 #define MLX4_EN_MAX_TX_RING_P_UP 32
131 #define MLX4_EN_NUM_UP_LOW 1
132 #define MLX4_EN_NUM_UP_HIGH 8
133 #define MLX4_EN_DEF_RX_RING_SIZE 1024
134 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
135 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
136 MLX4_EN_NUM_UP_HIGH)
137
138 #define MLX4_EN_DEFAULT_TX_WORK 256
139
140 /* Target number of packets to coalesce with interrupt moderation */
141 #define MLX4_EN_RX_COAL_TARGET 44
142 #define MLX4_EN_RX_COAL_TIME 0x10
143
144 #define MLX4_EN_TX_COAL_PKTS 16
145 #define MLX4_EN_TX_COAL_TIME 0x10
146
147 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
148 #define MLX4_EN_MAX_COAL_TIME U16_MAX
149
150 #define MLX4_EN_RX_RATE_LOW 400000
151 #define MLX4_EN_RX_COAL_TIME_LOW 0
152 #define MLX4_EN_RX_RATE_HIGH 450000
153 #define MLX4_EN_RX_COAL_TIME_HIGH 128
154 #define MLX4_EN_RX_SIZE_THRESH 1024
155 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
156 #define MLX4_EN_SAMPLE_INTERVAL 0
157 #define MLX4_EN_AVG_PKT_SMALL 256
158
159 #define MLX4_EN_AUTO_CONF 0xffff
160
161 #define MLX4_EN_DEF_RX_PAUSE 1
162 #define MLX4_EN_DEF_TX_PAUSE 1
163
164 /* Interval between successive polls in the Tx routine when polling is used
165 instead of interrupts (in per-core Tx rings) - should be power of 2 */
166 #define MLX4_EN_TX_POLL_MODER 16
167 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
168
169 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
170 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
171 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
172 #define PREAMBLE_LEN 8
173 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
174 ETH_HLEN + PREAMBLE_LEN)
175
176 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
177 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
178 */
179 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
180 #define ETH_BCAST 0xffffffffffffULL
181
182 #define MLX4_EN_LOOPBACK_RETRIES 5
183 #define MLX4_EN_LOOPBACK_TIMEOUT 100
184
185 /* Constants for TX flow */
186 enum {
187 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
188 MAX_BF = 256,
189 MIN_PKT_LEN = 17,
190 };
191
192 /*
193 * Configurables
194 */
195
196 enum cq_type {
197 /* keep tx types first */
198 TX,
199 TX_XDP,
200 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
201 RX,
202 };
203
204
205 /*
206 * Useful macros
207 */
208 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
209 #define XNOR(x, y) (!(x) == !(y))
210
211
212 struct mlx4_en_tx_info {
213 union {
214 struct sk_buff *skb;
215 struct page *page;
216 };
217 dma_addr_t map0_dma;
218 u32 map0_byte_count;
219 u32 nr_txbb;
220 u32 nr_bytes;
221 u8 linear;
222 u8 data_offset;
223 u8 inl;
224 u8 ts_requested;
225 u8 nr_maps;
226 } ____cacheline_aligned_in_smp;
227
228
229 #define MLX4_EN_BIT_DESC_OWN 0x80000000
230 #define MLX4_EN_MEMTYPE_PAD 0x100
231
232
233 struct mlx4_en_tx_desc {
234 struct mlx4_wqe_ctrl_seg ctrl;
235 union {
236 struct mlx4_wqe_data_seg data; /* at least one data segment */
237 struct mlx4_wqe_lso_seg lso;
238 struct mlx4_wqe_inline_seg inl;
239 };
240 };
241
242 #define MLX4_EN_USE_SRQ 0x01000000
243
244 #define MLX4_EN_CX3_LOW_ID 0x1000
245 #define MLX4_EN_CX3_HIGH_ID 0x1005
246
247 struct mlx4_en_rx_alloc {
248 struct page *page;
249 dma_addr_t dma;
250 u32 page_offset;
251 };
252
253 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
254
255 struct mlx4_en_page_cache {
256 u32 index;
257 struct {
258 struct page *page;
259 dma_addr_t dma;
260 } buf[MLX4_EN_CACHE_SIZE];
261 };
262
263 enum {
264 MLX4_EN_TX_RING_STATE_RECOVERING,
265 };
266
267 struct mlx4_en_priv;
268
269 struct mlx4_en_tx_ring {
270 /* cache line used and dirtied in tx completion
271 * (mlx4_en_free_tx_buf())
272 */
273 u32 last_nr_txbb;
274 u32 cons;
275 unsigned long wake_queue;
276 struct netdev_queue *tx_queue;
277 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
278 struct mlx4_en_tx_ring *ring,
279 int index,
280 u64 timestamp, int napi_mode);
281 struct mlx4_en_rx_ring *recycle_ring;
282
283 /* cache line used and dirtied in mlx4_en_xmit() */
284 u32 prod ____cacheline_aligned_in_smp;
285 unsigned int tx_dropped;
286 unsigned long bytes;
287 unsigned long packets;
288 unsigned long tx_csum;
289 unsigned long tso_packets;
290 unsigned long xmit_more;
291 struct mlx4_bf bf;
292
293 /* Following part should be mostly read */
294 void __iomem *doorbell_address;
295 __be32 doorbell_qpn;
296 __be32 mr_key;
297 u32 size; /* number of TXBBs */
298 u32 size_mask;
299 u32 full_size;
300 u32 buf_size;
301 void *buf;
302 struct mlx4_en_tx_info *tx_info;
303 int qpn;
304 u8 queue_index;
305 bool bf_enabled;
306 bool bf_alloced;
307 u8 hwtstamp_tx_type;
308 u8 *bounce_buf;
309
310 /* Not used in fast path
311 * Only queue_stopped might be used if BQL is not properly working.
312 */
313 unsigned long queue_stopped;
314 unsigned long state;
315 struct mlx4_hwq_resources sp_wqres;
316 struct mlx4_qp sp_qp;
317 struct mlx4_qp_context sp_context;
318 cpumask_t sp_affinity_mask;
319 enum mlx4_qp_state sp_qp_state;
320 u16 sp_stride;
321 u16 sp_cqn; /* index of port CQ associated with this ring */
322 } ____cacheline_aligned_in_smp;
323
324 struct mlx4_en_rx_desc {
325 /* actual number of entries depends on rx ring stride */
326 struct mlx4_wqe_data_seg data[0];
327 };
328
329 struct mlx4_en_rx_ring {
330 struct mlx4_hwq_resources wqres;
331 u32 size ; /* number of Rx descs*/
332 u32 actual_size;
333 u32 size_mask;
334 u16 stride;
335 u16 log_stride;
336 u16 cqn; /* index of port CQ associated with this ring */
337 u32 prod;
338 u32 cons;
339 u32 buf_size;
340 u8 fcs_del;
341 void *buf;
342 void *rx_info;
343 struct bpf_prog __rcu *xdp_prog;
344 struct mlx4_en_page_cache page_cache;
345 unsigned long bytes;
346 unsigned long packets;
347 unsigned long csum_ok;
348 unsigned long csum_none;
349 unsigned long csum_complete;
350 unsigned long rx_alloc_pages;
351 unsigned long xdp_drop;
352 unsigned long xdp_redirect;
353 unsigned long xdp_redirect_fail;
354 unsigned long xdp_tx;
355 unsigned long xdp_tx_full;
356 unsigned long dropped;
357 int hwtstamp_rx_filter;
358 cpumask_var_t affinity_mask;
359 struct xdp_rxq_info xdp_rxq;
360 };
361
362 struct mlx4_en_cq {
363 struct mlx4_cq mcq;
364 struct mlx4_hwq_resources wqres;
365 int ring;
366 struct net_device *dev;
367 union {
368 struct napi_struct napi;
369 bool xdp_busy;
370 };
371 int size;
372 int buf_size;
373 int vector;
374 enum cq_type type;
375 u16 moder_time;
376 u16 moder_cnt;
377 struct mlx4_cqe *buf;
378 #define MLX4_EN_OPCODE_ERROR 0x1e
379
380 const struct cpumask *aff_mask;
381 };
382
383 struct mlx4_en_port_profile {
384 u32 flags;
385 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
386 u32 rx_ring_num;
387 u32 tx_ring_size;
388 u32 rx_ring_size;
389 u8 num_tx_rings_p_up;
390 u8 rx_pause;
391 u8 rx_ppp;
392 u8 tx_pause;
393 u8 tx_ppp;
394 u8 num_up;
395 int rss_rings;
396 int inline_thold;
397 struct hwtstamp_config hwtstamp_config;
398 };
399
400 struct mlx4_en_profile {
401 int udp_rss;
402 u8 rss_mask;
403 u32 active_ports;
404 u32 small_pkt_int;
405 u8 no_reset;
406 u8 max_num_tx_rings_p_up;
407 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
408 };
409
410 struct mlx4_en_dev {
411 struct mlx4_dev *dev;
412 struct pci_dev *pdev;
413 struct mutex state_lock;
414 struct net_device *pndev[MLX4_MAX_PORTS + 1];
415 struct net_device *upper[MLX4_MAX_PORTS + 1];
416 u32 port_cnt;
417 bool device_up;
418 struct mlx4_en_profile profile;
419 u32 LSO_support;
420 struct workqueue_struct *workqueue;
421 struct device *dma_device;
422 void __iomem *uar_map;
423 struct mlx4_uar priv_uar;
424 struct mlx4_mr mr;
425 u32 priv_pdn;
426 spinlock_t uar_lock;
427 u8 mac_removed[MLX4_MAX_PORTS + 1];
428 u32 nominal_c_mult;
429 struct cyclecounter cycles;
430 seqlock_t clock_lock;
431 struct timecounter clock;
432 unsigned long last_overflow_check;
433 struct ptp_clock *ptp_clock;
434 struct ptp_clock_info ptp_clock_info;
435 struct notifier_block nb;
436 };
437
438
439 struct mlx4_en_rss_map {
440 int base_qpn;
441 struct mlx4_qp qps[MAX_RX_RINGS];
442 enum mlx4_qp_state state[MAX_RX_RINGS];
443 struct mlx4_qp *indir_qp;
444 enum mlx4_qp_state indir_state;
445 };
446
447 enum mlx4_en_port_flag {
448 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
449 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
450 };
451
452 struct mlx4_en_port_state {
453 int link_state;
454 int link_speed;
455 int transceiver;
456 u32 flags;
457 };
458
459 enum mlx4_en_mclist_act {
460 MCLIST_NONE,
461 MCLIST_REM,
462 MCLIST_ADD,
463 };
464
465 struct mlx4_en_mc_list {
466 struct list_head list;
467 enum mlx4_en_mclist_act action;
468 u8 addr[ETH_ALEN];
469 u64 reg_id;
470 u64 tunnel_reg_id;
471 };
472
473 struct mlx4_en_frag_info {
474 u16 frag_size;
475 u32 frag_stride;
476 };
477
478 #ifdef CONFIG_MLX4_EN_DCB
479 /* Minimal TC BW - setting to 0 will block traffic */
480 #define MLX4_EN_BW_MIN 1
481 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
482
483 #define MLX4_EN_TC_VENDOR 0
484 #define MLX4_EN_TC_ETS 7
485
486 enum dcb_pfc_type {
487 pfc_disabled = 0,
488 pfc_enabled_full,
489 pfc_enabled_tx,
490 pfc_enabled_rx
491 };
492
493 struct mlx4_en_cee_config {
494 bool pfc_state;
495 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
496 };
497 #endif
498
499 struct ethtool_flow_id {
500 struct list_head list;
501 struct ethtool_rx_flow_spec flow_spec;
502 u64 id;
503 };
504
505 enum {
506 MLX4_EN_FLAG_PROMISC = (1 << 0),
507 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
508 /* whether we need to enable hardware loopback by putting dmac
509 * in Tx WQE
510 */
511 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
512 /* whether we need to drop packets that hardware loopback-ed */
513 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
514 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
515 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
516 #ifdef CONFIG_MLX4_EN_DCB
517 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
518 #endif
519 };
520
521 #define PORT_BEACON_MAX_LIMIT (65535)
522 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
523 #define MLX4_EN_MAC_HASH_IDX 5
524
525 struct mlx4_en_stats_bitmap {
526 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
527 struct mutex mutex; /* for mutual access to stats bitmap */
528 };
529
530 enum {
531 MLX4_EN_STATE_FLAG_RESTARTING,
532 };
533
534 struct mlx4_en_priv {
535 struct mlx4_en_dev *mdev;
536 struct mlx4_en_port_profile *prof;
537 struct net_device *dev;
538 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
539 struct mlx4_en_port_state port_state;
540 spinlock_t stats_lock;
541 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
542 /* To allow rules removal while port is going down */
543 struct list_head ethtool_list;
544
545 unsigned long last_moder_packets[MAX_RX_RINGS];
546 unsigned long last_moder_tx_packets;
547 unsigned long last_moder_bytes[MAX_RX_RINGS];
548 unsigned long last_moder_jiffies;
549 int last_moder_time[MAX_RX_RINGS];
550 u16 rx_usecs;
551 u16 rx_frames;
552 u16 tx_usecs;
553 u16 tx_frames;
554 u32 pkt_rate_low;
555 u16 rx_usecs_low;
556 u32 pkt_rate_high;
557 u16 rx_usecs_high;
558 u32 sample_interval;
559 u32 adaptive_rx_coal;
560 u32 msg_enable;
561 u32 loopback_ok;
562 u32 validate_loopback;
563
564 struct mlx4_hwq_resources res;
565 int link_state;
566 bool port_up;
567 int port;
568 int registered;
569 int allocated;
570 int stride;
571 unsigned char current_mac[ETH_ALEN + 2];
572 int mac_index;
573 unsigned max_mtu;
574 int base_qpn;
575 int cqe_factor;
576 int cqe_size;
577
578 struct mlx4_en_rss_map rss_map;
579 __be32 ctrl_flags;
580 u32 flags;
581 u8 num_tx_rings_p_up;
582 u32 tx_work_limit;
583 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
584 u32 rx_ring_num;
585 u32 rx_skb_size;
586 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
587 u8 num_frags;
588 u8 log_rx_info;
589 u8 dma_dir;
590 u16 rx_headroom;
591
592 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
593 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
594 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
595 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
596 struct mlx4_qp drop_qp;
597 struct work_struct rx_mode_task;
598 struct work_struct restart_task;
599 struct work_struct linkstate_task;
600 struct delayed_work stats_task;
601 struct delayed_work service_task;
602 struct mlx4_en_pkt_stats pkstats;
603 struct mlx4_en_counter_stats pf_stats;
604 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
605 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
606 struct mlx4_en_flow_stats_rx rx_flowstats;
607 struct mlx4_en_flow_stats_tx tx_flowstats;
608 struct mlx4_en_port_stats port_stats;
609 struct mlx4_en_xdp_stats xdp_stats;
610 struct mlx4_en_phy_stats phy_stats;
611 struct mlx4_en_stats_bitmap stats_bitmap;
612 struct list_head mc_list;
613 struct list_head curr_list;
614 u64 broadcast_id;
615 struct mlx4_en_stat_out_mbox hw_stats;
616 int vids[128];
617 bool wol;
618 struct device *ddev;
619 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
620 struct hwtstamp_config hwtstamp_config;
621 u32 counter_index;
622
623 #ifdef CONFIG_MLX4_EN_DCB
624 #define MLX4_EN_DCB_ENABLED 0x3
625 struct ieee_ets ets;
626 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
627 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
628 struct mlx4_en_cee_config cee_config;
629 u8 dcbx_cap;
630 #endif
631 #ifdef CONFIG_RFS_ACCEL
632 spinlock_t filters_lock;
633 int last_filter_id;
634 struct list_head filters;
635 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
636 #endif
637 u64 tunnel_reg_id;
638 __be16 vxlan_port;
639
640 u32 pflags;
641 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
642 u8 rss_hash_fn;
643 unsigned long state;
644 };
645
646 enum mlx4_en_wol {
647 MLX4_EN_WOL_MAGIC = (1ULL << 61),
648 MLX4_EN_WOL_ENABLED = (1ULL << 62),
649 };
650
651 struct mlx4_mac_entry {
652 struct hlist_node hlist;
653 unsigned char mac[ETH_ALEN + 2];
654 u64 reg_id;
655 struct rcu_head rcu;
656 };
657
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)658 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
659 {
660 return buf + idx * cqe_sz;
661 }
662
663 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
664
665 void mlx4_en_init_ptys2ethtool_map(void);
666 void mlx4_en_update_loopback_state(struct net_device *dev,
667 netdev_features_t features);
668
669 void mlx4_en_destroy_netdev(struct net_device *dev);
670 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
671 struct mlx4_en_port_profile *prof);
672
673 int mlx4_en_start_port(struct net_device *dev);
674 void mlx4_en_stop_port(struct net_device *dev, int detach);
675
676 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
677 struct mlx4_en_stats_bitmap *stats_bitmap,
678 u8 rx_ppp, u8 rx_pause,
679 u8 tx_ppp, u8 tx_pause);
680
681 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
682 struct mlx4_en_priv *tmp,
683 struct mlx4_en_port_profile *prof,
684 bool carry_xdp_prog);
685 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
686 struct mlx4_en_priv *tmp);
687
688 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
689 int entries, int ring, enum cq_type mode, int node);
690 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
691 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
692 int cq_idx);
693 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
694 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
695 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
696
697 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
698 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
699 struct net_device *sb_dev);
700 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
701 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
702 struct mlx4_en_rx_alloc *frame,
703 struct mlx4_en_priv *priv, unsigned int length,
704 int tx_ind, bool *doorbell_pending);
705 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
706 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
707 struct mlx4_en_rx_alloc *frame);
708
709 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
710 struct mlx4_en_tx_ring **pring,
711 u32 size, u16 stride,
712 int node, int queue_index);
713 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
714 struct mlx4_en_tx_ring **pring);
715 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
716 struct mlx4_en_tx_ring *ring);
717 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
718 struct mlx4_en_tx_ring *ring,
719 int cq, int user_prio);
720 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
721 struct mlx4_en_tx_ring *ring);
722 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
723 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
724 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
725 struct mlx4_en_rx_ring **pring,
726 u32 size, u16 stride, int node, int queue_index);
727 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
728 struct mlx4_en_rx_ring **pring,
729 u32 size, u16 stride);
730 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
731 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
732 struct mlx4_en_rx_ring *ring);
733 int mlx4_en_process_rx_cq(struct net_device *dev,
734 struct mlx4_en_cq *cq,
735 int budget);
736 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
737 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
738 int mlx4_en_process_tx_cq(struct net_device *dev,
739 struct mlx4_en_cq *cq, int napi_budget);
740 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
741 struct mlx4_en_tx_ring *ring,
742 int index, u64 timestamp,
743 int napi_mode);
744 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
745 struct mlx4_en_tx_ring *ring,
746 int index, u64 timestamp,
747 int napi_mode);
748 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
749 int is_tx, int rss, int qpn, int cqn, int user_prio,
750 struct mlx4_qp_context *context);
751 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
752 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
753 int loopback);
754 void mlx4_en_calc_rx_buf(struct net_device *dev);
755 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
756 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
757 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
758 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
759 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
760 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
761
762 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
763 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
764
765 void mlx4_en_fold_software_stats(struct net_device *dev);
766 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
767 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
768
769 #ifdef CONFIG_MLX4_EN_DCB
770 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
771 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
772 #endif
773
774 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
775 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
776
777 #ifdef CONFIG_RFS_ACCEL
778 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
779 #endif
780
781 #define MLX4_EN_NUM_SELF_TEST 5
782 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
783 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
784
785 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
786 ((dev->features & feature) ^ (new_features & feature))
787
788 int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
789 int mlx4_en_reset_config(struct net_device *dev,
790 struct hwtstamp_config ts_config,
791 netdev_features_t new_features);
792 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
793 struct mlx4_en_stats_bitmap *stats_bitmap,
794 u8 rx_ppp, u8 rx_pause,
795 u8 tx_ppp, u8 tx_pause);
796 int mlx4_en_netdev_event(struct notifier_block *this,
797 unsigned long event, void *ptr);
798
799 struct xdp_md;
800 int mlx4_en_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp);
801 int mlx4_en_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash);
802
803 /*
804 * Functions for time stamping
805 */
806 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
807 u64 mlx4_en_get_hwtstamp(struct mlx4_en_dev *mdev, u64 timestamp);
808 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
809 struct skb_shared_hwtstamps *hwts,
810 u64 timestamp);
811 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
812 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
813
814 /* Globals
815 */
816 extern const struct ethtool_ops mlx4_en_ethtool_ops;
817
818
819
820 /*
821 * printk / logging functions
822 */
823
824 __printf(3, 4)
825 void en_print(const char *level, const struct mlx4_en_priv *priv,
826 const char *format, ...);
827
828 #define en_dbg(mlevel, priv, format, ...) \
829 do { \
830 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
831 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
832 } while (0)
833 #define en_warn(priv, format, ...) \
834 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
835 #define en_err(priv, format, ...) \
836 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
837 #define en_info(priv, format, ...) \
838 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
839
840 #define mlx4_err(mdev, format, ...) \
841 pr_err(DRV_NAME " %s: " format, \
842 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
843 #define mlx4_info(mdev, format, ...) \
844 pr_info(DRV_NAME " %s: " format, \
845 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
846 #define mlx4_warn(mdev, format, ...) \
847 pr_warn(DRV_NAME " %s: " format, \
848 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
849
850 #endif
851