1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2022 Foundries.io Ltd 4 */ 5 6 #ifndef __DRIVERS_VERSAL_NVM_H__ 7 #define __DRIVERS_VERSAL_NVM_H__ 8 9 #include <drivers/versal_mbox.h> 10 #include <platform_config.h> 11 #include <tee_api_types.h> 12 #include <types_ext.h> 13 #include <util.h> 14 15 #define PUF_EFUSES_WORDS (128) 16 #define PUF_SYN_DATA_WORDS (127) 17 #define EFUSE_MAX_USER_FUSES (64) 18 19 #define EFUSE_OFFCHIP_REVOCATION_ID_LEN (4) 20 #define EFUSE_REVOCATION_ID_LEN (4) 21 #define EFUSE_DEC_ONLY_LEN (4) 22 #define EFUSE_DNA_LEN (16) 23 #define EFUSE_PPK_LEN (32) 24 #define EFUSE_IV_LEN (12) 25 26 enum versal_nvm_iv_type { 27 EFUSE_META_HEADER_IV_RANGE = 0, 28 EFUSE_BLACK_IV, 29 EFUSE_PLM_IV_RANGE, 30 EFUSE_DATA_PARTITION_IV_RANGE, 31 }; 32 33 enum versal_nvm_ppk_type { 34 EFUSE_PPK0 = 0, 35 EFUSE_PPK1, 36 EFUSE_PPK2 37 }; 38 39 enum versal_nvm_revocation_id { 40 EFUSE_REVOCATION_ID_0 = 0, 41 EFUSE_REVOCATION_ID_1, 42 EFUSE_REVOCATION_ID_2, 43 EFUSE_REVOCATION_ID_3, 44 EFUSE_REVOCATION_ID_4, 45 EFUSE_REVOCATION_ID_5, 46 EFUSE_REVOCATION_ID_6, 47 EFUSE_REVOCATION_ID_7 48 }; 49 50 enum versal_nvm_offchip_id { 51 EFUSE_INVLD = -1, 52 EFUSE_OFFCHIP_REVOKE_ID_0 = 0, 53 EFUSE_OFFCHIP_REVOKE_ID_1, 54 EFUSE_OFFCHIP_REVOKE_ID_2, 55 EFUSE_OFFCHIP_REVOKE_ID_3, 56 EFUSE_OFFCHIP_REVOKE_ID_4, 57 EFUSE_OFFCHIP_REVOKE_ID_5, 58 EFUSE_OFFCHIP_REVOKE_ID_6, 59 EFUSE_OFFCHIP_REVOKE_ID_7 60 }; 61 62 /* 63 * All structures mapped to the PLM processor must be address_and_size aligned 64 * to the cacheline_len. 65 */ 66 67 struct versal_efuse_glitch_cfg_bits { 68 uint8_t prgm_glitch; 69 uint8_t glitch_det_wr_lk; 70 uint32_t glitch_det_trim; 71 uint8_t gd_rom_monitor_en; 72 uint8_t gd_halt_boot_en; 73 uint8_t pad[53]; 74 }; 75 76 struct versal_efuse_aes_keys { 77 uint8_t prgm_aes_key; 78 uint8_t prgm_user_key0; 79 uint8_t prgm_user_key1; 80 uint32_t aes_key[8]; 81 uint32_t user_key0[8]; 82 uint32_t user_key1[8]; 83 uint8_t pad[25]; 84 }; 85 86 struct versal_efuse_ppk_hash { 87 uint8_t prgm_ppk0_hash; 88 uint8_t prgm_ppk1_hash; 89 uint8_t prgm_ppk2_hash; 90 uint32_t ppk0_hash[8]; 91 uint32_t ppk1_hash[8]; 92 uint32_t ppk2_hash[8]; 93 uint8_t pad[89]; 94 }; 95 96 struct versal_efuse_dec_only { 97 uint8_t prgm_dec_only; 98 uint8_t pad[63]; 99 }; 100 101 struct versal_efuse_revoke_ids { 102 uint8_t prgm_revoke_id; 103 uint32_t revoke_id[8]; 104 uint8_t pad[89]; 105 }; 106 107 struct versal_efuse_offchip_ids { 108 uint8_t prgm_offchip_id; 109 uint32_t offchip_id[8]; 110 uint8_t pad[89]; 111 }; 112 113 struct versal_efuse_user_data { 114 uint32_t start; 115 uint32_t num; 116 uint64_t addr; 117 uint8_t pad[48]; 118 }; 119 120 struct versal_efuse_puf_fuse { 121 uint8_t env_monitor_dis; 122 uint8_t prgm_puf_fuse; 123 uint32_t start; 124 uint32_t num; 125 uint64_t addr; 126 uint8_t pad[104]; 127 }; 128 129 struct versal_efuse_ivs { 130 uint8_t prgm_meta_header_iv; 131 uint8_t prgm_blk_obfus_iv; 132 uint8_t prgm_plm_iv; 133 uint8_t prgm_data_partition_iv; 134 uint32_t meta_header_iv[3]; 135 uint32_t blk_obfus_iv[3]; 136 uint32_t plm_iv[3]; 137 uint32_t data_partition_iv[3]; 138 uint8_t pad[12]; 139 }; 140 141 struct versal_efuse_misc_ctrl_bits { 142 uint8_t glitch_det_halt_boot_en; 143 uint8_t glitch_det_rom_monitor_en; 144 uint8_t halt_boot_error; 145 uint8_t halt_boot_env; 146 uint8_t crypto_kat_en; 147 uint8_t lbist_en; 148 uint8_t safety_mission_en; 149 uint8_t ppk0_invalid; 150 uint8_t ppk1_invalid; 151 uint8_t ppk2_invalid; 152 uint8_t pad[54]; 153 }; 154 155 struct versal_efuse_puf_sec_ctrl_bits { 156 uint8_t puf_regen_dis; 157 uint8_t puf_hd_invalid; 158 uint8_t puf_test2_dis; 159 uint8_t puf_dis; 160 uint8_t puf_syn_lk; 161 uint8_t pad[59]; 162 }; 163 164 struct versal_efuse_sec_misc1_bits { 165 uint8_t lpd_mbist_en; 166 uint8_t pmc_mbist_en; 167 uint8_t lpd_noc_sc_en; 168 uint8_t sysmon_volt_mon_en; 169 uint8_t sysmon_temp_mon_en; 170 uint8_t pad[59]; 171 }; 172 173 struct versal_efuse_boot_env_ctrl_bits { 174 uint8_t prgm_sysmon_temp_hot; 175 uint8_t prgm_sysmon_volt_pmc; 176 uint8_t prgm_sysmon_volt_pslp; 177 uint8_t prgm_sysmon_temp_cold; 178 uint8_t sysmon_temp_en; 179 uint8_t sysmon_volt_en; 180 uint8_t sysmon_volt_soc; 181 uint8_t sysmon_temp_hot; 182 uint8_t sysmon_volt_pmc; 183 uint8_t sysmon_volt_pslp; 184 uint8_t sysmon_temp_cold; 185 uint8_t pad[53]; 186 }; 187 188 struct versal_efuse_sec_ctrl_bits { 189 uint8_t aes_dis; 190 uint8_t jtag_err_out_dis; 191 uint8_t jtag_dis; 192 uint8_t ppk0_wr_lk; 193 uint8_t ppk1_wr_lk; 194 uint8_t ppk2_wr_lk; 195 uint8_t aes_crc_lk; 196 uint8_t aes_wr_lk; 197 uint8_t user_key0_crc_lk; 198 uint8_t user_key0_wr_lk; 199 uint8_t user_key1_crc_lk; 200 uint8_t user_key1_wr_lk; 201 uint8_t sec_dbg_dis; 202 uint8_t sec_lock_dbg_dis; 203 uint8_t boot_env_wr_lk; 204 uint8_t reg_init_dis; 205 uint8_t pad[48]; 206 }; 207 208 struct versal_efuse_puf_header { 209 struct versal_efuse_puf_sec_ctrl_bits sec_ctrl; 210 uint8_t prmg_puf_helper_data; 211 uint8_t env_monitor_dis; 212 uint32_t efuse_syn_data[PUF_SYN_DATA_WORDS]; 213 uint32_t chash; 214 uint32_t aux; 215 uint8_t pad[56]; 216 }; 217 218 struct versal_efuse_puf_user_fuse { 219 uint32_t data_addr[PUF_EFUSES_WORDS]; 220 uint8_t env_monitor_dis; 221 uint8_t prgm_puf_fuse; 222 uint32_t start_row; 223 uint32_t num_rows; 224 }; 225 226 TEE_Result versal_efuse_read_dna(uint32_t *buf, size_t len); 227 TEE_Result versal_efuse_read_user_data(uint32_t *buf, size_t len, 228 uint32_t first, size_t num); 229 TEE_Result versal_efuse_read_iv(uint32_t *buf, size_t len, 230 enum versal_nvm_iv_type type); 231 TEE_Result versal_efuse_read_ppk(uint32_t *buf, size_t len, 232 enum versal_nvm_ppk_type type); 233 TEE_Result versal_efuse_write_user_data(uint32_t *buf, size_t len, 234 uint32_t first, size_t num); 235 TEE_Result versal_efuse_write_aes_keys(struct versal_efuse_aes_keys *keys); 236 TEE_Result versal_efuse_write_ppk_hash(struct versal_efuse_ppk_hash *hash); 237 TEE_Result versal_efuse_write_iv(struct versal_efuse_ivs *p); 238 TEE_Result versal_efuse_write_dec_only(struct versal_efuse_dec_only *p); 239 TEE_Result versal_efuse_write_sec(struct versal_efuse_sec_ctrl_bits *p); 240 TEE_Result versal_efuse_write_misc(struct versal_efuse_misc_ctrl_bits *p); 241 TEE_Result versal_efuse_write_glitch_cfg(struct versal_efuse_glitch_cfg_bits 242 *p); 243 TEE_Result versal_efuse_write_boot_env(struct versal_efuse_boot_env_ctrl_bits 244 *p); 245 TEE_Result versal_efuse_write_sec_misc1(struct versal_efuse_sec_misc1_bits *p); 246 TEE_Result versal_efuse_write_offchip_ids(struct versal_efuse_offchip_ids *p); 247 TEE_Result versal_efuse_write_revoke_ppk(enum versal_nvm_ppk_type type); 248 TEE_Result versal_efuse_write_revoke_id(uint32_t id); 249 TEE_Result versal_efuse_read_revoke_id(uint32_t *buf, size_t len, 250 enum versal_nvm_revocation_id id); 251 TEE_Result versal_efuse_read_misc_ctrl(struct versal_efuse_misc_ctrl_bits *buf); 252 TEE_Result versal_efuse_read_sec_ctrl(struct versal_efuse_sec_ctrl_bits *buf); 253 TEE_Result versal_efuse_read_sec_misc1(struct versal_efuse_sec_misc1_bits *buf); 254 TEE_Result 255 versal_efuse_read_boot_env_ctrl(struct versal_efuse_boot_env_ctrl_bits *buf); 256 TEE_Result versal_efuse_read_offchip_revoke_id(uint32_t *buf, size_t len, 257 enum versal_nvm_offchip_id id); 258 TEE_Result versal_efuse_read_dec_only(uint32_t *buf, size_t len); 259 TEE_Result versal_efuse_read_puf_sec_ctrl(struct versal_efuse_puf_sec_ctrl_bits 260 *buf); 261 TEE_Result versal_efuse_read_puf(struct versal_efuse_puf_header *buf); 262 TEE_Result versal_efuse_read_puf_as_user_fuse(struct versal_efuse_puf_user_fuse 263 *p); 264 TEE_Result versal_efuse_write_puf_as_user_fuse(struct versal_efuse_puf_user_fuse 265 *p); 266 TEE_Result versal_efuse_write_puf(struct versal_efuse_puf_header *buf); 267 TEE_Result versal_bbram_write_aes_key(uint8_t *key, size_t len); 268 TEE_Result versal_bbram_zeroize(void); 269 TEE_Result versal_bbram_write_user_data(uint32_t data); 270 TEE_Result versal_bbram_read_user_data(uint32_t *data); 271 TEE_Result versal_bbram_lock_write_user_data(void); 272 273 #endif /*__DRIVERS_VERSAL_NVM_H__*/ 274