1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef DDR_INIT_H
9 #define DDR_INIT_H
10 
11 #include "synquacer_mmap.h"
12 
13 #include <internal/reg_DDRPHY_CONFIG.h>
14 #include <internal/reg_DMC520.h>
15 
16 #include <fwk_log.h>
17 
18 #include <fmw_cmsis.h>
19 
20 #include <stdbool.h>
21 #include <stdint.h>
22 
23 #define printf(...) FWK_LOG_INFO("[DDR] " __VA_ARGS__)
24 #define pr_err(...) FWK_LOG_ERR("[DDR] " __VA_ARGS__)
25 
26 #define dmb __DMB
27 
28 #define REG_DDRPHY_CONFIG_0_BA UINT32_C(0x7F210000)
29 #define REG_DDRPHY_CONFIG_1_BA UINT32_C(0x7F610000)
30 
31 #define REG_DMC520_0_BA UINT32_C(0x4E000000)
32 #define REG_DMC520_1_BA UINT32_C(0x4E100000)
33 #define REG_DMC520_3_BA UINT32_C(0x4E300000)
34 
35 #define DDR_TRAINING_ON
36 #define DDR_DQSTRAINWA_ON
37 #define DDR_WAIT_TIMEOUT_US UINT32_C(1000000)
38 
39 extern int ddr_dual_ch_init_mp(void);
40 extern int ddr_ch0_init_mp(void);
41 extern int ddr_ch1_init_mp(void);
42 extern uint8_t ddr_is_secure_dram_enabled(void);
43 
44 #endif /*DDR_INIT_H */
45