1 /** 2 ****************************************************************************** 3 * @file rtl8721d_psram.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the PSRAM firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8710B_PSRAM_H 20 #define _RTL8710B_PSRAM_H 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup PSRAM 27 * @brief PSRAM driver modules 28 * @{ 29 */ 30 31 /** @addtogroup PSRAM 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * PSRAM_Controller is used to communicate with PSRAM 37 * PSRAM: 38 * - IPclk: 50Mhz 39 * - Memory Size: 32M bits 40 * - Address Mapping: 0x0200_0000 ~ 0x0240_0000 41 * - Access: direct access or dpin mode 42 * - IRQ: PSRAMC_IRQ 43 * - GDMA: Support 44 * 45 ***************************************************************************************** 46 * How to use PSRAM_Controller to direct access PSRAM memory 47 ***************************************************************************************** 48 * To direct access PSRAM memory, the following steps are mandatory: 49 * 50 * 1. Program read/write Latency, access mode, refresh_rate 51 * PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct) 52 * 53 * 2. Init Hardware use step1 parameters: 54 * PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct) 55 * 56 * 3. Calibration the best rwds delay line: 57 * PSRAM_calibration() 58 * 59 * 4. Access PSRAM memory normally 60 * 61 ***************************************************************************************** 62 * How to use PSRAM_Controller to access PSRAM by Dpin mode 63 ***************************************************************************************** 64 * To access PSRAM by Dpin mode, the following steps are mandatory: 65 * 66 * 1. Program read/write Latency, access mode, refresh_rate 67 * PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct) 68 * 69 * 2. Init Hardware use step1 parameters: 70 * PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct) 71 * 72 * 3. Calibration the best rwds delay line: 73 * PSRAM_calibration() 74 * 75 * 4. Generate PSRAM command address value for dpin mode 76 * PSRAM_CTRL_CA_Gen() 77 * 78 * 5. Access PSRAM memory/registers by dpin mode 79 * PSRAM_CTRL_DPin_Mem():Access PSRAM memory 80 * PSRAM_CTRL_DPin_Reg():Access PSRAM register 81 * 82 * @note: Cache should be disable during DPIN mode 83 * 84 ***************************************************************************************** 85 * How to use PSRAM_Controller to access PSRAM by DMA mode 86 ***************************************************************************************** 87 * To access PSRAM by DMA mode, the following steps are mandatory: 88 * 89 * 1. Program read/write Latency, access mode, refresh_rate 90 * PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct) 91 * 92 * 2. Init Hardware use step1 parameters: 93 * PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct) 94 * 95 * 3. Calibration the best rwds delay line: 96 * PSRAM_calibration() 97 * 98 * 4. Alloc a free channel for PSRAM GDMA and register GDMA IRQ callback function and data 99 * GDMA_ChnlAlloc() 100 * 101 * 5. GDMA related configurations(source address/destination address/block size etc.) 102 * GDMA_StructInit():Fills GDMA_InitStruct member with its default value 103 * GDMA_Init():Init GDMA 104 * GDMA_BurstEnable():Enable GDMA Burst Transmission 105 * 106 * 6. Active the PSRAM DMA Request using the function GDMA_Cmd() 107 * 108 * @note: The Maximum Msize of Channel0 is different from other Channels 109 * Maximum Msize of Channel0 is 256 110 * Maximum Msize of Channel1 ~ Channel5 is 8 111 * 112 * @endverbatim 113 */ 114 115 /* Exported types ------------------------------------------------------------*/ 116 117 /** @defgroup PSRAM_Exported_Types PSRAM Exported Types 118 * @{ 119 */ 120 121 /** 122 * @brief PSRAM Init structure definition 123 */ 124 typedef struct { 125 u8 PCTL_dfi_cs_wr_dly; /*!< Specifies the latency contrast between PHY write data path latency 126 and PHY command path latency. 127 This parameter must be set to a value in the 0-15 range */ 128 u8 PCTL_dfi_cs_rd_dly; /*!< Specifies the latency contrast between PHY read data enable path 129 latency and PHY command path latency . 130 This parameter must be set to a value in the 0-15 range */ 131 u8 PCTL_tphy_wrdata; /*!< Specifies the delay latency from DFI write command to DFI write data. 132 This parameter is proposed to set PCTL_wl+2 */ 133 u8 PCTL_fix_tphy_lat; /*!< Specifies thePSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only . 134 This parameter can be a value of @ref PSRAM_TPHY_LAT_definitions */ 135 u8 PCTL_tphy_rddata; /*!< Specifies the delay latency from DFI read command to DFI read data. 136 This parameter is proposed to set PCTL_rl+3 */ 137 u8 PCTL_dfi_path_dly; /*!< Specifies which TPHY_WRATA/TPHY_RDDATA cycle to sample DFI latency. 138 This parameter is proposed to set PCTL_wl */ 139 u8 PCTL_wl; /*!< Specifies the PSRAM write latency . 140 This parameter must be set to a value in the 3-6 range */ 141 u8 PCTL_rl; /*!< Specifies the PSRAM read latency. 142 This parameter must be set to a value in the 3-6 range */ 143 u32 PCTL_tcph_ps; /*!< Specifies the PSRAM CE# pin HIGH cycles between subsequent command. 144 This parameter unit is ps */ 145 u32 PCTL_tpu_ps; /*!< Specifies the time between access PSRAM and RESET# pin high. 146 This parameter unit is ps */ 147 u32 PCTL_tcem_ps; /*!< Specifies the maximum average Refresh commands delay cycles. 148 This parameter unit is ps */ 149 u32 PCTL_clk_ps; /*!< Specifies the PSRAM clock cycle. 150 This parameter unit is ps */ 151 u8 PCTL_mr0_burst_len; /*!< Specifies the PSRAM burst length. 152 This parameter can be a value of @ref PSRAM_BURST_LENGTH_definitions */ 153 u8 PCTL_mr0_burst_type; /*!< Specifies the PSRAM wrapped burst type. 154 This parameter can be a value of @ref PSRAM_BURST_TYPE_definitions */ 155 u8 PCTL_mr0_lat_mode; /*!< Specifies the PSRAM whether fix latency. 156 This parameter can be a value of @ref PSRAM_LATENCY_MODE_definitions */ 157 u8 PCTL_mr0_init_lat; /*!< Specifies the PSRAM initial latency. 158 This parameter can be a value of @ref PSRAM_INIT_LATENCY_definitions */ 159 u8 PCTL_mr0_drv_strength; /*!< Specifies the PSRAM drive strength. 160 This parameter can be a value of @ref PSRAM_DRV_STRENGTH_definitions */ 161 u8 PCTL_mr0_dpd_en; /*!< Specifies the PSRAM whether enter deep power pown. 162 This parameter can be a value of @ref PSRAM_DPD_definitions */ 163 u8 PCTL_mr1_pasr; /*!< Specifies the PSRAM partial array self refresh. 164 This parameter can be a value of @ref PSRAM_PASR_definitions */ 165 u8 PCTL_mr1_half_slp; /*!< Specifies the PSRAM half sleep mode set. 166 This parameter can be a value of @ref PSRAM_HALF_SLP_definitions */ 167 u8 PCTL_mr1_refresh_rate; /*!< Specifies the PSRAM refresh rate. 168 This parameter can be a value of @ref PSRAM_REFRESH_RATE_definitions */ 169 } PCTL_InitTypeDef; 170 /** 171 * @} 172 */ 173 174 /* Exported constants --------------------------------------------------------*/ 175 176 /** @defgroup PSRAM_Exported_Constants PSRAM Exported Constants 177 * @{ 178 */ 179 180 /** @defgroup PSRAM_Peripheral_definitions 181 * @{ 182 */ 183 #define IS_PSRAM_ALL_PERIPH(PERIPH) ((PERIPH) == PSRAM_DEV) 184 /** 185 * @} 186 */ 187 188 /** @defgroup PSRAM_TPHY_LAT_definitions 189 * @{ 190 */ 191 #define PSRAM_FIX_TPHY_LATENCY 1 192 #define PSRAM_UNSET_TPHY_LATENCY 0 193 /** 194 * @} 195 */ 196 197 /** @defgroup PSRAM_BURST_LENGTH_definitions 198 * @{ 199 */ 200 #define PSRAM_BURST_LENGTH_128B 0 201 #define PSRAM_BURST_LENGTH_64B 1 202 #define PSRAM_BURST_LENGTH_16B 2 203 #define PSRAM_BURST_LENGTH_32B 3 204 /** 205 * @} 206 */ 207 208 /** @defgroup PSRAM_BURST_TYPE_definitions 209 * @{ 210 */ 211 #define PSRAM_BURST_VENDOR_TYPE 0 212 #define PSRAM_BURST_LEGACY_TYPE 1 213 /** 214 * @} 215 */ 216 217 /** @defgroup PSRAM_LATENCY_MODE_definitions 218 * @{ 219 */ 220 #define PSRAM_2TIMES_LATENCY_FIXED 1 221 #define PSRAM_VARIABLE_LATENCY 0 222 /** 223 * @} 224 */ 225 226 /** @defgroup PSRAM_INIT_LATENCY_definitions 227 * @{ 228 */ 229 #define PSRAM_INIT_LATENCY_5CLK 0 230 #define PSRAM_INIT_LATENCY_6CLK 1 231 #define PSRAM_INIT_LATENCY_3CLK 0xe 232 #define PSRAM_INIT_LATENCY_4CLK 0xf 233 /** 234 * @} 235 */ 236 237 /** @defgroup PSRAM_DRV_STRENGTH_definitions 238 * @{ 239 */ 240 #define PSRAM_DRV_STRENGTH_50OHMS 0 241 #define PSRAM_DRV_STRENGTH_35OHMS 1 242 #define PSRAM_DRV_STRENGTH_100OHMS 2 243 #define PSRAM_DRV_STRENGTH_200OHMS 3 244 /** 245 * @} 246 */ 247 248 /** @defgroup PSRAM_DPD_definitions 249 * @{ 250 */ 251 #define PSRAM_DPD_MODE 0 252 #define PSRAM_NORMAL_MODE 1 253 /** 254 * @} 255 */ 256 257 /** @defgroup PSRAM_PASR_definitions 258 * @{ 259 */ 260 #define PSRAM_PASR_FULL_ARRAY 0 261 #define PSRAM_PASR_BOT_HALF_ARRAY 1 262 #define PSRAM_PASR_BOT_QUARTER_ARRAY 2 263 #define PSRAM_PASR_BOT_EIGHTH_ARRAY 3 264 #define PSRAM_PASR_NONE 4 265 #define PSRAM_PASR_TOP_HALF_ARRAY 5 266 #define PSRAM_PASR_TOP_QUARTER_ARRAY 6 267 #define PSRAM_PASR_TOP_EIGHTH_ARRAY 7 268 /** 269 * @} 270 */ 271 272 /** @defgroup PSRAM_HALF_SLP_definitions 273 * @{ 274 */ 275 #define PSRAM_HALF_SLP_DIS 0 276 #define PSRAM_HALF_SLP_EN 1 277 /** 278 * @} 279 */ 280 281 /** @defgroup PSRAM_REFRESH_RATE_definitions 282 * @{ 283 */ 284 #define PSRAM_REFRESH_RATE_FAST 0 285 #define PSRAM_REFRESH_RATE_NORMAL 1 286 /** 287 * @} 288 */ 289 290 /** @defgroup PSRAM_BURST_TYPE_definitions 291 * @{ 292 */ 293 #define PSRAM_WRAPPED_TYPE 0 294 #define PSRAM_LINEAR_TYPE 1 295 #define IS_PSRAM_BURST_TYPE(TYPE) (((TYPE) == PSRAM_WRAPPED_TYPE) || \ 296 ((TYPE) == PSRAM_LINEAR_TYPE)) 297 /** 298 * @} 299 */ 300 301 /** @defgroup PSRAM_ADDR_SPACE_definitions 302 * @{ 303 */ 304 #define PSRAM_MEM_SPACE 0 305 #define PSRAM_REG_SPACE 1 306 #define IS_PSRAM_ADDR_SPACE(MODE) (((MODE) == PSRAM_MEM_SPACE) || \ 307 ((MODE) == PSRAM_REG_SPACE)) 308 /** 309 * @} 310 */ 311 312 /** @defgroup PSRAM_WR_TRANSACTION_definitions 313 * @{ 314 */ 315 #define PSRAM_WRITE_TRANSACTION 0 316 #define PSRAM_READ_TRANSACTION 1 317 #define IS_PSRAM_WR_TRANSACTION(MODE) (((MODE) == PSRAM_WRITE_TRANSACTION) || \ 318 ((MODE) == PSRAM_READ_TRANSACTION)) 319 /** 320 * @} 321 */ 322 323 324 /** @defgroup PSRAM_DPIN_WR_MODE_definitions 325 * @{ 326 */ 327 #define PSRAM_DPIN_READ_MODE 0 << 17 328 #define PSRAM_DPIN_WRITE_MODE 1 << 17 329 330 /** 331 * @} 332 */ 333 334 335 336 /** 337 * @} 338 */ 339 340 /* Exported functions --------------------------------------------------------*/ 341 /** @defgroup PSRAM_Exported_Functions PSRAM Exported Functions 342 * @{ 343 */ 344 _LONG_CALL_ void PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct); 345 _LONG_CALL_ void PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct); 346 _LONG_CALL_ void PSRAM_CTRL_CA_Gen(u8* PSRAM_CA, u32 StartAddr, u8 BurstType, u8 AddSpace, u8 RW); 347 _LONG_CALL_ void PSRAM_CTRL_DPin_Mem(u8* PSRAM_CA, u32* PSRAM_data, u32 PSRAM_byteen, u8 RW); 348 _LONG_CALL_ void PSRAM_CTRL_DPin_Reg(u8* PSRAM_CA, u32* PSRAM_data, u8 RW); 349 _LONG_CALL_ u32 PSRAM_PHY_REG_Read(u8 offset); 350 _LONG_CALL_ void PSRAM_PHY_REG_Write(u8 offset, u32 reg_val); 351 _LONG_CALL_ BOOL PSRAM_calibration(VOID); 352 /** 353 * @} 354 */ 355 356 /* Registers Definitions --------------------------------------------------------*/ 357 /** @defgroup PSRAM_Register_Definitions PSRAM Register Definitions 358 * @{ 359 */ 360 /**************************************************************************//** 361 * @defgroup PSRAM_CCR 362 * @{ 363 *****************************************************************************/ 364 /******************** Bits definition for CCR register *******************/ 365 #define BIT_PSRAM_CR_UPDATE ((u32)0x00000001 << 31) /*Bit[31],bit for update the internal timing/control registers or Quick INIT done*/ 366 #define BIT_PSRAM_FLUSH_FIFO ((u32)0x00000001 << 8) /*Bit[8],bit for flush all FIFO in PSRAM_LPC_CTRL*/ 367 #define BIT_PSRAM_DPIN ((u32)0x00000001 << 3) /*Bit[3],bit for start to set PSRAM command function*/ 368 #define BIT_PSRAM_INIT ((u32)0x00000001) /*Bit[0],bit for start to issue PSRAM initialization sequence*/ 369 /** @} */ 370 371 /**************************************************************************//** 372 * @defgroup PSRAM_DCR 373 * @{ 374 *****************************************************************************/ 375 /******************** Bits definition for DCR register *******************/ 376 #define BIT_PSRAM_AADMUX ((u32)0x00000001 << 20) /*Bit[20], bit for indicate the target PSRAM is AADMUX type or ADMUX or mormal type*/ 377 #define BIT_PSRAM_PAGE_SIZE ((u32)0x0000000f << 16) /*Bit[19:16], bits for indicate the target PSRAM page size*/ 378 #define BIT_PSRAM_SUSPEND_EN ((u32)0x00000001 << 9) /*Bit[9], bit for indicate PSRAM_CTRL support SUSPEND command*/ 379 #define BIT_PSRAM_CLK_EN ((u32)0x00000001 << 8) /*Bit[8], bit for indicate PSRAM at asynchronous mode clock enable*/ 380 #define BIT_PSRAM_CRE_EN ((u32)0x00000001 << 7) /*Bit[7], bit for indicate access PSRAM register mode*/ 381 #define BIT_PSRAM_DFI_RATE ((u32)0x00000007 << 4) /*Bit[6:4], bits for set DFI ratio*/ 382 #define BIT_PSRAM_DDR_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for indicate the PSRAM work at DDR mode or SDR mode*/ 383 #define BIT_PSRAM_ASYNC_MODE ((u32)0x00000001 << 2) /*Bit[2], bit for indicate the PSRAM work at asynchronous mode or synchronous mode*/ 384 #define BIT_PSRAM_DQ ((u32)0x00000003) /*Bit[1:0], bits for set the PSRAM architecture*/ 385 /** @} */ 386 387 /**************************************************************************//** 388 * @defgroup PSRAM_IOCR0 389 * @{ 390 *****************************************************************************/ 391 /******************** Bits definition for IOCR0 register *******************/ 392 #define BIT_PSRAM_DFI_PATH_DLY_MASK ((u32)0x0000001f << 25) /*Bit[29:25], bits for select which TPHY_WRATA/TPHY_RDDATA cycle to sample dfi_latency_en*/ 393 #define BIT_PSRAM_DFI_PATH_DLY_SHIFT 25 394 #define BIT_PSRAM_TPHY_RDDATA_EN_MASK ((u32)0x0000001f << 20) /*Bit[24:20], bits for setting the delay latency from DFI read command to dfi_rddata_en signal*/ 395 #define BIT_PSRAM_TPHY_RDDATA_EN_SHIFT 20 396 #define BIT_PSRAM_FIX_TPHY_LAT_MASK ((u32)0x00000001 << 19) /*Bit[19], bit for PSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only*/ 397 #define BIT_PSRAM_FIX_TPHY_LAT_SHIFT 19 398 #define BIT_PSRAM_TPHY_WRDATA_MASK ((u32)0x0000001f << 12) /*Bit[16:12], bits for setting the delay latency from DFI write command to DFI write data*/ 399 #define BIT_PSRAM_TPHY_WRDATA_SHIFT 12 400 #define BIT_PSRAM_RD_PIPE_MASK ((u32)0x0000000f << 8) /*Bit[11:8], bits for SDR mode read data delay setting*/ 401 #define BIT_PSRAM_RD_PIPE_SHIFT 8 402 #define BIT_PSRAM_DFI_CS_RD_DLY_MASK ((u32)0x0000000f << 4) /*Bit[7:4], bits for setting the latency contrast between PHY write data path latency and 403 PHY command path latency*/ 404 #define BIT_PSRAM_DFI_CS_RD_DLY_SHIFT 4 405 #define BIT_PSRAM_DFI_CS_WR_DLY_MASK ((u32)0x0000000f) /*Bit[3:0], bits for setting the latency contrast between PHY read data enable path latency 406 and PHY command path latency*/ 407 #define BIT_PSRAM_DFI_CS_WR_DLY_SHIFT 0 408 /** @} */ 409 410 /**************************************************************************//** 411 * @defgroup PSRAM_CSR 412 * @{ 413 *****************************************************************************/ 414 /******************** Bits definition for CSR register *******************/ 415 #define BIT_PSRAM_DPIN_MODE ((u32)0x00000003 << 17) /*Bit[18:17], bit for DPIN mode decode*/ 416 #define BIT_PSRAM_MEM_IDLE ((u32)0x00000001 << 8) /*Bit[8], bit for disable memory access state*/ 417 /** @} */ 418 419 /**************************************************************************//** 420 * @defgroup PSRAM_DRR 421 * @{ 422 *****************************************************************************/ 423 /******************** Bits definition for DRR register *******************/ 424 #define BIT_PSRAM_PU_TIME_MASK ((u32)0x0000007f << 15) /*Bit[21:15], bits for If non-defined CR_INTI_RMBIT configuration*/ 425 #define BIT_PSRAM_PU_TIME_SHIFT 15 426 #define BIT_PSRAM_CEM_TIME_MASK ((u32)0x000007ff << 4) /*Bit[14:4], bits for Maximum average Refresh commands delay cycles*/ 427 #define BIT_PSRAM_CEM_TIME_SHIFT 4 428 #define BIT_PSRAM_CPH_TIME_MASK ((u32)0x0000000f) /*Bit[3:0], bits for PSRAM CE# pin HIGH cycles between subsequent command*/ 429 #define BIT_PSRAM_CPH_TIME_SHIFT 0 430 /** @} */ 431 432 /**************************************************************************//** 433 * @defgroup PSRAM_CMD_DPIN_NDGE 434 * @{ 435 *****************************************************************************/ 436 /******************** Bits definition for CMD_DPIN_NDGE register *******************/ 437 #define BIT_PSRAM_DPIN_ADDR_NDGE ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at negative edge*/ 438 /** @} */ 439 440 /**************************************************************************//** 441 * @defgroup PSRAM_CMD_DPIN 442 * @{ 443 *****************************************************************************/ 444 /******************** Bits definition for CMD_DPIN register *******************/ 445 #define BIT_PSRAM_DPIN_ADDR_POSI ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at positive edge*/ 446 /** @} */ 447 448 /**************************************************************************//** 449 * @defgroup PSRAM_CR_TDPIN 450 * @{ 451 *****************************************************************************/ 452 /******************** Bits definition for CR_TDPIN register *******************/ 453 #define BIT_PSRAM_DFI_RESET_N ((u32)0x00000001) /*Bit[0], bit for set the PSRAM TDPIN register value*/ 454 /** @} */ 455 456 /**************************************************************************//** 457 * @defgroup PSRAM_MR_INFO 458 * @{ 459 *****************************************************************************/ 460 /******************** Bits definition for MR_INFO register *******************/ 461 #define BIT_PSRAM_RL_LATENCY_MASK ((u32)0x0000001f << 5) /*Bit[9:5], bits for indicate PSRAM read latency counter*/ 462 #define BIT_PSRAM_RL_LATENCY_SHIFT 5 463 #define BIT_PSRAM_WL_LATENCY_MASK ((u32)0x0000001f) /*Bit[4:0], bits for indicate PSRAM write latency counter*/ 464 #define BIT_PSRAM_WL_LATENCY_SHIFT 0 465 /** @} */ 466 467 /**************************************************************************//** 468 * @defgroup PSRAM_MR0 469 * @{ 470 *****************************************************************************/ 471 /******************** Bits definition for MR0 register *******************/ 472 #define BIT_PSRAM_MR0_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR0 register in initialization flow*/ 473 #define BIT_PSRAM_MR0_BURST_DPD_MODE_MASK ((u32)0x00000001) 474 #define BIT_PSRAM_MR0_BURST_DPD_MODE_SHIFT 15 475 #define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_MASK ((u32)0x00000007) 476 #define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_SHIFT 12 477 #define BIT_PSRAM_MR0_BURST_RSVD_MASK ((u32)0x0000000f) 478 #define BIT_PSRAM_MR0_BURST_RSVD_SHIFT 8 479 #define BIT_PSRAM_MR0_BURST_INIT_LAT_MASK ((u32)0x0000000f) 480 #define BIT_PSRAM_MR0_BURST_INIT_LAT_SHIFT 4 481 #define BIT_PSRAM_MR0_BURST_LAT_MODE_MASK ((u32)0x00000001) 482 #define BIT_PSRAM_MR0_BURST_LAT_MODE_SHIFT 3 483 #define BIT_PSRAM_MR0_BURST_TYPE_MASK ((u32)0x00000001) 484 #define BIT_PSRAM_MR0_BURST_TYPE_SHIFT 2 485 #define BIT_PSRAM_MR0_BURST_LENGTH_MASK ((u32)0x00000003) 486 #define BIT_PSRAM_MR0_BURST_LENGTH_SHIFT 0 487 /** @} */ 488 489 /**************************************************************************//** 490 * @defgroup PSRAM_MR1 491 * @{ 492 *****************************************************************************/ 493 /******************** Bits definition for MR1 register *******************/ 494 #define BIT_PSRAM_MR1_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR1 register in initialization flow*/ 495 #define BIT_PSRAM_MR1_REFRESH_RATE_MASK ((u32)0x00000001) 496 #define BIT_PSRAM_MR1_REFRESH_RATE_SHIFT 6 497 #define BIT_PSRAM_MR1_HALF_SLP_MODE_MASK ((u32)0x00000001) 498 #define BIT_PSRAM_MR1_HALF_SLP_MODE_SHIFT 5 499 #define BIT_PSRAM_MR1_PASR_MASK ((u32)0x00000007) 500 #define BIT_PSRAM_MR1_PASR_SHIFT 0 501 /** @} */ 502 503 /**************************************************************************//** 504 * @defgroup PSRAM_DPDRI 505 * @{ 506 *****************************************************************************/ 507 /******************** Bits definition for DPDRI register *******************/ 508 #define BIT_PSRAM_DPIN_DATA_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for indicate select which DPIN DATA register .*/ 509 /** @} */ 510 511 /**************************************************************************//** 512 * @defgroup PSRAM_DPDR 513 * @{ 514 *****************************************************************************/ 515 /******************** Bits definition for DPDR register *******************/ 516 #define BIT_PSRAM_DPIN_DATA ((u32)0xffffffff) /*Bit[31:0], bits for indicate the data which will be written to PSRAM or the data 517 read from PSRAM.*/ 518 /** @} */ 519 520 /**************************************************************************//** 521 * @defgroup PSRAM_PCTL_SVN_ID 522 * @{ 523 *****************************************************************************/ 524 /******************** Bits definition for PCTL_SVN_ID register *******************/ 525 #define BIT_PSRAM_CTRL_GIT_CNT ((u32)0x0000ffff << 16) /*Bit[31:16], bits for indicate the Git counter of the released RTL code.*/ 526 #define BIT_PSRAM_CTRL_RELEASE_DATE ((u32)0x0000ffff) /*Bit[15:0], bits for indicate the IP release date for the particular project.*/ 527 /** @} */ 528 529 /**************************************************************************//** 530 * @defgroup PSRAM_PCTL_IDR 531 * @{ 532 *****************************************************************************/ 533 /******************** Bits definition for PCTL_IDR register *******************/ 534 #define BIT_PSRAM_CTRL_CR_VER ((u32)0x0000ffff << 16) /*Bit[31:16], bits for control register version number.*/ 535 #define BIT_PSRAM_CTRL_CR_PCTL_DEF ((u32)0x0000ffff) /*Bit[15:0], bits for user definition or support PSRAM type.*/ 536 /** @} */ 537 538 /** 539 * @} 540 */ 541 /** 542 * @} 543 */ 544 545 /** 546 * @} 547 */ 548 549 /******************** Bits definition for REG_PSRAM_CAL_CTRL register *******************/ 550 #define BIT_PSRAM_CFG_CAL_INTR ((u32)0x00000001 << 16) /*Bit[16], bit for Interrupt flag raised by calibration.*/ 551 #define BIT_PSRAM_CFG_CAL_INTR_MASK ((u32)0x00000001 << 8) /*Bit[8], bit for Calibration fail interrupt mask.*/ 552 #define BIT_PSRAM_CFG_CAL_THD_MASK ((u32)0x0000000f) /*Bit[7:4], bits for Error check threshold value , used as a filter*/ 553 #define BIT_PSRAM_CFG_CAL_THD_SHIFT 4 554 #define BIT_PSRAM_CFG_CAL_EN ((u32)0x00000001) /*Bit[0], bit for Hardware auto calibration enable.*/ 555 556 /******************** Bits definition for REG_PSRAM_CAL_PARA register *******************/ 557 #define BIT_PSRAM_CFG_CAL_JMIN_MASK ((u32)0x00000007) /*Bit[26:24], bits for Minimum J.*/ 558 #define BIT_PSRAM_CFG_CAL_JMIN_SHIFT 24 559 #define BIT_PSRAM_CFG_CAL_JMAX_MASK ((u32)0x0000000f) /*Bit[19:16], bits for Maximum J.*/ 560 #define BIT_PSRAM_CFG_CAL_JMAX_SHIFT 16 561 #define BIT_PSRAM_CFG_CAL_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Initial value J calibrated by software.*/ 562 #define BIT_PSRAM_CFG_CAL_J_SHIFT 8 563 #define BIT_PSRAM_CFG_CAL_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Initial value N calibrated by software.*/ 564 #define BIT_PSRAM_CFG_CAL_N_SHIFT 0 565 566 /******************** Bits definition for REG_PSRAM_CAL_STATUS register *******************/ 567 #define BIT_PSRAM_CFG_CAL_CUR_ST_MASK ((u32)0x0000001f) /*Bit[28:24], bits for Calibration current state.*/ 568 #define BIT_PSRAM_CFG_CAL_CUR_ST_SHIFT 24 569 #define BIT_PSRAM_CFG_CAL_PDST_MASK ((u32)0x00000007) /*Bit[18:16], bits for Calibration check result for last read burst.*/ 570 #define BIT_PSRAM_CFG_CAL_PDST_SHIFT 16 571 #define BIT_PSRAM_CFG_CAL_CUR_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Current value J read from hardware.*/ 572 #define BIT_PSRAM_CFG_CAL_CUR_J_SHIFT 8 573 #define BIT_PSRAM_CFG_CAL_CUR_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Current value N read from hardware.*/ 574 #define BIT_PSRAM_CFG_CAL_CUR_N_SHIFT 0 575 576 /******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_L register *******************/ 577 #define BIT_PSRAM_CMD_ADDR_INFO_L_MASK ((u32)0xffffffff) /*Bit[31:0], bits for Command/Address information[31:0].*/ 578 579 /******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_H register *******************/ 580 #define BIT_PSRAM_CMD_ADDR_INFO_H_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for Command/Address information[47:32].*/ 581 582 /******************** Bits definition for REG_PSRAM_BYTE_CNT_INFO register *******************/ 583 #define BIT_PSRAM_WBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[31:24], bits for length of write data given by psram controller, will be cleared at the end of this Transaction.*/ 584 #define BIT_PSRAM_WBYTE_ACCU_SHIFT 24 585 #define BIT_PSRAM_WBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[23:16], bits for length of data written to psram controller, will be cleared at the end of this Transaction.*/ 586 #define BIT_PSRAM_WBYTE_CNT_SHIFT 16 587 #define BIT_PSRAM_RBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[15:8], bits for length of read data given by psram controller, will be cleared at the beginning of next Transaction.*/ 588 #define BIT_PSRAM_RBYTE_ACCU_SHIFT 8 589 #define BIT_PSRAM_RBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[7:0], bits for length of data read from psram controller, will be cleared at the beginning of next Transaction.*/ 590 #define BIT_PSRAM_RBYTE_CNT_SHIFT 0 591 592 /******************** Bits definition for REG_PSRAM_TIME_OUT_CTRL register *******************/ 593 #define BIT_PSRAM_TIME_OUT_INTR ((u32)0x00000001 << 31) /*Bit[31], bit for read transaction time out interrupt flag.*/ 594 #define BIT_PSRAM_TIME_OUT_INTR_MASK ((u32)0x00000001 << 23) /*Bit[23], bit for read transaction time out interrupt mask.*/ 595 #define BIT_PSRAM_TIME_OUT_THOLD_MASK ((u32)0x000000ff) /*Bit[7:0], bits for read transaction time out threshold.*/ 596 #define BIT_PSRAM_TIME_OUT_THOLD_SHIFT 0 597 598 /******************** Bits definition for REG_PSRAM_DBG_SEL register *******************/ 599 #define BIT_PSRAM_PSRAM_PHY_DBG_SEL_MASK ((u32)0xff) /*Bit[7:0], bits for psram phy debug select signal.*/ 600 #define BIT_PSRAM_PSRAM_PHY_DBG_SEL_SHIFT 0 601 602 /******************** Bits definition for REG_PSRAM_DBG_INFO register *******************/ 603 #define BIT_PSRAM_PSRAM_PHY_DBG_MASK ((u32)0xffffffff) /*Bit[31:0], bits for psram phy debug signals.*/ 604 #define BIT_PSRAM_PSRAM_PHY_DBG_SHIFT 0 605 606 /******************** PSRAM PHY register *******************/ 607 #define REG_PSRAM_CAL_CTRL 0x000 /*!< PSRAM PHY Calibration control register */ 608 #define REG_PSRAM_CAL_PARA 0x004 /*!< PSRAM PHY Calibration parameter register*/ 609 #define REG_PSRAM_CAL_STATUS 0x008 /*!< PSRAM PHY Calibration status register*/ 610 #define REG_PSRAM_CMD_ADDR_INFO_L 0x010 /*!< PSRAM Command/address information register[31:0]*/ 611 #define REG_PSRAM_CMD_ADDR_INFO_H 0x014 /*!< PSRAM Command/address information register[48:32]*/ 612 #define REG_PSRAM_BYTE_CNT_INFO 0x018 /*!< PSRAM Byte Counts register*/ 613 #define REG_PSRAM_TIME_OUT_CTRL 0x01C /*!< PSRAM Timeout Control register*/ 614 #define REG_PSRAM_DBG_SEL 0x0F0 /*!< PSRAM Debug select register*/ 615 #define REG_PSRAM_DBG_INFO 0x0F8 /*!< PSRAM Debug information register*/ 616 617 /* Other definations --------------------------------------------------------*/ 618 619 typedef struct 620 { 621 u32 psram_dev_enable; /*enable psram*/ 622 u32 psram_dev_cal_enable; /*enable psram calibration function*/ 623 u32 psram_dev_retention; /*enable psram retention when km4 enter low power mode*/ 624 u32 psram_heap_start_address; /*config psram heap start address*/ 625 u32 psram_heap_size; /*config psram heap size*/ 626 } PSRAMCFG_TypeDef; 627 628 extern PSRAMCFG_TypeDef psram_dev_config; 629 630 #endif //_RTL8710B_PSRAM_H 631 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 632